SU752738A1 - Method of controlling operation of m-phase pulse-width dc converters - Google Patents

Description

one

The invention relates to a technique for controlling the operation of thyristor-pulse converters of direct current.

A known method for controlling thyristors of multiphase pulse-width transducers of direct current, which consists in the fact that the duration of the on state tO of the thyristors of each phase varies throughout the entire control range with a shift in the work of the phase stage by the switching period (t is the number of phases of the converter) one . . 15

The closest technical solution to the present invention is a method for controlling thyristors of multiphase transducers, consisting in a discrete change in the duration, 20 of the on state of the thyristors of each phase in the entire control range with a shift in the operation of each phase, by. adjustment period 2.

However, this method of controlling the operation of thyristors of multiphase transducers requires the construction of diode arrays of decoders for all states of clock and reversible counter triggers in order to ensure

neither the regulation of each phase in the whole range of regulation, which requires a large number of decoder elements, leading to an excessive power consumption, a decrease in reliability and an increase in volume and cost,

H

The purpose of the invention is to simplify the control system of m-phase pulse-width converters.

This goal is achieved by the fact that in the process of changing the duration of the turn-off state of the thyristors, the thyristor control channels of each phase are transmitted when the limit value of the control zone of each control channel is reached.

The limiting value of the range of variation of the fill factor of the channel for adjusting each phase with the proposed control method is equal to A / li / rn

or the range of adjustment of the fill factor of each channel is: 1st - lt,} I-ro-u / l i / / nn n-a / li / m; w -ro-ii / if5j iS / mfi m |

the latter is / k / lim () / V, for example, when controlling the 1 st phase. FIG. 1 is a block diagram of a control device implementing the described method (for a four-phase converter); Fig. 2 shows charts describing the principle of transfer of control channels in the case of control of a four-phase converter. The control device contains a master oscillator 1, which is a generator of relaxation oscillations, medium-sized with a clock counter 2 pulses, fired out as a binary counter and containing a number of triggers equal to the number of three ger reversible counter 3 controls, which also represents a binary counter. The clock counter with 2 outputs is connected to the decoders 4,5,6,7. also made in the form of diode arrays, which are assembled in such a way that the shift of control pulses with these decoders occurs within Of / 4 (, / t) - the filling effect, t i pulse duration), but with mixing in time. Single clock clock is connected to the decoder 8, made in the form of a diode Katritsa, which is used to shift the unshifted sequences of control pulses by T (T - the switching period of the thyristors) which appear at the outputs 9,10,11,12 decoder. The decoders are connected to matching element 13, which contains AND elements, through which control channels are transmitted. The matching element 13 has outputs 14,15,16,17, followed by time-shifted pulses and Rai-T offset relative to each other. The tires of the set 18 and the return of 15 positions of the control unit 20 are connected to a reversible counter having output tires 21,22,23,24, controlling the fill factor, respectively. but 0; 0.25; 0.5, - 0.75. The control device operates as follows. Initially, in the range of variation; the coefficient of filling | 6.25 of the regulation channel controls the first and third phase thyristors, and the channel n controls the thyristors of the phase J, W, and the channel controls the thyristors of phase iif and W -and channels are thyristors of the 1st phase. Moreover, the beginning of regulation of 1 alady phase is shifted in time by 0.25 T (Fig. 2). From the master oscillator 1, the clock pulses arrive at the clock counter 2 pulses, which lead to a change in the trigger trigger 2 trigger signals. From the clock counter soda signals are sent: to the decoders. The diode matrix of the decoder 8 is typed in such a way that when the state of the triggers of the clock counter 2 changes, outputs 9-12 of the pulses appear, shifted in time relative to each other by 4 T, which follow to the main thyristors of the converter phases. When a signal is received from the control device 20 via the position set bus 18 to the reversible counters 3, the latter triggers change their states, in accordance with which the signals appear on the output tires of the reversing counter 3 connected to the decoders 4-7. At the same time, a potential signal appears at the output of 21. The reversible counter 3, which follows the matching element 13. When the state of the trigger of the clock 2 and reversible 3 counters coincides, the pulses that are shifted in time and / A T and shifted relative to corresponding impulses going through output buses 9-12 per d T / o which pass through matching element 13: from decoder 4 to exit 14, from decoder 5 to exit 15, from decoder 6 to exit 16 and from the decoder 7 - on exit 17, Arrival of subsequent imp control pulses from the control unit 20 via the set position bus 18 on the re; versal counter 3 leads to a change in the state of the triggers of the reversible counter, in connection with which it coincides. The trigger and reverse counter trigger state occurs at another time, thereby increasing the delay in the arrival of pulses from the outputs of the decoders 4-7 relative to the corresponding pulses coming from outputs 9712. When the fill factor reaches 0.25, the output 21 of the reverse counter 3 disappears potential signal and appears at output 22. At the same time, P1) resets the reverse of counter 3 to the first position at which the shift between pulses coming from outputs 9-12 and pulses going with the corresponding decoders 4-7, minimal and equal to cf. Taking into account that at this stage of regulation (0.25ff $ 0.5) the potential signal is present at output 22, the control of the Xth control channel is transferred to the thyristors of the S-th phase; tt channel on thyristors I-th phase; Wj-ro channel to thyristors I. -th phase of the 75th channel to thyristors of the 1st phase, i.e. with

decoder 4: pulses pass through matching element 13 to output 17, from decoder 5 to output 14, from decoder B to output 15 and from decoder 7 to output 16.

As the pulses from. the control unit 20 on the tire 18 of the set of positions on the reversible counter 3, an increase in the fill factor to G | 0.5 (Fig. 2).

When the fill factor reaches the value of / 0.5 from the output 22 of the reversible counter 3, the signal disappears and appears at the output 23. Simultaneously, the reversible counter 3 is reset to the first position. In this case, the control of the I-th control channel is transferred to the thyristors of the 1st phase; th channel to the thyristors of the 5th phase of the iji channel to the thyristors of the 1st phase of the th channel to the thyristors of the i phase, Impulses shifted in time come from the decoder 4 through the matching element 13 to the output 16, from the decoder 5 - to exit 17, from decoder B - to exit 14 and from decoder 7 to exit 15.

At the moment when the fill factor reaches the value of / jj 0.75, the signal at the output 24 of the reversing counter appears and the control of the first control channel to the thyristors -and phase- occurs. 1 channel to thyristors AND to phase 1 to channel to thyristors and phase; v-th channel to the thyristors of the 1st phase, with the pulses from the decoder 4 passing through the matching element 13 to the output 15, from the decoder 5 to the output 16, from the decoder 6 to the output 17, and from the decoder 7 to the output 14.

If it is necessary to reduce the fill ratio from the controlling authority 20, the signals are sent to the reversible counter 3 via the return position bus 19. In this case, the transmission channels

utravlenn occurs in reverse order.

Thus, with the proposed control method, the decoder diode arrays are recruited only to provide control in the range from O to 0.251 in this case and in the general case from O to (n) - /) ((t is the number of phases of the multiphase converter), and not for providing regulation in the whole range of 04 1 which leads to a decrease in the required number of elements of the decoders, to a decrease in power consumption, volume, cost and to an increase in efficiency.

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Claims (2)

1.BirznieksL. B. Pulsed DC Converters. M., Energie, 1974, p. 18-20. 0 2. Control circuits of the thyristor-impulse converters with discrete shift of pulses. Proceedings of the Dnepropetrovsk Institute of Railway Engineers, 1972, 5 Issue 135, p.47-105 (prototype). ,