SU1599793A1 - Apparatus for measuring ratio of pulse sequence frequencies - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices for measuring the value of the ratio of the frequencies of the pulse sequences, reduced to its nominal value. The aim of the invention is to expand the range of measured frequencies and functionality. The device for measuring the frequency ratio of the pulse sequences contains input buses 1 and 2, a reversible counter 5, a differential frequency driver 6, a blocking element 7, an output information bus 8, and a code-controlled frequency divider 10. Introduction of input buses 3 and 4, output information bus 9, code-controlled frequency dividers 11 and 12, multiplexer 13, memory block 14, pulse generator 15, clock 16, demultiplexer 17, frequency divider 18 and control block 19 allows measure the ratio of frequencies to one of a number of nominal values in the "Tuning" and "Operation" modes. 10 il.

Description

01

co stock 1

g oe

Fi9.1

The invention relates to a pulse technique and can be used in automation and computing devices for measuring the frequency ratio of pulse sequences, reduced to its nominal value.

The purpose of the invention is to expand the range of measured frequencies and functionality.

Figure 1 shows the block diagram of the device; on - time diagrams; Figs 3-8 are diagrams of individual units of the device; FIGS. 9 and 10 are time diagrams explaining his work.

A device for measuring the frequency ratio of sequences of pulses contains input buses 1-4, a reversible counter 5, a differential frequency generator 6, a blocking element 7, output information buses 8 and 9, code-controlled dividers 10-12 frequencies, a multiplexer 135 memory block A, shaper 15 of a series of pulses, clock generator 16, demultiplexer 17, frequency divider 18 and control unit is 1ppl block 19, the first input of which is connected to the first output of frequency divider 18, the second input - to the input bus 3, the third input - with input bus 4 and control The first input of the multiplexer is 13, the first output is with the recording input of memory 14, the second output is with the initial installation of memory 14, the fourth input is combined with the synchronization input of the frequency divider 12, the first. pulse generator 15 of a series of pulses, with the first output of the demultiplexer 17 and the first synchronization input of the differential frequency former 6, and the third output connected to the input of the initial installation of the reversible counter 5, whose information outputs are bitwise connected to the information inputs of the frequency controlled frequency divider 10 , the output information bus 8, the information inputs of the memory block 14 and the information inputs of the first channel of the multiplexer 13oInformational inputs of the second channel of the multiplexer 13 are bitwise connected with information inputs of a code-controlled frequency divider 11, with information outputs of memory block 14 and an output information bus 9, and information outputs are connected bitwise with information inputs of a code-controlled frequency divider 12, the second

the input of which is connected to the input bus 2, and the output is connected to the subtractive input of the imaging unit 6 differential

frequency, while its summing input is connected to the output of the code-controlled frequency divider 10, and the first output is connected to the counting input of the reversible counter 5 and the first input of the blocking element 7 The output of the element 7 is connected to the clock

the input of the reversible counter 5, information inputs - with information outputs of the reversible counter 5, and the second input is connected to the second output of the differential frequency generator 6, the second synchronization input of which is combined with the synchronization inputs of the code-controlled frequency dividers 10 and 11, the second output of the demultiplexer 17 whose first entry

connected to the second output of the frequency divider 18, and the second input is connected to the input of the frequency divider 18 and the output of the clock generator 16, and the input bus 1 is connected to the second input

shaper 15 pulse series; Shaper 15 shaper is connected to the input of the code-controlled frequency divider 11, the output of which is connected to the input of the code-controlled divider 10

frequencies

Codo-controlled frequency divider 10 (11) (FIG. 3) contains a subtractive counter 20 and a trigger 21, whose information input is connected to its inverse output, a reset input connected to the input of the coding-controlled frequency divider, the direct output connected to the output of the code-controlled frequency divider and to the input of the record of the subtracting counter 20, the output of which (N + l) -ro bit, used as the reverse overflow output, is connected to the trigger input of the trigger 21 The clock input and the information inputs of the N low bits are respectively the second input ohm and data inputs kodoupravl emogo frequency divider, wherein the information input (N + l) ro discharge subtracting counter 20 is supplied to level O,

Coding-controlled frequency divider 12 (FIG. 4) contains a summing counter 22 and triggers 23 and 24. The inverse clock input of the trigger 24 is connected

ten

with the clock input of the trigger 23 and the input of the third code-controlled frequency divider 12, the information input is connected to the synchronization input of the code-controlled frequency divider 12, and the output is connected to the clock input of the summing counter 22, the output of which () -ro bit is used as the output pr The overflow is connected to the trigger setup input 23. The recording input connected to the trigger output 23, and the information inputs of the N minor bits are respectively the output and information of 5 inputs of the code-controlled divider 12 you, wherein the information input of the flip-flop 23 and the information input (N + l) -ro discharge totalizer 22 is fed level.

The pulse generator 15 of the pulse train (FIG. 5) contains the triggers 25 and 26, the counter 27 and the element 28, the output of which is the output of the pulse former of the pulse train 15, the inverse input is connected to the clock input and the output of the (M + 1) th counter of the counter 27 and the inverse reset input of the trigger 26, and the direct input is connected to the clock input of the trigger 25, to the counting enable input of the counter 27 and is the first input of the driver 15 of a series of pulses. The trigger output 26 is connected to the zero reset input of the counter 27, and the clock input is connected to the trigger output 25, the information input of which is the second input of the pulse generator 15 of a series of pulses, and the level l is fed to the information input of the trigger 26

The control unit 19 (FIG. 6) contains the triggers 29 and 30, the AND 31 element, the AND-NE element 32 and the four OR-NOT elements 33-36, with the clock input of the trigger 29 being the first input of the control unit 19 and connected to a clock input of trigger 30, a first input of an NAND 32 element and a first input of a third element OR A NO 35 A reset input 50 is the second input of a control unit 19 and connected to a reset input of a trigger 30 and the first input of a fourth element OR NOT 36, the information input is the third 55 input of the control unit 19, and the direct output is connected to the information the one input of the trigger 30 and the first inputs of the element And 31 and the first element OR20

25

thirty

Q

45

35

NO 33, the second inputs of which are interconnected and connected to the inverse output of the second trigger 30. The output of element AND 3 is connected to the first input of the second element OR-NOT 34, and the second input of the fourth element RSHI-HE 36, the output of which is the second in ( 1 is the control unit 19 output. The output of the first element 1-CHI-HE 33 is connected to the second inputs of the AND-NE element 32 and the second element 1-SH-34, and the third input of the AND-32 element is the fourth input of the control unit 19 and the output is the first output of the control unit 19 o The output of the second element OR NOT 34 with of the connections to the second input of the third OR-NO element 35 whose output is a third output controlling unit 19,

The blocking element 7 (FIG. 7) contains two elements AND-NO 37.38, element OR 39, three elements OR-NOT 40-42, and the inputs of the element AND-NOT 37

in pairs are connected to the inputs of the element OR 39 and are the information inputs of the blocking element 7a. The output of the AND-NOT element 37 is connected to the first input of the element OR-NOT 40, and the output

the OR element 39 is connected to the first input of the OR-NO 42 element, the second input of which is connected to the second (inverse) input of the SH-NE 40 element and is the first input of the blocking element 7, and the output is connected to the first input of the OR-NO element 41, the second input of which is connected to the output of the OR-NOT 40 element, and the output is connected to the first input of the NE-38 element, the second

Its entrance is the second input of blocking element 7.

Shaper 6 differential frequency; Fig. 8) contains four elements AND 43-46, element OR 47 and four trig.

Gera 48-51, the first input of the element And 43, is the first synchronization input, and the second — the summing input of the difference frequency generator 6 — is connected to the clock inputs of the flip-flops 48 and 49, the output is connected to the reset inputs of the flip-flops 50 and 51 and the first the input element AND 45, the output ... of which is connected to the first input of the element OR 47o The second input is connected to the output of the trigger 49, whose information input is connected to the output of the trigger 48 and is the first output of the differential frequency driver 6, and the reset input is connected to the input

the trigger reset house 48, the output element AND4 and the first input element AND 46, the output of which is connected to the second input of the RSHI element 47, the second input is connected to the output of the trigger 51, whose information input is connected to the output of the trigger 50, and the clock input is subtractive the input of differential frequency generator 6 is connected to the clock input of trigger 50 and the first input of element 44, the second input of which is the second synchronization input of differential frequency generator 6, and level 1 inputs to the information inputs of trigger 48 and 50 the output of the element OR 47 is the second output of the differential frequency generator 6

The memory unit 14 is constructed according to a known registrar with parallel loading, the first input of the memory 1 unit being the input of the recording from the information inputs, and the second input the input of the initial installation on the information outputs of the memory 14, a predetermined fixed numerical value. code P, o

In the example of a specific embodiment of the device, the reversible counter 5, the co-controlled frequency dividers 10-12, the memory block 14 and the two-channel multiplexer 13 have the same number of bits equal to five, and the numerical code P has the value

P,

, H-1

+ 1 100002 17.0

1 {- 1-lW4J w W2 I /,

In order to simplify the mathematical calculations, the description uses binary 11a numbering system, in which the number 00600 2 corresponds to the number 1, p, the number 00001 - 2.0 and t "d.

The device operates in two modes.

In the Setup mode, the nominal ratio of the frequencies of the pulse sequences fed to the input buses 1 and 2 is measured, and in the Work mode, the ratio of the frequencies of the sequences of pulses fed to the input buses 1 and 2, reduced to its nominal value measured in Setup mode.

In Setup mode, the device works as follows.

The clock generator 16 runs-clock pulses (FIG. 2a) with a frequency fp and a duty cycle equal to

ten

25

Two are fed to the input of the frequency divider 18 and to the second input of the demultiplexer 17, while the second output of the frequency divider 18 produces a signal with a frequency / 2 (Fig. 26), which goes to the first (control) signal. the input of the demultiplexer 17. The demultiplexer 17 comments on the pulses of the tactile generator 16 with the frequency f./2, while at its outputs two pulse sequences are formed with the frequency fjj / 2, with a duty cycle of four, and out of phase with one another for a half period These pulse sequences are used for synchronization and devices (Fig. 2c, d).

At the first output of the 18 divider frequency, a signal with a frequency d / 2 is produced (in FIG 2d, this signal is shown at) and is fed to the first input of the control unit 195 to the fourth input of which the clock pulses come from the first output of the demultiplexer I7 and to the third input (input name 4), a signal is selected. Selection of the operation mode (Fig. 2g), the high level of which corresponds to the device setup mode.

When the control unit 19 arrives at the second input from the input bus 3 of the signal. The initial installation in the form of a positive polarity pulse (FIG. 2e) triggers 29 and 30 are reset, and the signals from their outputs are fed to the inputs of the And element 31, the output of which is set to low. voltages applied to the second input element OR-NOT 36 At its output a pulse of negative polarity is formed with a duration equal to the duration of the signal Initial setting (Figure 2h). This pulse from the 15th output of the element OR NOT 36 is fed to the input of the initial installation of the memory block 14 and is set at a low voltage level to it. information outputs fixed value of code 50, equal to 10,000.

When a control unit 19 receives a positive voltage drop coming from the first output of the divider 18 of frequency 55 (the trigger 29 is set to one state and the signal from its output sets element 31 also to one state 31 sets

35

at the output of the OR-1№ 36 element, the voltage is low, while at the information outputs of the memory block 14 the numerical code P is stored equal to 10,000.

At the same time, high voltage levels from the outputs of the flip-flops 29 and 30 are fed to the inputs of the IPI-NE 33 element and set at its output a low voltage level that goes to the second input of the ShSh-NE element 34 to the first input of which a high the voltage level from the output of the element 31. The output of the 1SHI-HE 34 element sets the low voltage that goes to the second input of the RSHI-HE 35 element, while a negative polarity pulse arrives at the first input of the control unit 19 figo.d), it comes in first stroke element PLD NOR 35 and is coupled to its output inverted. A positive polarity pulse (FIG. 2i) from the output of the element OR NOT 35 is fed to the input of the initial installation of the reversible counter 5 and, at a high voltage level, sets its information outputs to a numerical code П,, equal to 10,000, fixed on its information inputs a positive positive voltage drop to the first input of the control unit 19 (FIG 2d), the trigger 20 is set to the single state, while its inverse output is set to a low voltage level, the second output to the control its block 19 is set to a high voltage level (fig2). and at the third outlet, a low voltage level (Fig. 2i). From this point in time, the device is ready for operation in mode. Customization.

The input bus 1 receives a sequence of pulses with a frequency f, from where it is fed to the information input of the trigger 25, which is set to one when there is a high voltage on its information input on the front of the synchronizing pulse (Fig. 2b) coming from the first the output of the demultiplexer 17 at its clock. input. A positive voltage drop, coming from the output of the trigger 25 to the clock input of the trigger 26, sets the last

in a single state. The high voltage level, coming from the output of the trigger 26 to the reset input of the counter 27, sets the information outputs of the latter to zero states, while the low level voltage coming from the output of the (M + 1) th digit of the counter 27 to the inverse input element 28 and the inverse reset input of trigger 26, sets the last to zero state and allows clock pulses to pass to the input of the code-controlled frequency divider 11 through the element 28. The low level voltage coming from the output of the trigger 26 to the reset input of the counter 27, and the low voltage coming from the output of the (M + 1) th discharge of the counter 27 to its clock input, allows the latter to count the synchronizing pulses the input of the permission of the account, carried out upon receipt of the leading edges of the specified clock pulses at its input of the resolution of the account. When the output (M + 1) of the high voltage level counter 27 appears at the output, it blocks further counting at the clock input of the counter 27 and prohibits the passage of synchronizing pulses from the first output of the demultiplexer 17 to the input of the co-controlled frequency divider 11 through the AND element 28, while from the moment of zeroing of the counter 27 until it is blocked at the output of the element And 28, a packet of (R 2 pulses, TeV, average frequency f. Of the pulse sequence at the output of the pulse generator 15 series of pulses

 . „-F., 2,. (2)

When a pulse sequence with frequency f arrives at the second input of the code-controlled frequency divider 11, the subtractive counter 20 reduces its contents to a high voltage level at the reverse of its overflow, while the positive differential sets the trigger 21 to one (), previously in the zero state due to the arrival at its input of a reset of synchronizing pulses from the second output of the demultiplexer 17. The high voltage level that occurred on the right output of the trigger 21 em in counter 20

numerical code П ,, 10000, arriving at its information-1-1 inputs. from the information outputs of the block 14 are pastes, and the strongest synchronizing pulse, received at the reset input of trigger 21, sets it to the zero state, allowing the counter to be counted 20 o

: Thus, the code-controlled de | 1 frequency 11 frequency divides the frequency f, SB N, times, at THIS; at its output, pulses of positive polarity (figo 2l) are generated, following with a frequency

  , (3)

f g

P,

The leading edge of which coincides with the leading edge of the synchronizing impulses with the first output of the de-flexor 17, and the falling edge with the leading edge of the synchronizing pulses from the second output of the demultiplexer 17o

The pulses from the output of the code-controlled frequency divider 1 are fed to the input of the code-controlled frequency divider 10, which operates similarly to the dividing factor of the code-controlled frequency divider 10 equal to the numerical code P on the information outputs of the reversible counter 5, and the frequency at its output

 llJ (4) 35

40

45

 3 r

moreover, the front edges of its output mycoles (FIG 2L) also coincide with the leading edge of synchronizing impulses from the first output of demultiplexer 17, and the falling edge - with the leading edge of synchronizing pulses from the second output of demultiplexer 17o

The pulses from the output of the code-controlled frequency divider 10 are fed to the summing input of the difference frequency frequency generator 6, and the frequency with which they are taken into account is (2) - (4) equal to.

.fc - |: f- (5) 50

At the same time, the input bus 2 receives a pulse sequence with a frequency, ,, from which it is fed to the information input of the trigger 24, which is set to the single state at the same time

receipt of a high level eg H11 at its information input

with

0

0

five

0

five

0

five

0

(figo) and the falling edge of the syngonic impulse coming from the first output of the demultiplexer 17 to its clock input Positive, voltage drop, flow; 1y from the output of trigger 24 to the clock input of the summing counter 22, increases the state of the last by one, and The counting process of the input pulses with a frequency f continues until the high-level summing counter 22 appears at the output of the overflow, which is fed to the S input of the trigger setup 23. The trigger 23 is set to one state si (Fig, 2o), a high level of voltage from its output is fed to the input of the record of the summing counter 22 and records in it the numerical code P from the informational inputs of the latter, which are connected through the multiplexer 13 to the information outputs of the reversible counter 5, while the multiplexer 13 by supplying to its control input a high level of voltage from the input band 4 is switched on to transmit data from its information inputs of the first channel to its output. The output of the direct overflow of the summing counter 22 is set to the bottom. cue voltage level, while the trigger 23 is set to the zero state (Fig. 2o) when its front-edge clock input arrives at its nearest synchronization pulse from the first output of the demultiplexer 17,

Thus, the code-controlled frequency divider 12 has a division factor

, (b)

where N is the number of bits of the information inputs of the code-controlled frequency divider 12, the frequency of the pulse sequence from the output of the code-controlled frequency divider 12 to the subtracting input of the differential frequency generator 6

f.

(7)

moreover, to represent the coefficient D in the decimal system of calculation, it is necessary to perform a subtraction (2-D) in the binary system and present its result in the decimal system of calculus

A positive polarity pulse arriving at the summing input of the differential frequency generator 6 sets the trigger A8 to a single state and allows one synchronizing pulse from the first output of the multiplexer 17 to pass through the And 43 element, the output of which (FIG. 2m) resets the triggers 50 and 51, while the high voltage level from the output of the trigger 48 goes to the first input of the reversing counter 5 and sets the summing mode of its operation. The next pulse received on the summing One of the differential frequency generator 6, in the absence of a pulse at its subtractive input, sets the trigger 49 also into one state, which permits the passage of a single clock pulse matching the input pulse from the output of the AND 43 element through the element 45 to the input of the element OR 47 from where it is fed through the blocking element 7 to the clock input of the reversible counter 5, increasing its state by one

When a difference pulse frequency from the output of the code-controlled divider 12 arrives at the subtracting input of the shaper 6, it sets the trigger 50 to the one state and allows one synchronizing pulse from the second output of the demultiplexer 17 to pass through the element 44, the signal from the output of the cross ( Fig. 2p) resets the triggers 48 and 49, while the low voltage level at the output of the trigger 48 sets the subtractive mode of operation of the reversing counter 5, and the next impulse arriving at the subtracting input is formed Atel 6 difference often do, set the trigger. 51 into a single state that permits the passage of a synchronizing pulse coinciding with the input pulse from the output of element AND 44 through element AND 46 to the input of element OR 47, from where it is fed through blocking element 7 to the clock input of the reversible counter 5, reducing it state per unit

With the alternate arrival of pulses on the summing and subtracting inputs of differential frequency forcing 6, the output of the OR 47 pulse does not appear, because the triggers 49 and 51 are in the zero state of the institute

Thus, at the second output of the difference frequency generator 6, a pulse sequence is generated with a frequency

lf, .- fz, l

(eight)

and the possibility of failures when the frequency of the signals at the subtractive and summing inputs coincide is eliminated by eliminating the coincidence of the phases of these signals by synchronizing the differential frequency generator 6.

In the Tuning mode, the input busses 12 receive pulse sequences with frequencies f .j and f, the ratio of which average values remain unchanged until the end of the Tuning mode and is the main value of the measured ratio of average values of f and f. At the same time, the sequence of pulses with frequency fj comes from the second output of the spinner 6 differential frequency drive through the blocking element 7 to the clock input of the reversing counter 5 and changes its state until the device enters the steady state at which m second output of the difference frequency of 6 pulses is stopped formation 3 then taking (8) dn spra- vedpivo steady state equation:

f, 3-f, 0.

(9)

whence it follows that the ratio of the average values of the frequencies fj and f, taking into account (5) - (7), is equal to

fj p1

f; (f

()

(ten)

Moreover, equality (10) is valid with an accuracy due to the discrete character of the measurement.

The value of the numerical code P coming from the information outputs of the reversible counter 5 to the output information bus 8 in the Setup mode, in an unspecified form, characterizes the nominal value of the measured ratio of average values of frequencies f, and f. pulse sequences, defined by the expression (10),

 Mode Configuring the operation of a device that is stationary

mode, ends when a HHt-i arrives on a low-level input bus 4 Hj-f signaling signal Selection of the operating mode corresponding to the Device operation mode (FIG2). From the input bus 4, the specified signal is fed to the information input of the trigger 29 and to the control input of the multiplexer 13, the latter is set to transmit data from the information inputs of the second channel to its output,

The trigger 29 is set to the zero state by a positive voltage drop from the first output of the frequency divider 18 to its clock input, while the low voltage levels coming from the outputs of the flip-flops 29 and 30 on. the inputs of the SHSHE-33 element are set at (ITS output high level of the voltage, Which goes to the second input of the LE-NE 32 element,;; A high voltage level, output from the divider 18 frequency output to the second input element AND-HE 32, allows the passage of synchronizing pulses from the first, the output of the multiplexer 17 through the element AND-HE 32, where their polarity is changed to the opposite, to the recording input of the memory block 14, while negatively; The signal drops (Fig. 2k) from the output of the stroke of the element N-HE 32 are produced.

Parallel loading into the memory block 14 of the numeric code. P, which is supplied to its information inputs from the information outputs of the reversible counter 5 o In this case, the information outputs of the memory block 14 are set to the numerical code P, equal to to the numeric code P, which is set to its information inputs. To the end of the Tuning mode, when measuring the nominal values of the ratios of frequencies () (, equal in accordance with the expression (10)

(ll) f - 1,

P,

Ji

()

(P)

The passage of sish-phoning pulses to the write input of the block of 14 memory .. through the element IS-NOT 32 finishes-. with when entering a low level - pp pa from the first output of the divider, 18; the frequency at the first input of the element AND- NOT 32, also arriving at the first. left, the input element is OR NOT-35, and the output at the output of the last ...

50

5 o

five

0 - five

0

five

high level

 yarn, because its second input receives a low voltage level from the output of the OR-NOT 34 element, to the input of which a high voltage level from the output of the OR-NOT 33 element is supplied. A high voltage level from the output of the ICH-NO 35 element (FIG. , 2i) is fed to the input of the initial installation of the reversible counter 5 and sets on the information outputs a numerical code P (5 fixed on its information. Inputs

Upon receipt of a positive voltage drop from the first output of the frequency divider 18 to the clock input of the trigger 30, the latter is set to the zero state, while you-. The high voltage level, coming from its inverse output to the second input of the ШШ-НЕ.3 element, sets the latter to the zero state. A low voltage level goes to the first input of 1-1PII-NOT 34, the signal from the output of which goes to the second input element UTI-NOT 35 and sets at the last output a low voltage level, which enters the input of the initial installation of the reversible counter 5 and allows it to work in the counting mode. From this moment on, the device is ready to function in the -Rab mode. ,

In Operation mode, the device works as follows.

The input bus 1 and 2 continue to receive a sequence of pulses with frequencies f, and f ,, while

The frequency of the pulse sequence on the output of the former 15 series of immersions is determined by expression (2).

A pulse sequence with a frequency f. |, From the output of a series of pulses, is fed to the input of a co-controlled frequency divider 11, in which the frequency f is divided. (j for the value of the numerical code P arriving at its information inputs from the information outputs of the memory block 14, while at the output of the code-controlled donor 11 frequency a pulse sequence is generated with the frequency

/ 4-i, t,

which is fed to the second input of the kodo of the controlled frequency divider 10, axis 1 is the central frequency division by the value of the numerical code P, which enters its information inputs from the information outputs of the reversible counter 5

At the output of the code & controlled frequency divider 10, a sequence of pulses is formed with a frequency

h (13)

or taking into account (2) and (12) Ф-f V

(14)

f -: PG P

 which arrives at the summing input of the delimiter 6 of the difference frequency,

At the same time, the frequency f. pulse sequence arriving n

; in the second entrance of the code-controlled divide-

 l 12 frequencies, divided by coefficient

ID equal to (6):

2

(15)

Since, its informational inputs receive the numerical code of the informational outputs of memory block 14 through multiplexer 13, while the frequency at the output of the code-controlled frequency divider 12

- | i,.

-2f

D

(sixteen)

35

A pulse sequence with a frequency fg, from the output of the code-controlled splitter 12, frequency is applied to the subtracting input of the delimiter 6 for the difference frequency, the second output of which produces a pulse sequence with the difference frequency

F –f t 21

(17)

which enters through the blocking element 7 to the clock input of the reversing 5 of the counter 5 and changes its state until the device under the condition of a constant ratio of the average values of the frequencies f. and fj will not enter the established mode in which the frequency fj is zero.

Then, taking into account (17) for the established regime, equality holds;

f -f -n f 1% 41 (18)

From here, taking into account (14) and (16), the value of the numerical code P determined at the information outputs of the reversible counter 5 is found:

P fi. (:. (,9)

Ij P

Multiplying the numerator and the denominator of equality (19) by P, and substituting the expression (II) into it, get fi / fg

 -TTG717

From the expression

(20)

n, (20) it follows that

in Operation mode, the value of the numeric code P on the information outputs of the reversible counter 5 and on the output information bus 8 is equal to the constant value of the code P multiplied by the value of frequency f and f reduced to its nominal value measured in the Setup mode. While maintaining a constant frequency ratio, and f

five

Q

five

50

f4 D ";

 f.

)and

(21)

fl J-2

during the transition from the Setup to the mode: Operation in the Operation mode, the jcpasy starts to function in the established mode, 1 since the indicated transition to the reversible counter 5 records the code P ,, corresponding to equality (21) and being the unit value of--. measured to the nominal value of the measured frequency ratio f, and f,

In the Operation mode, the output information bus 9 comes from the information outputs of the memory block 14, a numerical code P, which in an implicit form, in accordance with expression (11) determines the value of the nominal value of the measured frequency ratio f, and f.

in Operation mode, the relative measurement error is the reduced to the nominal value of the frequency ratio f, and f

one

r p.

(22)

and the measurement range of said ratio is

(f./fz).

m

(23)

n, - (, - n,

in Setup mode, the relative error is about. measuring the nominal frequency ratio, and f for; “,

Where

 Have

(24)

19 taking into account the expression (S)

8 -) ° to x- (i-x)

1599793

(25)

p kr n g and and and n n l

From the plot of the dependence of от on X day (Fig. 9a) and for (Fig. 9b) it is indicated that the function 0 (, (X) is symmetric, ijia is relatively and almost constant in the interval 0,, 85, which allows to form a wide

The measurement range of the nominal values of the frequency cut-off f, and fj, has 1 relative width K with a given

 maximum relative error

(. The value of S M, etc., and this for the boundaries of the symmetric interval:

(1-Y) 2

(26)

G de

one

 ,five.

 the content of the ero H discrete nominal j values of the measured ratio of the part-That f and fl, and

H (1-2Y), (27)

value of K taking into account the expression (10)

.. (fi / fa) HMQ.c 1-Y 24l-y) n (2a

 (f7 / f xWH7 Y i + Y-2-

where () is the maximum nominal value of the measured ratio; (f,) „„ J, - minimum nominal

national meaning

 measured ratio

and the graph of K versus fr, constructed with allowance for expressions (25) and (28), is shown in FIG. DL and FIG.

From the expression (10) it follows that in the Setting mode, the value of P, defined by expression (2), sets the scale of the measurement of the frequency ratio f, TL f., And allows, by selecting the value M, to place the range of variation

measured frequency ratio within the measuring range

and f.

In order to protect the reversible counter 5 from overflow in the event that the measured ratio of frequencies f and f is outside the measuring range of the device, blocking element 7 serves (Fig. 7).

From the measurement range of the device, nominal values of measurements are excluded.

five

0

five

zo

before

45

50

55

the corresponding ratios correspond to the extreme values of the numerical code P on the information outputs of the reversible counter 5, when reached, the value of Ots increases dramatically, therefore the information inputs of the element. AND-NOT 37 and the element OR 39 are connected to all the information outputs, with the exception of the low-order, reversible counter 5 o When the subtraction mode of the reversible counter 5 appears at all its information outputs connected to the information inputs of the blocking element 7, a low voltage level at the output of the IL element And 39 a low voltage level is also set, which goes to the first input of the OR-HEN element 42 and sets a high voltage level at its output, because the second input of the OR-NO 42 element receives a low voltage level from the first output of the differential frequency generator 6 defining the subtraction mode of the reversible counter 5

The voltage from the output of the SHS-NO 42 element is fed to the input of the OR-NOT 41 element and sets at the output of the last low voltage level, which prohibits the passage of pulses from the second output of the differential frequency generator 6 through the I-NE 38 element to the second input of the reversible counter 5

When the reversive counter 5 appears in the summing mode, all its information outputs connected to the information inputs of the blocking element 7, a high voltage level, at the output of the AND-HE element 37 establish a low voltage level, which is fed to the first input of the OR-NOT element 40, the inverted input of which, from the first output of the differential frequency generator 6, receives a high voltage level corresponding to the summing mode of the reversible counter 5.

The output of the OR-NOT 40 element sets a high voltage level that is applied to the input of the OR-NOT 41 element and sets: at its output a low voltage level prohibits the passage of pulses from the first output of the differential frequency generator 6 through the IS-38 element to the second input of the reversing counter 5,

When the device operates in the Operation mode, the ratio of the frequencies f and fl is measured to its nominal value, measured in the Tuning mode. If necessary, measure the frequency ratio f. and fl, given to

h

2

to

15

Otherwise, its nominal value is fed to the input bus 4. High signal voltage level The choice of operating mode (Fig. 2g) corresponding to the Tuning mode, the device switches to Tuning mode, in which the new nominal frequency ratio f is measured, and f .

The device provides a measurement of the ratio of the frequencies f, and f ,, reduced to any of the set H of its nominal values that are within the measurement of the device and, therefore, the extension of the range of measured frequencies and functionality, which allows it to be used in such automation and computing systems where it is required when the measured value of the frequency ratio f and f „deviates from its nominal value

20

thirty

35

f from

generate a discrepancy signal in the form of a numerical code P, deviating from the predetermined numerical code i, which is the unit value of the measured frequency ratio f, and f 2. In addition, the internal synchronization of the operation of the device with two sequences of synchronizing pulses, shifted in phase, eliminates, - the possibility of failures, Toe, the reliability of the proposed device increases.

Claims (1)

Invention Formula A device for measuring the frequency ratio of a pulse sequence containing the first and second input buses, a differential frequency shaper, a blocking element, a first code-controlled frequency divider, a reversible counter, whose information outputs are bitwise connected to the information inputs of the first code-controlled frequency divider and are the first output data bus, with the input being directed to 15 25 20 thirty 35  . 0 t, - 45 50 55 The counting of the reversible counter sub-switch to the first output of the differential frequency generator and the first input of the blocking element, and the output of the first code-controlled frequency divider is connected to the summing input of the differential frequency generator, characterized in that, in order to expand the range of measured frequencies and functional capabilities, the second and third code-controlled frequency dividers, a memory block, a multiplexer, a demultiplexer, a pulse trainer, a frequency divider, a clock generator are additionally introduced into it. torus, third and fourth input buses, second output information bus and control unit, the first input of which is connected to the first output of the frequency divider, the second input - to the third input bus, the third input - to the fourth input bus and control input of the multiplexer, the fourth input - with the first output of the demultiplexer., the synchronization input of the third code-controlled frequency divider, the first input of the pulse shaper generator and the first synchronization input of the shaper - differential frequency, the first output is connected to the recording input the memory location, the second output to the input of the initial installation of the memory block, and the third output to the input of the initial installation of the reversible counter, while the information outputs of the reversible counter are bitwise connected to the information inputs and the memory block and the first channel of the multiplexer, the information inputs of the second channel of which, bitwise, are connected to the informational outputs of the memory unit, the second code-controlled frequency divider and the second output-od; -5th device information bus, and the information outputs are connected with information - 1 inputs of the third code-controlled frequency divider, the input of the third code-controlled frequency divider is connected to the second input bus, and the output to the subtractive input of the differential frequency frequency converter, the second output of which is connected to the second input of the blocking element, the information inputs of the blocking element & 1 with information outputs of the reversible counter, the clock input of which is connected to the output of the blocking element, the second synchronization input, differential frequency generator about) - one with the synchronization inputs of the first and second code-controlled frequency dividers and the second output of the demodulator, the first input of which is connected to the second output of the frequency divider, and the second input is combined with the output of the clock generator and input sPi /. 2 BJCOd2 V insormation inputs FIG. the frequency divider, the second input of the pulse trainer is connected to the first input bus and the output to the input of the second code-controlled frequency divider, whose output is connected to the input of the first code-controlled frequency divider. input1 c I d 1 / L ± one Output  Rig. 6 5 1599793 FIG. 7 FIG. eight 0.1 0.1 0, S 0.4 0.5 0.1 0.8 0.9 X Fi.9 Bxodz ) (Od1 / Y , 2-10 2-10 10 5 W 2-W ten S 10 2 W 10 50 20 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 // 0U2, fO Compiled by H. Fedorov Editor L. Pčoli ska. Tehred M. Khodanich Proofreader O. Tsiple. Order 3140 Circulation 559 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology CQCP 113035, Moscow, Zh-35, 4/5, Raushsk nab. Subscription