SU1161977A1 - Pulse-position converter - Google Patents

Abstract

1. PHASE-IMPULSE CONVERTER containing the driver of the reference signal pulses, the input connected to the reference signal bus, and the output to the first input of the first trigger, the first and second drivers of the measuring signal, inputs connected to the bus of the measuring signal, and outputs with the first inputs respectively the second and third triggers, the outputs of the first, second and third triggers are connected respectively to the first inputs of the first, second and third synchronizers, the outputs of which are connected to responsibly with the first inputs of the first, second and third elements I, the outputs connected respectively via the first, second or third divider with the second inputs of the first, second and third triggers, the second input of the first synchronizer is connected to the second inputs of the second and third elements I and to the first output of the imager clock pulses, the input of which is connected to the output of the clock pulse generator, and the second output is connected to the second inputs of the second and third syncro. and the second input of the first element I, the combination adder, the inputs of which are connected to the outputs of the second and third elements I, the first output connected through the fourth divider to the first input of the first element S1I, the second input of which is connected to the second output of the combination-. adder, the output of the first divider is connected via the first one vibrator to the control input of the register, the code inputs of which are connected to the outputs of the first counter, which is characterized by the fact that, in order to expand its functionality, the first switch (L switch, fourth, fifth and the sixth triggers, the second element OR, the second counter, the second and third one-shot, five elements AND, the fourth divider, the first input of the first switch connected to the output of the first element OR and the first Od input of the fourth element a And, the second input - with the output of the first element And and the first input of the fifth element And; the third and fourth inputs are connected to the outputs of the fourth trigger, the fifth input is connected to the output of the second element OR and the second inputs of the fourth and fifth elements And, and the outputs are connected respectively to the first and second inputs of the first counter, the code outputs of which are connected to the inputs of the second OR element, and the third input is connected to the first input of the fifth trigger, through the second one-vibrator is connected to the first input of the sixth trigger

Description

He and the output of the first one-shot and through the third one-shot is connected to the first input of the second counter and the first input of the fourth trigger, the second and third inputs of which are connected respectively to the outputs of the fourth and fifth elements And, the fourth input is connected to the output of the sixth trigger, the second input of which is connected with the first input of the sixth element And the first output of the fifth trigger, the second input of which is connected to the first output of the fourth trigger, and the second output is connected to the first input of the seventh element And, the second input to expensively connected to the second input of the sixth element And, to the second input of the second counter and through the fourth divider to the output of the eighth element And, the first input of which is connected to the second input of the second synchronizer, and the second input is connected to the output of the second counter, the code inputs of which are connected to code the register outputs and the control outputs of the divider, and the code outputs are connected to the code inputs of the first counter.

2. The device according to claim 1, in order to expand the functionality, a second switch, a third counter, a third OR element, a seventh trigger, and four AND elements are introduced into it, the first and second inputs of the second switch are connected respectively, with the outputs of the sixth and seventh elements And with the first inputs of the ninth and tenth elements And, the second inputs of which are connected to the third input of the second switch and through the third elements OR to the code outputs of the third counter, and the outputs are connected to the inputs of the seventh About the trigger, the first and second outputs of which are connected respectively to the fourth and fifth inputs of the second switch and the first inputs of the eleventh and twelfth elements I, the second inputs of which are connected to the output of the third counter, the inputs of which are connected to the outputs of the second switch.

The invention relates to automation and computing, can be used in phase information-measuring systems.

A device containing amplifiers, a clock pulse generator connected to the inputs of a blocking voltage generator and a divider counter connected through serially connected sinusoidal voltage drivers, a phase sensor and a phase pulse former to a first input of the valve, to the second input of which the driver of a blocking generator is connected is known. voltage, as well as the next meter, synchronizer, decoder and circuit. And, the counting input of the next meter is connected to the output of the clock generator pulses, bits of the next counter are connected to the outputs of the decoders, the input

setting the follow-up counter to zero is connected to the first synchronizer input, the first input of which is connected to the valve output, the second input to the output of the clock generator, the second output to the first inputs of the AND circuit, the second input of each of which is connected to the output of the corresponding decoder, and output - with the input of the corresponding amplifier 03.

The disadvantage of this device is its narrow functionality, due to the fact that it can work only with one type of input signal.

A device containing a driver pulse reference signal, the input connected to the reference signal bus, and the output to the first input of the first trigger, the first and second pulse shapers of the measuring signal, the inputs connected to the measuring signal bus, and outputs to the first inputs of the second and third triggers, the outputs of the first, second and third triggers are connected respectively to the first inputs of the first, second, and third synchronizers, the outputs of which are: connected respectively to ne the primary inputs of the first, second and third elements And, the outputs connected respectively through the first, second or third dividers with the second inputs of the first, second and third triggers, the second input of the first synchronizer is connected to the second inputs of the second and third elements And, and the first code of the clock pulse generator whose input is connected to the output of the clock pulse generator, and the second output is connected to the second inputs of the second and third synchronizers and to the second input of the first element I, the combinational adder, one of which is connected to the outputs of the second and third elements AND, the first output is connected via the fourth divisor to the first input of the first OR element, the second input of which is connected to the second output of the combinational adder, the output of the first divider is connected to the control input the register, the code inputs of which are connected to the outputs of the first counter, the input of the phase shifter is connected to the output of the power source, and the output is connected to the bus of the measuring signal, the input of the counter is connected to the output of the element OR C2l. However, this device is characterized by narrow functionality, since it does not allow to transform phase shifts in a series of pulses of a unitary code and can work only with one type of input signal. The purpose of the invention is to expand the functionality. The goal is achieved by the fact that a phase-impulse converter containing a driver of reference pulse, the input connected to the reference signal bus and the output to the first input of the first trigger, the first and second pulse generator of the measuring signal, the inputs connected to the tire of the measuring signal, and outputs with the first inputs of the second and third flip-flops respectively, the outputs of the first, second and third flip-flops are connected respectively with the first inputs of the first, second and third synchronizers in, the outputs of which are connected respectively with the first inputs of the first, second and third elements And, the outputs connected respectively through the first, second or third divider with the second inputs of the first, second and third flip-flops, the second input of the first synchronizer is connected to the second inputs of the second and third elements And and with the first output of the clock pulse generator, the input of which is connected to the output of the clock pulse generator, and the second output is connected to the second inputs of the second and third synchronizers and to the second input The first element And, combinator, whose inputs are connected to the outputs of the second and third elements, the first output is connected through a quarter divider to the first input of the first element OR, the second input of which is connected to the second output of the combinational adder, the output of the first divider is connected to the first the input of the register, the code inputs of which are connected to the outputs of the first counter, introduced the first switch, the fourth, fifth and sixth triggers, the second element OR, the second counter, and the second and third one-shot, five AND elements, the fourth divider, the first input of the first switch connected to the output of the first OR element and the first input of the fourth AND element, the second input to the output of the first And element and the first Bbw input of the fifth And element, the third and fourth inputs are connected to the outputs the fourth trigger, the fifth input is connected to the output of the second OR element and to the second inputs of the fourth and fifth And elements, and the outputs are connected to the first and second inputs of the first counter, respectively, whose code outputs are connected to the inputs element OR, and the third input is connected to the first input of the fifth trigger, through the second one-shot it is connected

with the first input of the sixth trigger and the output of the first single vibrator, and through the third single vibrator connected to the first input of the second counter and the first input of the fourth trigger, the second and third inputs of which are connected respectively to the codes of the fourth and fifth elements And, and the fourth input connected to the output of the sixth trigger whose second input is connected to the first input of the sixth element And and the first output of the fifth trigger, the second input of which is connected to the first output of the fourth trigger, and the second output is connected to the first input of the seventh And element, the second input of which is connected to the second input of the sixth element I, with the second input of the second counter and through the fourth divider - from the output of the eighth element And, the first input of which is connected to the second input of the second synchronizer, and the second input is connected to the output of the second counter the inputs of which are connected to the code codes of the register and the control inputs of the divider, and the code outputs are connected to the code inputs of the first counter.

In addition, a second switch, a third counter, a third element OR, a seventh trigger, and four AND elements are entered into the device, with the first and second inputs of the second switch connected to the sixth and seventh And elements, respectively, and to the first inputs of the ninth and tenth And elements the second inputs of which are connected to the third input of the second switch and via the third element OR to the code outputs of the third counter, and the outputs are connected to the inputs of the seventh trigger, the first and second outputs of which are connected respectively to the fourth Dirt and FIFTH inputs of the second switch and the first inputs of the eleventh and twelfth elements And, the second inputs of which are connected to the output of the third counter, the inputs of which are connected to the outputs of the second switch.

FIG. 1 shows a block diagram of a phase pulse converter; 2 shows timing diagrams for his work.

The device contains a driver 1 pulses of the reference signal, the input

connected to the reference signal bus, and the output to the first input of trigger 2., drivers 3 and 4 pulses of the measuring signal, inputs connected to the measuring signal bus, and outputs to the first inputs of triggers 5 and 6, respectively, outputs of trigger 2.5 and 6 connected respectively with the first

synchronizer inputs 7-9, the outputs of which are connected respectively with the first inputs of the elements And 10-12, outputs connected respectively through a divider 13-15 with the second

the inputs of the trigger 2.5 and 6, the second input of the synchronizer 7 is connected to the second inputs of the elements 11 and 12 and the first code of the driver 16 clock pulses, the input of which

connected to the output of the generator 17 clock pulses, and the second output is connected to the second inputs of synchronizers 8 and 9 and the second input of the element 10, the combination adder 18, whose inputs are connected to the outputs of the elements 11 and 12, the first output is connected through a divider 19 to the first input the element OR 20, the second input of which is connected to the second output of the adder 18, the output of the divider 13 through the one-shot 21 is connected to the control input of the register

22, the code inputs of which are connected to the outputs of the counter 23, the first input

switch 24 is connected to the output

the element OR 20, and the first input element AND 25, the second input - with the output element AND 10 and the first input element AND 26, the third and fourth inputs are connected to the outputs of the trigger 27, the fifth input is connected to the output element OR 28 and the second inputs of the elements 25 and the outputs are connected respectively to the first and second

the counter inputs .23, the code outputs of which are connected to the input of the element OR 28, and the third input is connected to the first input of the trigger 29, through the one-shot 30 to the first input

trigger 31 and the output of the one-shot 21, and through the one-shot 32 is connected to the first input of the counter 33 and the first input of the trigger 27, the second and third inputs of which are connected

with the outputs of the elements And 25 n 26, and the fourth input is connected to the output of the trigger 31, the second input of which is connected to the first input of the element And 34 and the first output of the trigger 29, the second input of which is connected to the first output of the trigger 27, and the second output is connected to the first input And 35, the second input of which is connected to the second input of the And 34 element, to the second input of the counter 33 and through the divider 36 is connected to the And 37 element, the first input of which is connected to the second input of the synchronizer 8, and the second input is connected to the counter output 33 whose code inputs are connected The code outputs of the register 22 and the control inputs of the divider 36, and the code outputs are connected to the code inputs of the counter 23, the first and second inputs of the switch 38 are connected respectively to the output of the And 34 and 35 elements and the first inputs of the And 39 and 40 elements, the second inputs which are connected to the third input of the switch 38 and through the element OR 41 - with the code outputs of the counter 42, and the output is connected to the inputs of the trigger 43, the first and second outputs of which are connected respectively to the fourth and fifth eight inputs of the switch 38 and the first inputs of the elements 44 and 45 wto These inputs are connected to the output of counter 42, the inputs of which are connected to the inputs of the switch 38 The converter operates in the following way. The driver 16 clock pulses forms two sequences of alternating pulses of pulses (TI1 and TI2). The duration of which is equal to the pulse duration of the generator of 17 pulses, and the frequency at its outputs is equal to f, ..., f f (r / 2). where, and, is the frequency of the first second sequence of the TI1, TI2 pulses; ff. - frequency of the generator 17 pulses. The pulses of the TI1 sequence are fed to the inputs of synchronizers 8 and 9 and the input of element I 10, and the impulses of the sequence TI2 are fed to the input of elements 11 and 12 and to the input of synchronizer 7. Shapers 1 and 3 form short pulses, respectively (Fig. 2a, B) when the input signal is changed by 78 (Fig. 2B, d) from a negative value to a positive one, and driver 4, on the contrary, when the input signal changes from a positive value to a negative one (Fig. 2e). Triggers 2, 5 and 6, the output signal from which is fed to the corresponding input of the synchronizers 7-9, ensure the passage of whole pulses through the elements 10-12 when applying to one of the inputs of the triggers 2.5 and 6 pulses with corresponding shapers 1,3 and 4 to their other inputs - pulses from the outputs of dividers 13–15, respectively. At the outputs of elements 10-12, pulses are received (Fig. 201, O when the number of pulses in the packs is equal to the division ratio of dividers 13-15. The frequency of the pulse generator 17 and the division ratio of dividers 13-15 at a given frequency of the reference signal are selected, based on the required phase resolution from the ratio iN oc J, the division ratio of the dividers is 13-15; -frequency of the reference signal. The signal (Fig. 2e) from the output of the And 10 element is fed to the corresponding input of the switch 24 and the input of the And 26 element. Signals from the elements And 11 and-12 served on the input inputs of the combinational adder 18. Signals from its outputs are fed to the first input of the element OR 20 through the frequency divider 19, and to the second directly. The resulting signal (Fig. 210 from the output of the OR element 20 is fed to another input of the switch and the first input of the AND 25 and is a sequence of steps; A check of counting pulses, following one after the other, at a pulse frequency in packs equal to 2/2. The switch provides switching of input pulses to the inputs + or - of the reversing counter 23, depending on the presence in it of the number and the state of the trigger 27, which determines the sign of this number in accordance with the logic given in Table 1. From Table 1 it follows that the number accumulated in counter 23 is always in the direct code, and the sign of this number is determined by trigger 27 at the moment the counter goes through zero with the arrival of the first pulse at the input of switch 24. Code from the output of counter 23 is fed to input element OR 28. Element ШШ 28 provides the permitting potential on the second inputs of the elements 25 and 26 only when the number in the counter corresponds to zero and the trigger 27 is set to one or zero + state with the arrival on the first inputs of the elements 25 and 26 pulses from the element And 10 or OR 20. The code from counter 23 is fed to the first input of register 22, to the second input of which recording pulses are delivered (Fig. 2x) from the output of frequency divider 13 through the one-shot 21. In the absence of a change in phase of the measuring signal relative to the reference signal, at any relative position between them the number of pulses coming through the inputs of the switch 24 to the summing and subtracting inputs of the counter 23 is the same. This condition is also satisfied when the frequency of the input signals (UPP and Uy) changes from their nominal values. The counting result in the counter 23, which is recorded in the register 22 for each period of the write pulse (Fig. 2k), does not change. If the number previously recorded in counter 23 corresponds to zero, the number recorded in register 22 also corresponds to zero (information in register 22 is recorded when a pulse is applied (Fig. 2 | s) from the one-shot 21, while the previously recorded information is the register is automatically cleared). When changing the phase of the measuring Signal relative to the reference, corresponding to the phase lag, for example IC |, (fig.2g), the change in the signal corresponds to the absence of pulses, and through the inputs of the switch 24 to the summing input of the counter 23 receives a smaller number of pulses than its subtracting. The result of the readout recorded in register 22 corresponds to a phase change aqi, with a minus sign determining the state of the trigger 27 1 710 When the phase of the measuring signal changes relative to the reference, corresponding to the phase advance, for example utf (FIG. 2d), the signal corresponds to this phase change double the number of pulses, and through the inputs of the switch 24 to the summing input of the counter 23 receives more pulses than to its subtracting. The counting result recorded in register 22 corresponds to a change in the phase uqjj with a plus sign determined by the state of trigger 27. The output code from the register 22 is fed to the control inputs of the frequency divider 36 with a variable division factor and counter 33. In order for the output number For each counting period, the frequency of the divider 36 (Fig. 2k) was equal to the code of the number supplied to its information inputs, the frequency of the input and output signals, and the division factor of this divider should correspond to the ratio sig the input divider input, the selected division factor, the divider capacitance 36, or the number of pulses per signal period (FIG. 2k) T p, the number of output pulses; T p the number of input pulses; j with n N p K, i.e., if the number of pulses at the divider input for the reference period is equal to the capacitance of the divider, then the number of pulses at its output is equal to the number code at its information inputs. At selected TWI values from frequency dividers 13–15, the capacity of counter 23, register 22, frequency divider 36 with variable division factor, counter 33 is equal to 11. Sequence of pulses ТИ1 through the second input of AND 37 element supplied to frequency divider 36 with variable by the division factor, and from its output - to the first inputs of the AND 34 and 35 elements and to the subtracting input of counter 33. When the number of counter 33 is zero, and the signal level at its input corresponds to logical O, the signal at its subtracting output also corresponds to to the logical O, which is fed to the first input of the element I 37, ensuring the prohibition of the passage of pulses to the input of the frequency divider 36. If there is a number in the counter 33 on its subtractive output, the signal corresponds to the logic level 1, ensuring the passage of pulses from the sequence TI1 of the AND 37 element. The code from the output of the counter 33 goes to the code inputs of the counter 23. The output signal of the trigger 27 goes to the trigger input 29, the signal from its outputs are fed to the input element And 35, to the input of element 34 And and to the input of the trigger 31. The signal from the output of the trigger 31 is fed to the second trigger of the trigger 27. Thus, the signal pulse (figure 2), coming from the one-shot 21 to the input register 22 and in One trigger 31 rewrites the counting result from counter 23 to register 22 and the sign from trigger 29 to trigger 31, a signal pulse (FIG. 2) coming from the one-shot 30 to the front input of counter 23 and the trigger input 29 rewrites the number from counter 33 to the counter 23 and the sign from trigger 27 to trigger 29; the pulse of the signal (fig.2O t arriving from the one-shot 32 to the corresponding1; rj input of the counter 33 and the input of the trigger 27, rewrites the number from the register 22 into the counter 33 and the sign from the trigger 31 into the trigger 27. Pulses (figure 2, l, m respectively, with the one-shot 21, 30 and 32 take the time interval between pulses ТИ1 and ТИ2, immediately after the last counting period immediately after the last counting pulse ТИ1 from the frequency divider 13. With the value of "each counting period, the code of the number recorded in counter 33 is equal to 7 the impulses of his subtraction input d from the output of divider 36, and at values of os, the inhibitory potential supplied from the subtractive output of counter 33 to the input of element I 37 prevents the passage of TI1 pulses to the input of frequency divider 36 until its code changes at its information inputs and the code write in counter 33 is followed by a write pulse (Fig. 2m). At the same time, a code corresponding to zero from the output of counter 33 is recorded by a signal (Fig. 2A) into counter 23, and the count of the phase change follows the period of time relative to zero. For values f JL, the code entered into counter 33 does not have time to be compensated for the time of LT — the remainder from its output is again recorded into counter 23 with a signal (Fig.2l), and the sign into trigger 27 with a signal (Fig.2 A. Thus, in this case, the phase change of the next period is read off relative to the entered residue with its sign, and there is no loss of information. As follows from the time diagrams when the phase of the measuring signal changes relative to the reference one in the direction of lagging or leading by 2, the number The pulses output from the AND 33 element or the AND 34 element are equal to the division ratio of the dividers 13-15, therefore, one output pulse from these elements corresponds to a phase change equal to 2./1 L, where is the phase change resolution. The converter converts the phase change into the number of pulses of a unitary code in the case of correct input signals, in case of incorrect input signals, when there are oscillations of the measuring signal relative to the reference signal, and outputs the converter corresponding to these variations in alternately on pulses are influencing the quality of the devices connected vneschnih. In order to eliminate this drawback and agree on the discreteness of the reference phase change with an external device, signals from the outputs of elements 35 and 34 are fed to the inputs of the switch 38 and the first inputs of elements 39 and 40, respectively, and to the second inputs of these signals 41. The switch 38 commutes the signals to the inputs of the reversible counter 42 and from its pulsed positive output to the inputs of the AND 44 or 45 elements, depending on the input signal, the state of the trigger 43 at the time of input signal and the presence of in the counter there are 42 matches with the logic given in table 2. The discreteness of the phase change in this case, at the outputs of the elements 44 and 45, becomes equal to a ° 1 × Г. where N is the coefficient of division of counter 42. As can be seen from the obtained data, if the number of pulses that arrive at the inputs of the switch 38 in turn is less than the capacity of the counter 42, then the outputs of the elements 44 and 45 are not. The pulses at the outputs of the And 44 and 45 elements appear in the form of overflows of the counter 42 and the sign determined by the trigger when the counter 42 passes through zero with the arrival of the first pulse at the input of the switch 38. The maximum angular rate of phase change in the proposed converter (determined as the permissible change in the phase of the measuring signal, I. 7 .14, equal to the time T / 2 of the reference signal. Therefore, jf - ff - so, the phase pulse converter allows the conversion of the phase change to The impulses of the unitary code are switched by two outputs according to the sign of the phase change in case of correct and incorrect input signals and when the frequency of the reference signal deviates from the nominal value, which significantly increases its functionality. The proposed pulse-phase converter can be widely used for monitoring and adjustments in phase systems, CNC, for example for the purpose of graphical control of the control of 1x programs recorded on a magnetic tape, by means of It consists of an NZZ interpolator, a plotter AP-7251 and a UZK recording device, which provides indirect graphical control of control programs recorded on a magnetic tape, by supplying a pulse-number code from an interpolator to a plotter, a phase-impulse converter provides a direct graphical control of control programs recorded on a tape when its input is connected to the playback head, and the output is connected to the input. plotter. In this case, the monitoring can be performed both during the recording process, and repeated monitoring. The speed of pulling the magnetic tape during repeated control can be increased by more than. 10 times compared to the machine.

1 2 3 A 5

6

48 49 48 49 48 49

1 2 3 4 5 6

Table 1

-ABOUT

+ + 0 ID E «0 # 0

 b l and

c a 2

The number of countsSignals on the 42 dah counter 42

O 1 O O 1 1

0

+ + +

-ABOUT

0

fO

# 0

# 0

f

Claims (2)

1. A PHASE-PULSE CONVERTER, comprising a driver of the reference signal pulses, with an input connected to the bus of the reference signal, and an output with the first input of the first trigger, the first and second pulse generators of the measuring signal, inputs soy, repaired with the measuring signal bus, and outputs with the first inputs respectively, of the second and third triggers, the outputs of the first, second and third triggers are connected respectively to the first inputs of the first, second and third synchronizers, the outputs of which are connected respectively associated with the first inputs of the first, second and third elements And, outputs connected respectively through the first, second or third divider with the second inputs of the first, second and third triggers, the second input of the first synchronizer is connected to the second inputs of the second and third elements And clock pulses, the input of which is connected to the output of the clock generator, and the second output is connected to the second inputs of the second and third synchro-clocks and to the second input of the first element And, combinational with mmator having inputs connected to the outputs of the second and third AND gates, the first output is connected through a fourth divider with the first input of the first OR gate, a second input coupled to a second output of the combination. of the combiner, the output of the first divider through the first one-shot is connected to the control input of the register, the code inputs of which are connected to the outputs of the first counter, characterized in that, in order to expand the functionality, the first switch, fourth, fifth and sixth triggers are introduced into it, the second OR element, second counter, second and third one-shots, five AND elements, fourth divider, the first input of the first switch connected to the output of the first OR element and the first input of the fourth AND element, the second stroke - with the output of the first element And and the first input of the fifth element And, the third and fourth inputs are connected to the outputs of the fourth trigger, the fifth input is connected to the output of the second element OR and the second inputs of the fourth and fifth elements And, the outputs are connected respectively to the first and second the inputs of the first counter, the code outputs of which are connected to the inputs of the second OR element, and the third input is connected to the first input of the fifth trigger, through the second one-shot connected to the first input of the sixth trigger and the output of the first one-shot, and Through the third one-shot is connected to the first input of the second counter and the first input of the fourth trigger, the second and third inputs of which are connected respectively to the outputs of the fourth and fifth elements And, and the fourth input is connected to the output of the sixth trigger, the second input of which is connected to the first input of the sixth element And and the first output of the fifth trigger, the second input of which is connected to the first output of the fourth trigger, and the second output is connected to the first input of the seventh element And, the second input of which is connected to the second input of the sixth element And, with the second input of the second counter and through the fourth divider, with the output of the eighth element And, the first input of which is connected to the second input of the second synchronizer, and the second input is connected to the output of the second counter, the code inputs of which are connected to the code outputs of the register and the control outputs of the divider , and the code outputs are connected to the code inputs of the first counter. 2. The device according to claim 1, characterized in that, in order to expand the functionality, a second switch, a third counter, a third OR element, a seventh trigger and four AND elements are introduced into it, the first and second inputs of the second switch being connected respectively to the outputs of the sixth and seventh elements of And with the first inputs of the ninth and tenth elements of And, the second inputs of which are connected to the third input of the second switch and through the third elements OR with the code outputs of the third counter, and the outputs are connected to the inputs of the seventh trigger a gera, the first and second outputs of which are connected respectively to the fourth and fifth inputs of the second switch and the first inputs of the eleventh and twelfth elements And, the second inputs of which are connected to the output of the third counter, the inputs of which are connected to the outputs of the second switch.