SU1231495A1 - N-digit pulse distributor - Google Patents

Abstract

The invention relates to the field of computing and can be used as a multi-program cyclic channel switch. A distinctive feature of the device is the provision of a variable period in the forward and reverse direction. The aim of the invention is to expand the functional possibilities. The goal is achieved by introducing a multiplexer, two AND-NOT elements of an additional trigger, and introducing a selector distributor into each bit. I il. with with joint venture

Description

one

The invention relates to computing and can be used as a multi-program cyclic channel switch, controlled by a generator of code: sequences and a frequency divider with a variable division factor in discrete systems of automatic control and processing of digital information.

The purpose of the invention is to expand the functionality.

The drawing shows an N-bit pulse distributor.

The pulse distributor contains the inputs 1 of the installation, the inputs 2 reset, asynchronous short-circuit triggers 3, shapers 4 and 5 pulses, selectors 6 and 7, elements AND-HE 8 and 9, multiplexer 10, clock input 11, a group of 12 mode setting inputs, . group 13 vpsodov.

The N-bit pulse distributor operates as follows.

Before starting the operation of the distributors in any of the possible switching modes, its main N-flip-flop on inputs 1 and 2 are set to plugs corresponding to one of the code combinations of this switching mode, and on its group of 12 setting inputs the corresponding combination of single ones is set. and zero logical potential levels, B depending on the desired direction of switching

output channels (M + 1) —– the control trigger on inputs 1 and 2 is set. is cast to a single or zero logical position.

When the clock input arrives at 11 clock pulses, they pass through those drivers 4 and 5 pulses, at the information inputs of which in these clock cycles there are single logic potentials. Zero short pulses are generated from their trailing edges (decays) in the corresponding driver 4 and 5, which arrive at definite ones. (single or zero.) information- inputs of the discharge asynchronous triggers, and depending on the given switching pattern in this mode, they confirm their initial states or switch to opposite states.

50

15 th 5

five

0

0

In the forward direction mode, alternating switching of the output channels of the distributor (K + 1) -th trigger on inputs 1 and 2 is set to a single logical state. Depending on the required number of units, the pulses, which are continuously shifted over the discharge of the ring distributor, the corresponding group of main triggers are also set to one states at inputs i and 2, and the rest to the zero conditions. Zero logic potentials are applied to all inputs of the group 12 of the mode setting inputs. Due to this, the I-BE elements 8 and 9 are locked by the second inputs and, regardless of the logical potentials of the switchable output channels of the distributor, ensure the invariable initial logic state of the control (N + 1) -ro trigger. When applying clock pulses to the input P, an alternate ring shift to the right is recorded for the adjacent bits of the flip-flops of logical units.

The change in the number of logical units in shifted code combinations is carried out by changing the initial states of the trigger, t, e. by changing the number of units written in the bits.

 the ring shift in the backward pre-recorded coding of the coding nations distributor in the reverse direction of switching output channels is created when the control (K + 1) - th trigger is set to the zero initial state,

Rd of creating automatic switching of modes to the first control is ush; a single logical potential is applied to the input of group 12. This allows the I-BE elements 8 and 9 to control the process of automatic reversal of the control (N + l) -ro trigger on single signals alternately outputted from the first discharge output of the pulse distributor and from the output of the multiplexer 10, A to the address inputs of the multiplexer Plexor-10 applies a set of logical zero and unitary powers: s, which determines the length of the switching cycle in a given switching mode.

For example, to ensure complete cycles of circulation

3

different code combinations throughout

The distributor bit to the address inputs of the multiplexer, at the inputs 12, is applied a set of logical potentials, which provide the B of the last information input and, thus, connect to the output of the direct output of the trigger of the last bit of the distributor.

To provide shortened cycles of various code combinations, corresponding sets of logic potentials are applied to the address inputs of the multiplexer, providing connections to the output of the outputs of the corresponding trigger bits.

Claims (1)

Invention Formula An N-bit pulse distributor, containing in each discharge trigger, two pulse formers, with the outputs of the first and second pulse formers in each discharge of the pulse distributor connected to the first single and first zero inputs of the trigger, the second single and second zero inputs of the trigger, respectively the pulse distributor are respectively the installation inputs and the reset inputs of the pulse distributor, the forward triggers are the outputs of the pulse distributor, respectively tovy input coupled to the clock pulse shapers, characterized - in that, for the purpose of spreading functionality. invoice of the liver for forward and reverse directions of all possible N-cycle switching modes of the output channels with a variable period, a multiplexer, two; AND-NOT elements, an additional trigger, and two selectors are introduced into each distributor, and the outputs of the first and the second selectors in each bit, the distributor is connected to the informational inputs of the first and second pulse shapers, respectively; the direct output of the additional trigger is connected to the first control inputs of the first and second watts. ryh selectors all bits of the distributor, the second control inputs of which are connected to the inverted output s five 0 5 о 5 0 4954 additional trigger, the first input of the group of inputs of the distributor modes is connected to the first inputs of the first and second IS-NOT elements, the direct output of the first bit of the distributor is connected to the first information input of the first selector of the second bit of the distributor, with the second information input of the first selector -th bit and with the second input of the first element I-EE, the output of which is connected to the first single input of the additional trigger, the first zero input of which is connected to the output of the multiplexer In addition, the inputs of which are connected to the inputs from the second to (n + 1) -th group of inputs of the distributor modes, the second single and second zero inputs of the additional trigger are respectively the installation and reset inputs of the distributor, the first information input of the multiplexer is connected to the zero potential bus the distributor, the direct outputs of the bits from the second to the (n + 1) -th distributor are connected respectively to the first information inputs of the first selectors of the subsequent bits of the distributor, with the second information input inputs of the first selectors of the previous bits of the distributor and with information inputs from the second to (n-1) th multiplexer, direct output of the n-th the bit of the distributor is connected to the first information input of the first selector of the first bit., with the second information input of the first selector of the (n-1) -th bit and with the n information input of the multiplexer, inverse output of the first bit the limiter is connected to the first information input of the second selector of the second bit of the distributor and the second information input of the second selector of the n-th bit of the distributor, the inverse outputs of the bits from the second .to (p-1) -th distributor, respectively, are connected with the second information inputs of the first selectors of the previous bits and with the first information inputs of the second selectors of the subsequent distributor bits, the inverse output of the n-th distributor of the second $ 1231495 " the selector of the first bit of the distribution of the second selector (n-l) -ro and tel with the second information input of the distributor.