SU1171759A1 - Device for controlling flow rate - Google Patents

Abstract

1. A DEVICE FOR-REGULATION OF COSTS, containing a pulse generator, a flow meter, a first reversible counter sequentially connected to a second reversible counter and an adder, an actuator, o. in order to improve accuracy and speed, a pulse separation unit, a clock generator, a delay element, a code-frequency converter, an AND cell chip, two OR cells are entered into it. , controlled switch, functional converter, frequency multiplier, third reversible counter, register, with the output of the pulse generator connected to the iiep-r inputs of the pulse separation unit in time and the functional converter, the second inputs of which are connected to the output the flow meter, the first and second outputs of the pulse separation unit in time are connected to the addition and subtraction inputs of the first reversible counter with the first inputs of the SHS elements, the output of the clock generator is connected to the third inputs of the pulse separation unit in time and the functional converter, as well as to the first input frequency multiplier and through the delay element with the first input of the frequency converter, the output of which is connected to the first inputs of the first and second elements AND, the second inputs of which are connected S with the first and second outputs of the sign of the first river counter, the parallel output of which is connected to the parallel input of the S code-frequency converter and one input of the first and second OR elements, whose outputs are connected to the addition and subtraction inputs of the second reversible counter, and the other inputs With the output of the first and second elements And, the first and second outputs of the functional converter are connected to the first and second inputs of the controlled switch and to the first inputs of the third and fourth elements And, the output equal switch is connected to the second input of the frequency multiplier, the output of which is connected to the second. the inputs of the third and fourth elements I, connected by their outputs to the inputs of the subtraction and addition of the third reversible counter, the parallel output of which is connected to the parallel input of the register connected to its second output to the second input of the adder, and a significant output to the third input of the controlled switch, the third output .4) the functional converter is connected to the third input of the multiplier

Description

frequency and with the register recording input, the fourth output of the functional converter is connected to the fourth and to the input of the frequency multiplier and to the input to the reset of the reversible counter, the input of the adder is connected to the input of the actuator.

2. Device POP.1, characterized in that the pulse separation unit in time is made on one T-trigger, four G-triggers, four AND-NOT elements and two inverters, and the T-input of the T-trigger is connected to the first inputs of the first and the second element NAND, the direct output of the T-flip-flop is connected to the second input of the first N-element, and the inverse output of the T-flip-flop is connected to the second input of the second NAND element, the direct outputs of the first and second D-triggers are connected with I) -inputs, respectively, of the third and fourth D-flip-flops, and the inverse outputs of the latter with Rin With the respectively the first and second D-flip-flops, the output of the first AND-NOT element is connected to the T-input of the Third D-trigger and through the first inverter to the first input of the third AND-NAND element, the output of the second AND-NE element is connected to the T-input of even of the first J) trigger and, via the second inverter, with the first input of the fourth element NAND, the direct outputs of the third and fourth D triggers are connected to the second inputs of the third and fourth elements NAND, respectively, the outputs of which are connected respectively to the first and second the outputs of the imp block separation unit lsov connected to its first and second inputs respectively to the T inputs of the first and second D -triggerov.

3. The device according to Claim 1, vl and h it is due to the fact that the functional converter is made

- on two jK-flip-flops, two RS-triggers, two T-triggers, eight IS-NOT elements, an AND element and an inverter, and the inverse outputs of the first and second jK-flip-flops are connected respectively to the 5-inputs of the first and second RS-triggers, as well as with the first inputs of the first and second elements AND-NOT and with the first and second inputs of the element AND, the inverse output of the second jK-flip-flop is also connected to the R input of the first H3-trigger1) a, and the direct output of the last 11

it is connected to the second input of the first NAND element and to the third input of the I element, and the direct output of the second RS flip-flop to the second input of the second AND-NAND element and to the fourth input of the AND element, inverse outputs of the first and second RS triggers from are connected to the inputs of the third NAND element, the output of which is connected to the first input of the fourth NAND element, the output of the first NAND element is connected to the first j-input of the first jK flip-flop and the second input of the fourth AND-NAND element, and the output the latter is connected to the first j-input of the second jK-flip-flop, the output of the second ele I-NOT is connected to the second j, the input of the second K-flip-flop and to the input of the inverter, the output of which is connected to the second j-input of the first; K-flip-flop, the output of the AND element is connected to the first input of the R-in-fitsam first and second T-flip-flops, the output of the fifth element AND-NOT connected to the counting input of the first T-flip-flop, the first inputs of the sixth, seventh and eighth elements AND-NOT connected to the second input of the fifth element AND-NOT, the direct output of the first T-flip-flop is connected to the second inputs of the sixth and eighth NAND elements, and its inverse output is connected to the second input of the seventh NAND element and the counting input of the second T-flip-flop, whose direct output is connected to the third inputs of the seventh and eighth AND-NAND elements, and the inverse output to the third input of the sixth AND-NAND element, the output of the latter is connected to R- the input of the second RStrigger, the first and second inputs of the functional converter are connected to the C inputs of the first and second jK-flip-flops respectively, the direct outputs of which are connected respectively to its first and second outputs, the third input of the functional converter is connected to the first the input of the sixth element IS-NOT, the output of which is connected to the third output of the functional converter, the fourth output of which is connected to the top of the seventh element AND-NOT.

4. The device according to A.1, which is based on the fact that the frequency multiplier is made on the element I, the sum of the counting counter, the register, the subtractive counter and the frequency divider, with

In this case, the output of the element I is connected to the counting input of a summing counter, the parallel output of which is connected to the parallel input of the register, and the output of the latter is connected to the parallel input of the counting counter, the overflow output of which is connected to its installation input and output of the frequency multiplier, the output of the frequency divider is connected to the first input

element I ,, the input of the frequency divider is connected to the counting input of the subtracting counter and the first input of the frequency multiplier, the second input of which is connected to the second input of the element I, the third input of the frequency multiplier is connected to the enable input of the register, and its fourth input to the input of the summing counter.

one

The invention relates to the control of technological processes, in particular, to devices for automatic control of the flow of liquids and gases.

The purpose of the invention is to increase the accuracy and speed of the device.

Figure 1 presents the block diagram of the proposed device; 2, a functional diagram of a pulse separation unit in FIG. 3 is a functional diagram of a functional converter; figure 4 is a functional diagram of the frequency multiplier.

The device contains a pulse generator 1, a flow meter 2 with a frequency-pulse output signal, a pulse separation unit in time, a generator of 4 clock pulses, a first reversible counter 5, a delay element 6, a frequency converter 7, the first and second elements 8 and 9, elements OR 10 and 11, second reversible counter 12, controlled switch 13, functional converter 14, frequency multiplier 15, third and fourth elements AND 16 and 17, reversible counter 18, register 19, adder 20, digital-to-analog converter 21, performer the first mechanism 22.

Pulse separation unit 3 in time contains (FIG. 2) T-flip-flop 23, D-flip-flops, 24-27, AND-HE elements 28-31, inverters 32 and 33.

Functional Converter 14 contains (fig.Z) jK-triggers 34 and 35, R5-triggers 36 and 37, T-triggers 38 and 39, elements AND NOT 40-47, element 48, inverter 49.

The frequency multiplier contains (figure 4) element And 50, a summing counter 51, a register 52, a frequency divider 53, a subtractive counter 54.

5 Pulse separation unit 3 in time, generator 4, reversible counters 5 and 12, delay element 6, code-frequency converter 7, AND elements 8 and 9, and elements OR 10 and 11

O form a channel for measuring the mismatch and forming the first and second integral components of the control law.

Control switch 13,

15 a functional converter 14, a frequency multiplier 15, the elements 16 and 17, a reversible counter 18 and a register 19 form a channel forming a proportional component

20 of the law of regulation.

The device works as follows.

The pulse sequences, whose frequencies are proportional to the given flow rate and actual flow, are output from the generator 1c of the flow meter 2 to the inputs 55 and 56 of the pulse separation unit 3 in time, respectively. The work of the latter is controlled by a clock generator 4, from the output of which the pulse sequence with the frequency F is continuously fed to the T-input of the T-flip-flop 23 and to the inputs of the elements 28 and 29 ..

With each clock pulse, the thrigger 23 changes its state, alternately opening elements 28 and 29 to advance the clock pulses.

4Q Result at the element outputs

3

AND-NO 28 and inverter 32, a sequence of even clock pulses is formed, and at the inputs of the AND-NOT element

29 and inverter 33 — a sequence of odd clock pulses shifted in time relative to the even ones for a period of 1 / F. At the initial moment, the D-triggers 24-27 are in the zero state and the AND – NO elements

30 and 31 do not pass the clock, pulses from the inverter outputs to the outputs 57 and 58 of block 3. The input pulses of a given and actual flow received at the T-inputs of D-flip-flops 24 and 25 y put them into one state, as at the V-inputs Of these triggers, a single signal is constantly present. L-triggers 24

and 25 are independent, ke are in common, and are not clocked. Therefore, the pulses of a given and the actual flow can arrive at the T-inputs of the D-flip-flops 24 and 25 at arbitrary times and simultaneously.

Next, the operation of unit 3 takes place in four cycles. The first clock pulse from the output of element 29 overwrites the single information from D of trigger 25 to D-trigger 27. Element NO-NE 31 receives at its first input a resolving single signal from the forward trigger code 27. Simultaneously, the trigger 25 of the noR input is transferred to the original zero a state of zero signal from the inverse output of the T-zigger. 27.

The second clock pulse generated at the output of element 28 and shifted in time relative to the first one by 1 / F rewrites the single information from the B trigger of 24 to D trigger 26. Element 30 receives at its first input a resolving single signal from the direct output of trigger 26. At the same time, the trigger 24 at the R input is transferred to the initial zero state by the zero potential from the inverse output of the trigger 26. The inverted second clock pulse from the inverter output 32 passes through element 31 to the output 58 of block 3. At the last pulse corresponding to the actual flow rate of the flow meter 2f received at the input 56 of the block Zg

The third clock pulse generated at the output of the element 29 and shifted in time relative to the second

594

for the period I / F., returns the trigger 27 to the initial zero state in accordance with the state of the trigger 25. The inverted third clock pulse from the output of the inverter 33 passes through the element 30 to the output 51 of the block 3. A clock pulse appears on the latter. corresponding to the impulse of setting the flow rate from generator 1, received at input 55 of block 3, and shifted in time relative to impulse at output 58 for a period of I / FT-.

The fourth clock pulse generated at the output of the IS-NOT element 28 and shifted relative to the third by a period of 1 / F returns the trigger 26 to the initial zero state in accordance with the state of the trigger 24. As a result, unit 3 transitions to the state corresponding to the initial moment his works. The cycle of operation of the block is repeated when the next pulses of the task and the actual flow are received at the inputs 55 and 56.

Since the working cycle of block 3 takes four clock cycles, equal to the value of the clock frequency F must satisfy the condition

 Ft, fj.

In order to form an integral component in the law of regulation, from outputs 57 and 58 of the unit .3 the separated pulses in time arrive at

inputs of addition and subtraction of the first reversible counter 5, as well as through the elements OR 10 and 11 to the inputs of addition and subtraction of the second reversible counter 12.

If the frequencies F and Fj are unequal, counter 5 accumulates a code proportional to the integral of the difference of frequencies F and F2. K0D from counter 5 is fed to the converter 7 code

executed, for example, according to the scheme

binary multiplier. The other input of the converter 7 through the delay element 6 receives the pulses of the generator 4 with a frequency F. From the output of the transducer 7, a sequence of pulses with a frequency proportional to the clock frequency F and the code from counter 5 is transferred, depending on the code code, through AND 8 or 9, and through IL 10 and 11 elements to the addition or subtraction input of counter 12. Delay clock pulses at the input of the converter 7 code-frequency relative to the pulses at the output of the block provides the addition of difference. frequencies P - F. with frequency, proportional to the code from counter 5, i.e. the integral of the difference frequency F 2 As a result of integrating the resulting sum of frequencies at the output of counter 12, a code is formed that is proportional to the sum of the two components: the integral of the difference frequency 2 of the double integral of the same difference. At the same time, to form a proportional component, the pulse sequences with frequencies F and F are fed to the inputs 59 and 60 of the converter 14, and to the input 61 clock pulses with a frequency F. The switch of 14 periods forms two sequences of mutually alternating pulses with durations equal to the period T of the impulses following the output task 62 and the period T following the impulses from the sender 3 flow at output 63, and the pulse commands Record and Reset at outputs 64 and 65, respectively necessary for controlling the sequence of operation of the elements of the formation channel of the proportional component. The formation of the proportional component is carried out by comparing the periods T and T. For comparison, the pulses equal in duration to the periods T and T. at spaced moments of time are filled with the reference frequency Fjjp, and Fgj, 77 F. The resulting codes are subtracted and as a result, the number N is equal to NK i -TilFon (1) or considering T 1 / F / Number N is proportional to the difference of frequencies F and F2. . To reduce the effect of non-linearity introduced by the product of P F in the denominator of expression (2), the reference frequency Fon does not remain constant, but changes proportionally more from the compared frequencies KF. when P1-P270; gkF2, whenF, where K - coefficient of proportionality. As a result, expression (2) is prefixed to the form -p. P i The specified Record and Reset commands are generated cyclically. Pulses with durations T and T are formed on single outputs jK of the triggers 34 and 35. In the initial state, the jK-triggers 34 and 35 are in zero, and R5-triggers 36 and 37 in the single state. At the same time, at the first and second inputs of the AND-EE elements 40 and 41 there are l signals, and at the outputs - O signals. Zero output signals of the AND-HE elements 40 and 41 arrive at the first j-inputs of the triggers 34 and 35 and. thereby keeping them in the zero state. Thus, the elements AND-NOT 40 and 41 together with the RS triggers 36 and 37 form the self-calibration circuits of the triggers 34 and 35. The AND-NOT element 42 and the inverter 49, connected by their outputs to the second j-inputs, respectively, of the triggers 35 and 34, form interlocking chains last. In the initial state, at the outputs of the NAND 42 element and the inverter 49 there are signals 1 and both interlocks do not work. Element And 48 controls the outputs of the flip-flops 34-37 and in the initial state of the converter 14 on all its inputs and outputs there are signals 1.-T-triggers 38 and 39 form a scaling circuit for four clock cycles and at the initial moment are in the zero state . Zero signals from the direct outputs of the flip-flops 38 and 39 prohibit the passage of pulses of the clock, frequency F, through the elements IS-NE 45-47. The single signal from the output of the AND 48 element allows the passage of clock pulses through the AND-NOT element 44 to the count input of the Trigger 38. During the counting process, the resolving unit potentials appear alternately at the inputs of the elements 45 - 47. Clock pulses, the passage through the elements AND-NOT 45-47, form at their outputs impulse commands Record, Reset and Start,

7 1 With the last command, Start RS, trigger 37 is set to the zero state. At the output of the element And 48, a signal O appears, which prohibits the further arrival of the clock pulses at the counting input Ttrigger 38c on the R input, sets the T-triggers 38 and 39 to zero. Commands are terminated before the start of the next cycle. At the same time, the signal 1 appears at the output of the IS 41 element, and the signal O at the output of the inverter 49. The self-blocking of the trigger 35 is removed, and the trigger 34 is activated by the interlock signal from the output of the inverter 49. With the arrival of the next pulse from the flow meter output input 61 and the counting input of the trigger 35, the latter goes into one state. At output 63 of the converter, signal 1 appears. At the same time, P5-flip-flop 36 changes its state — goes to zero, and R5-flip-flop 37 returns to one state under the action of a negative potential drop at the inverse output of jK-flip-flop 35. At the output Signal element I-NE 40 appears 1. Self-blocking from trigger 34 is removed, but it remains locked by the second j-input by the interlock signal from inverter 49. Trigger 34 is held in the zero state regardless of the effect on its counting input of target pulses R, . With the arrival of the next pulse from the flow meter through peri1 T, f, the trigger 35 returns

in zero state. At output 63, signal 1 is transferred to signal O, thereby completing the formation of a single pulse, equal in duration to the pulse flow time of the flow meter. At the same point in time, the self-blocking of the trigger 35 is activated and the interlocking of the trigger 34 is removed. Next, the trigger 34 generates a single pulse at the output 62, equal in duration to the follow-up period T of the generator 1 output, after which the trigger 34 becomes self-locking. In this part of the cycle, trigger 35 is not released from self-blocking, unlike trigger 34, since there is no cross-link with inverse17598

the trigger output 34 to the R input

Trigger R5 37. This link replaces the chain of the Run command.

As a result, the period switch returns to its original state. Then the cycle repeats.

The AND-NE element 43 prevents the converter from being set to a false steady state, which is possible when the device is turned on, by eliminating the simultaneous action of two interlocks.

The formed single pulses with durations T and I alternately pass through elements AND 16, 17 to the inputs of the reversible counter 18 a sequence of pulses following with a reference frequency, F-Epii, which are the pulses of the reference frequency P filling the period T. , and the filling period T is to the input of subtracting the counter 18, previously cleared by the Reset command.

In counter 18, the number N is formed,

.

equal (F or

So

Thus, in one cycle of operation of the converter 14, a code proportional to the frequency difference F, F2 is formed on the outflow of the reversible counter 18.

With the Record command, following the formation of the pulse T, the counter code 18 is rewritten into register 19, after which the Reset command prepares the counter for the next measurement cycle. At the output of register 19, a constant is proportional to the frequency difference R) and F, updated for each measurement cycle — the operation cycle of the converter. Maximum cycle time is

T, + 2Tj, at T2 T, -,,

(five)

2T, + T ,,

at T T

The product F Fvj makes non-linear dependence of the code at the output of the register 19 on the frequency difference.

V

To approximate the dependency, Mr.

Pi

f-iPi

to linear, as well as to ensure the stability of the device in a wide range of tasks (frequency F) flow rate, the reference frequency F is formed by multiplying the frequency R or F2 by the proportionality coefficient K with the help of frequency multiplier 15. As an input signal of the multiplier, pulses T and T are used, coming from outputs 62 and 63 of converter 14 through a controlled switch 13. The latter is controlled by the potential of the sign bit of register 19. When the sign of the number N in the register is positive, i.e. F -FjO, the input of multiplier 15 receives a pulse T, and the frequency R, is multiplied. At the opposite sign of F g, frequency multiplication occurs. Thus, the reference frequency P is determined by P GCRD, at P, KRg at F, the frequency multiplication occurs as follows (Fig. 4) A single pulse with a duration equal to the period of one of the frequencies, for example, T 1 / F, entering the input 66 of the element I 50, permits the passage of 51 clocks with a frequency to the counting input of the summing counter. FJ- divided by the frequency divider 53 by the proportionality coefficient K. During the period T, counter 51 accumulates K pulses: from N, A.T to 1. The number N with a parallel code is rewritten into register 52 by the Record command received from the period switch, followed by counter 51. set to zero by the command; Reset. The output parallel code of the numbers of the register 52 is fed to the parallel input of the subtracting counter 54. The code N is periodically entered into this counter by an overflow pulse on the subtraction bus P and written off to zero on the counting input by clock pulses with a frequency Fy. At the output P of the counter 54, the overflow pulses follow with a frequency equal to the reference frequency n Fr / N; . P / TT-KF. During the cycle of forming the pulses T and T and writing the number N to the reversible counter 18, the reference frequency Fgf is constant, and the frequencies R and F2 are compared under the same conditions. At the same time, a new value of N is written to summing counter 51, and the cycle repeats with synchronization with converter 14. Thus, the output of register 19 forms a code proportional to the frequency difference F and F by expression (4). The value of coefficient K is selected depending on from the design features of the flow meter 3 and the actuator 22; The code N is summed in the binary adder 20 with a code proportional to the sum of the first and second integrals of the frequency difference F - F. The algebraic sum of the codes from the output of the adder 20 is fed to a digital-analogue converter 21, from the output of which the control signal is fed to the actuator 22. The control signal translates the actuator to a position whereby the frequency Fl is established, and F, i. compliance with the actual flow specified. The time required to form a code N, proportional to the frequency difference 2, is, according to expressions ts), no more than three periods of one of the pulse sequences. In this case, there is no need to use a smoothing filter. This means that in terms of speed the proposed device surpasses the known one, in which the use of smoothing filters is fundamentally necessary for frequency conversion to voltage. The use of the invention will almost completely eliminate the instrumental errors of the mixing and metering processes, expand the functionality of these process control systems by using high-speed actuators, for example, drive motors of metering pumps operating in the flow meter mode when equipped with frequency converter converters to the frequency of electrical pulses. Ensuring the processing of each impulse of a task coming from the generator guarantees not only the exact maintenance of a given flow rate, but also the same exact correspondence

11117175912

the volume flowing through the flow meter is not a task in the process. This medium is proportional to the quantity. The property of the invention is valuable when its impulses are received for any use in a continuous time systems from an independent proportional dosing generator.

MO from the effects of perturbations and treason-5 and mixing.

2

50

I

TO

5C

Claims (4)

1. DEVICE FOR REGULATING THE FLOW, containing a pulse generator, a flow meter, a first reversible counter, and a second reversible counter and an adder connected in series, an actuator, characterized in that, in order to improve accuracy and speed, a pulse separation unit in time is introduced into it, a generator clock pulses, delay element, code-frequency converter, four AND elements, two OR elements, controllable switch, functional converter, frequency multiplier, third reverse with a counter, a register, wherein the output of the pulse generator is connected to the first inputs of the pulse separation unit in time and the functional converter, the second inputs of which are connected to the output of the flowmeter, the first and second outputs of the pulse separation unit in time are connected to the addition and subtraction inputs of the first reversible counter and with the first inputs of the OR elements, the output of the clock generator is connected to the third inputs of the time separation unit and the functional converter, as well as the first smart input ozhitelya frequency and delay element through the first input kodchastota converter whose output is connected to first inputs of first and second AND gates, whose second inputs are connected to first and second outputs of the first plate r.eversivnogo counter, whose parallel output is connected to a parallel input converter _'n code-frequency and one of the inputs of the first § and the second OR element, the outputs of which are connected to the inputs of addition and subtraction of the second reversible counter, and the other inputs are with the outputs of the first and second elements AND, n The first 5 and second outputs of the functional converter are connected to the first and second inputs of the controlled switch and to the first inputs of the third and fourth elements AND, the output of the controlled switch is connected to the second input of the frequency multiplier, the output of which is connected to the second inputs of the third and fourth elements AND, connected by their outputs with the inputs of subtraction and addition of the third reversible counter, the parallel output of which is connected to the parallel input of the register connected by its parallel output to the second the adder’s input, and the sign-on output - with the third input of the controlled switch, the third output of the functional converter is connected to the third input of the frequency multiplier and to the register recording input, the fourth output of the functional converter is connected to the fourth. input of the frequency multiplier and to the reset reset of the counter, the output of the adder is connected to the input of the actuator. 2. The device according to claim 1, characterized in that the pulse separation unit in time is made on one T-trigger, four-triggers, four NAND elements and two inverters, the T-trigger of the T-trigger connected to the first inputs of the first and of the second AND-NOT * elements, the direct output of the T-trigger is connected to the second input of the first element AND-NOT, and the inverse output of the T-trigger is connected to the second input of the second element AND, the direct outputs of the first and second D-triggers are connected to D - inputs of the third and fourth D-flip-flops, respectively, and the inverse outputs of the latter with Rin by the first and second D-flip-flops, respectively, the output of the first AND-NOT element is connected to the T-input of the third D-trigger and through the first inverter to the first input of the third AND-NOT element, the output of the second AND-NOT element is connected to the T-input the fourth D-trigger and through the second inverter with the first input of the fourth AND-HE element, the direct outputs of the third and fourth D-triggers are connected to the second inputs of the third and fourth AND-HE elements, respectively, the outputs of which are connected respectively to the first and second outputs of the pulse separation unit in connected to its first and second inputs respectively to the T-inputs of the first and second D-triggers. 3. The device according to claim 1, which implies that the functional converter is made. Not two jK-triggers, two RS-flip-flops, two T-flip-flops, eight AND-NOT elements, AND element and inverter, moreover the inverse outputs of the first th second j'K-flip-flops are connected respectively to the S-inputs of the first and second RS-flip-flops, as well as with the first inputs of the first and second elements AND-NOT and with the first and second inputs of the AND element, while the inverse output of the second jK -trigger is also connected to the R-input of the first / 23-trigger1> a, and the direct output of the latter is connected to the second input house pervoto AND-NO element and to third input of the AND, and a direct output of the second RS-flip-flops - with the second input of the second AND-NOT element and with the fourth input of the AND element, the inverse outputs of the first and second RS-triggers are connected to the inputs of the third 'AND-NOT element, the output of which is connected to the first input of the fourth AND-NOT element the first AND gate is connected to the first j-input of the first jK trigger and to the second input of the fourth AND gate, and the output of the last is connected to the first j input of the second jK trigger, the output of the second AND gate is connected to the second j input of the second jK-flip-flop and with an inverter input, the output of which is connected to volt by the j-input of the first jK-trigger, the output of the AND element is connected to the first input of the fifth element of the AND-NOT element and to the R ^ inputs of the first and second T-triggers, the output of the fifth element of AND-NOT is connected to the counting input of the first T -trigger, the first inputs of the sixth, seventh and eighth elements AND are NOT connected to the second input of the fifth element AND, the direct output of the first T-trigger is connected with the second inputs of the sixth and eighth elements AND, and its inverse output is with the second the input of the seventh element AND NOT and the counting input of the second T-trigger, the direct output of which is connected with the third inputs of the seventh and eighth elements AND-NOT, and the inverse output with the third input of the neck of that element AND-NOT, the output of the latter is connected to the R-input of the second RS trigger, the first and second inputs of the functional converter are connected to the C-inputs respectively, of the first and second jK flip-flops, the direct outputs of which are connected respectively to its first and second outputs, the third input of the functional converter is connected to the first input of the sixth AND-NOT element, the output of which is connected to the third output of the functional converter , the fourth output of which is connected to the output of the seventh element AND NOT. 4. The device according to claim 1, characterized in that the frequency multiplier is made on the element And, the totalizing counter, register, subtracting counter and frequency divider, while the output of the element And is connected to the counting input of the totalizing counter, the parallel output of which is connected to the parallel input of the register and the output of the latter is with a parallel input of the subtracting counter, the overflow output of which is connected to its installation input and the output of the frequency multiplier, the output of the frequency divider is connected to the first input of the element And, the input of the frequency divider connected to the counting input of the subtracting counter and the first input of the frequency multiplier, the second input of which is connected to the second input of the And element, the third input of the frequency multiplier is connected to the enable input of the register, and its fourth input is connected to the blanking input of the summing counter.