SU446879A1 - Discrete pulse frequency multiplier - Google Patents

Description

one

The invention can be used in the field of automation, computing and measuring equipment.

Discrete pulse frequency multipliers are known, including a period-to-code conversion counter, a multiplier-frequency period pulse-generator, multiplying frequency sources, triggers, coincidence circuits, and collective circuits.

However, the known multipliers do not provide the required accuracy, a wide range of multiplication and do not work when changing over a wide range of multiplied frequencies.

The aim of the invention is to improve the accuracy of operation and the expansion of the range of multiplication.

For this purpose, a multiplied frequency period change counter, a multiplication factor setting counter, a multiplied frequency period code register, a multiplication coefficient code register, a device for setting a conciliation factor, and a multiplication factor recalculation pulse generator are introduced, and the frequencies through the corresponding coincidence circuits are associated with the output of the same counter and with the outputs of the memory register of the period code connected through other corresponding circuits s

coincidence to the bit outputs of the said period-to-code conversion counter, and the input and bus of setting it to its initial state are respectively connected through the circuit

match with the output of the multiplier setting counter and with the input terminal of the multiplied frequency source, also connected to the installation bus to the initial state of the conversion counter of the period to the code, with the register of the iodine code of the multiplied frequency directly and through the collecting circuit with the output terminal, the bit inputs of the counter for setting the multiplication factor through the third

the corresponding coincidence circuits are connected to the output of the same counter and to the outputs of the memory register of the multiplication coefficient code, the input of which is connected to the output of the multiplication factor setting device; the counter input is connected to the output of the multiplication coefficient conversion generator; the resolution source terminal is connected to the inputs of the period-to-code conversion counters and the period changes of the multiplied frequency and to the output terminal via a collecting circuit.

The functional circuit of the discrete multiplier is shown in the drawing. The composition of the discrete frequency multiplier

the following pulses enter the counter 1 pret. i I-,

  ““ Ki

 h,

-4468 formation of a period into a code, a counter 2 changes a period of equal frequency, a counter 3 specifying a multiplication factor, a generator of 4 emulsions complied with a period of a multiplied frequency, a generator of 5 pulses of a recalculation of a multiplication factor, a register of a multiplied frequency period code, a register 7 of us of that coefficient code multiplication, Soviadeia schemes 8-18, collective scheme 19, device 20 given multiplication factors, triggers 21-25, delay elements 26-29, input terminal 30 of multiplied frequency source, signal source terminal 31 and and output terminal 32. The multiplier operates as follows. The input signals of the multiplied frequency are input to the input terminal 30. When the permission signal is applied to the terminal 31 at the time ti, the coping scheme 13 opens and the pulse of the input multiplied input sequence first after the moment ti passes through the specified co-driving circuit, translates the trigger 21 into a single state and through the collective circuit 19 enters the output device. As a result, the coincidence circuit 11 is opened and the period filling pulses from the output of the generator 4 impulses of filling the period of the multiplied frequency begin to pass to the input of the period conversion counter 1 to the code. The counting of the counter of the transformation of the neorod into the dry code, is confirmed until the next moment of its arrival, the pulse of the multiplied sequence, which nullifies the counter 1 of the period in the code. As a result, over the time interval between the two input pulses in the period-to-code conversion counter 1, information in a code representation is generated, which characterizes the code of the frequency multiplying period. With the arrival of the next (second after the resolution signal supplied) multiply frequency wave, the information pushed in the counter 1 of the conversion of the neyrode to the code is transmitted through the coincidence circuit 8 to the register 6 of the memory of the multiplied frequency period code, and the counter of the conversion of the neorod to the code is zero. is. The required temporal displacement by the moments of information transfer and the zeroing of the counter 1 for converting the neyrode into a code is carried out at the expense of delay elements 26 and 27. At the same time, after the permitting signal is supplied, which is also fed to one of the inputs of the circuit 12, the pulse of the multiplied sequence is received through the terminals 13 and 14, and through the circuit 18 of the coincidence signals from the output of the generator 4 pulses of the multiplied frequency period. Further, the impulse from the output of the joint circuit 13 through the delay element 28 passes to the counting input of the trigger 23, its transfer from the zero to the single state. In this case, an unlocking signal is applied to the coincidence circuit 15. When the next pulse of the multiplied frequency is fed, the signal from the output of the match circuit 14, via circuit 15, coincides with the input of the trigger 24, failing to return it to one state. As a result, the coincidence circuit 12 opens and the counting pulses from the output of the counter 3 set the multiplication factor to the input of the counter 2 of the replaced multiplied frequency multiplier. At the same time, scheme 14 of the joint venture is locked. Signals to the input of counter 2 of the multiplication frequency multiplier are delayed by one input multiplied frequency, which is necessary for the normal operation of the device, i.e., the code of the input code is determined in the first input frequency, the information on which is then used to obtain the multiplied sequence. frequencies. For getting information about the multiplied frequency during the nerve neorod of the input sequence, a circuit consisting of schemes 16, 17 and 18 of the assembly and triggers 22 and 25 serves. After iodachi the resolution signal to terminal 31 and the signal to terminal 30, the output of the conjunction circuit 18 passes the signal from the output of the generator 4 pulses of the period of the multiplied frequency and simultaneously from it to the input of the coincidence circuit 17. From the output of the coincidence circuit 18, the signal through the delay element 29 passes to the counting input of the trigger 22, translating it into a single state. In this case, the coincidence circuit 16 is opened and the signals from the output of the counter 3 of the multiplied factor are passed to its output. These signals are then fed through the collecting circuit 19 to the output terminal 32 of the device, forming, together with the pulse of the multiplied sequence, the first signals of the multiplied pulse sequence. The number of pulses from the output of the counter 3 sets the multiplication factor contained in the period of the signals from the generator output 4 pulses of the multiplication of a neyrode multiplied; This is possible due to the fact that the pulse repetition rates from the outputs of the 3 adann counter of the multiplication factor and the 4 nm generator of filling the multiply frequency period are in a ratio equal to the multiplication factor. It should be noted that the frequency of the following pulses from the output of the counter 3 set by the multiplication factor is always greater than or equal to the frequency of the pulses from the output of the generator 4 of the pulses of the non-multiplication frequency. When the next signal arrives from the output of the generator 4 pulses of filling of a non-multiplicated frequency, triggers 22 and 25 are triggered. As a result,

matching schemes 16, 17 and 18, which is necessary for the normal functioning of the device. The signals from the output of the counter 2 of the period change by multiplying the frequency through the collecting circuit 19 are fed to the output terminal 32 of the device, forming a sequence of multiplied frequency pulses, and to the control inputs of the matching circuit 9.

As a result, information about the period code of the multiplied signal stored in register 6 of the memory code of the period of the multiplied frequency is transmitted through a coincidence circuit 9 to the counter 2 changes the period of the multiplied frequency, forming its initial setpoint. Thus, depending on the value of the period code at the output of the counter 2 of the period of the multiplied frequency at a certain multiplication factor, i.e., at a certain pulse frequency at its input, a well-defined frequency of the multiplied frequency pulses is established. The greater the period of the multiplied frequency, the greater the conversion factor of counter 2, the change in the period of the multiplied frequency, and the lower the frequency of the recalculation pulses at its output, which is necessary in practice, since it ensures the necessary uniformity of the output sequence. It should be noted that each subsequent pulse of the multiplied frequency periodically resets the old information in the register of the code of the period of the multiplied frequency and records information about the new period.

The signals from the output of counter 2 of the change in the period of the multiplied frequency 2 are generated when it reaches zero information, i.e. simultaneously with the last pulse being written off, the output signal is generated (unlike the loan signal WHICH is generated when the next input signal is fed to the counter input in the zero state). This is accomplished by introducing into the counter 2 a change in the period of the multiplied frequency of the coincidence circuit and the delay element, which are not shown in the functional diagram of the device.

Obtaining a change in the period of the multiplied frequency, depending on the magnitude of the multiplication frequency of the pulses at the input of counter 2, is performed using a discrete controlled pulse generator, which includes a generator of 5 multiplication counts of pulses, the multiplier setting counter 3 , matching circuit 10, memory register of multiplication factor code 7.

From the output of the generator 5, the pulse of the recalculation of the multiplication factor is a sequence of pulses fed to the input of the counter 3, specifying the multiplication factor, where it is recalculated.

Moreover, the conversion factor is set by information from the register 7 of the memory of the code of the multiplication factor through the coincidence circuit 10. In register 7 of the memory of the multiplication coefficient code, information is recorded from the device 20 for setting the multiplication coefficient. With a constant multiplication factor, the information in memory register 7 of the multiplication factor code remains unchanged and is updated only when the multiplication factor is changed. The larger the value of the multiplication factor, the smaller the conversion factor and the greater the frequency at the output of the counter 3, the setting of the multiplication factor.

The recalculation signals from the counter 3 output of the multiplication factor are given

also on the control inputs of the circuits 10 coincidence.

As a result, the information, imperative in the memory register 7 of the multiplication coefficient code, is transmitted to the counter 3 to set the multiplication factor as the initial setpoint and a new recalculation cycle begins. The process then repeats. The minimum setpoint value at which the output frequency is equal to the frequency of the pulses from the generator output 4 of the pulses of the multiplied frequency period corresponds to a coefficients reduction of 1.

The number of pulses received during a period of multiply frequency

The pa of the input of the counter 1 is a period conversion into a code, is defined as

",(one)

- SPTA

TEX - the period of the input multiplied chagda stota;

.: - the repetition period of the filling pulses with the sweep of the generator of the 4 filling pulses of the period of the multiplied frequency; “I is the number of impulses. received at the input of the counter 1 period conversion into the code for the period GG.U.

The period of the multiplied output pulse sequence is determined by the expression

j umt-gerssch. t, (2)

where Tug - output period multiplied

pulse sequences; Thoros-g. - the period of sequential recalculation pulses at the input of the counter for changing the period of the multiplied frequency 2.

The period of the frequency of the following pulses is equal to

(3)

60

scroll

where t ,. - perpod of the initial pulse frequency from the output of the counter 3, specifying the multiplication factor in the absence of wm65 (n 1).

Substituting expressions (1) and (3) into (2), we obtain the final expression for the period of the multiplied frequency

Gwh

 141

(four)

clever

 zap1

OR In the frequency representation

 have ISH / BN

f:

P.

clever

/ zap

It follows that the magnitude of the multiplied frequency / uyn is directly proportional to the multiplication factor n and the input multiplied frequency / them, which is necessary for the multiplication operation.

Frequencies / Ref and ARE CONSTANT

and their ratio can be considered as a constant coefficient / s.

The faani frequency is selected based on the conversion of the period into a code with a given accuracy (discrete error).

The frequency / ref is selected from the following considerations. Let us put in expression (5) p I. At the same time, obviously, the multiplied frequency / s should be equal to the input / output from here / out f zap,

Thus, it follows from the foregoing that the discrete pulse frequency multiplier provides a significant increase in multiplication accuracy and a wider range of multiplication.

The increase in multiplication accuracy here is due to the fact that the output multiplied sequence is evenly uniform at any values of the input frequency period and the multiplication factor. The expansion of the multiplication range is due to the fact that there are practically no restrictions on the multiplier in both the multiplication range and the frequency band of the input sequence.

Claims (1)

Invention Formula Discrete pulse multiplying frequency multiplier, containing a period-to-code conversion counter, a multiplied frequency period wave generator, a multiplied frequency source, triggers, coincidence circuits, and collective circuits, in order to improve the accuracy operation and expansion of Dianzon multiplication, a multiplied frequency change period counter, a multiplication factor setting counter, a multiplied frequency period code register, a multiplication coefficient code memory register, The setting of the multiplication factor and the generator of recalculation of the multiplication factor, and the bit inputs of the counter for changing the period of the multiplied frequency through the corresponding coincidence circuits are connected to the output of the same counter and to the outputs of the memory register of the period code connected through other appropriate coincidence circuits to the bit outputs the period conversion counter to the code, and the input and the reset bus of its initial state are respectively connected via a matching circuit with the output of the counter and multiplying the one input terminal with the frequency multiplied signal source coupled to the installation bus and with the starting state of the counter conversion period in the code memory register with a period code are multiplied the frequencies directly and through the collecting circuit are with the output terminal, while the bit inputs of the counter for setting the multiplication factor through the third corresponding coincidence circuits are connected to the output this counter and with the outputs of the memory register of the multiplication coefficient code, the input of which is connected to the output of the device for setting the multiplication factor, the input of the counter is connected to the output of the pulse generator recalculating the multiplication factor, and the terminal of the source of the resolution signal is connected to the inputs of the period conversion counters to the code and changing the period of the multiplied frequency and with the output terminal of the device through the collective circuit.