SU375821A1 - - Google Patents

Info

Publication number
SU375821A1
SU375821A1 SU1727816A SU1727816A SU375821A1 SU 375821 A1 SU375821 A1 SU 375821A1 SU 1727816 A SU1727816 A SU 1727816A SU 1727816 A SU1727816 A SU 1727816A SU 375821 A1 SU375821 A1 SU 375821A1
Authority
SU
USSR - Soviet Union
Prior art keywords
dielectric
layer
foil
contact
areas
Prior art date
Application number
SU1727816A
Other languages
English (en)
Russian (ru)
Inventor
Т. А. Самарцева В. Д. Позднее
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to SU1727816A priority Critical patent/SU375821A1/ru
Application granted granted Critical
Publication of SU375821A1 publication Critical patent/SU375821A1/ru

Links

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
SU1727816A 1971-12-22 1971-12-22 SU375821A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU1727816A SU375821A1 (de) 1971-12-22 1971-12-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU1727816A SU375821A1 (de) 1971-12-22 1971-12-22

Publications (1)

Publication Number Publication Date
SU375821A1 true SU375821A1 (de) 1973-03-23

Family

ID=20497060

Family Applications (1)

Application Number Title Priority Date Filing Date
SU1727816A SU375821A1 (de) 1971-12-22 1971-12-22

Country Status (1)

Country Link
SU (1) SU375821A1 (de)

Similar Documents

Publication Publication Date Title
US3791858A (en) Method of forming multi-layer circuit panels
ATE82529T1 (de) Verfahren zur herstellung mehrschichtiger halbleiterplatten.
GB1268317A (en) Improvements in or relating to the manufacture of conductor plates
US2965952A (en) Method for manufacturing etched circuitry
SU375821A1 (de)
GB1262245A (en) Production of circuit boards
CN114760771B (zh) 线路板上导通孔的保护方法
DE3377454D1 (en) Method and apparatus for the selective and self-adjusting deposition of metal layers and application of this method
ATE96978T1 (de) Verfahren zum herstellen von durchkontaktierten leiterplatten mit sehr kleinen oder keinen loetraendern um die durchkontaktierungsloecher.
ES349275A1 (es) Un metodo de producir un dibujo de circuito conductor de configuracion previamente determinada.
JPS625356B2 (de)
JPH01137693A (ja) プリント基板の製造方法
JPS6345888A (ja) バンプ付配線板の製造方法
JPS59114889A (ja) 導電体パタ−ンの形成方法
JP2919423B2 (ja) 印刷配線板の製造方法
JP2661231B2 (ja) プリント配線板の製造方法
JPS58132995A (ja) 導電ペ−ストのはんだ付け方法
JP2500659B2 (ja) 印刷配線板の製造方法
JPS5916930B2 (ja) 積層板の製造方法
JPH0373593A (ja) フレキシブルプリント配線板の製造方法
JPH0354873B2 (de)
JPH0329346A (ja) 半導体パッケージ用基板に回路を形成する方法
JPH08213737A (ja) 導体形成方法
JPH0137877B2 (de)
JPS6052087A (ja) プリント板製造方法