SU1742854A1 - Device for controlling of matrix display - Google Patents

Abstract

The invention relates to automation and information technology, mainly to devices for forming images of alphanumeric characters on a small-format indicator of matrix organization. The purpose of the invention is to increase the brightness of the image by highlighting the optimal number of symbol segments. The goal is achieved by introducing into the device containing 1 clock pulse generator, counter 2, first decoder 3, digital-to-analog converters 5, 6, matrix indicator 7, memory block 8, second decoder 9, and delay element 10 with circuit connections described in claims. The invention made it possible to simplify the process of converting information by the decoder 3, increasing the quality of the image by eliminating empty elements of a simple (minimal) character, an optional & required to highlight a symbol with the maximum number of necessary symbol elements. 1 il.

Description

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The invention relates to automation and information technology, mainly to devices for forming an image of alphanumeric characters on a small-format indicator of matrix organization.

A device for controlling a matrix indicator, comprising a generator and counter connected in series, a decoder, the first group of inputs of which is connected to the outputs of the counter, and an indicator are known.

However, this device has a low

the input of which is the information input of the device, the address gap is connected to the output of the counter, and the output

, the memory unit is connected to the information inputs of the first and second decoders, the output of the second decoder is connected to the installation input of the counter, the input of the permission of which account

10 is connected to the memory read / write control input and to the control input of the clock generator and is the control input of the device, the input of the delay element is its quality due to its weak dinen with the sync input contrast contrast

Closest to the invention is a device for controlling a matrix indicator, comprising a series-connected generator and a counter, the outputs of which are connected to the first group of inputs of the decoder, digital-analogue converters, the inputs of which are connected to the corresponding

The chick is the synchronous input of the device.

The drawing shows the structure of the device for controlling the matrix 20 indicator.

The device contains 1 clock pulse generator, counter 2, first decoder 3, device information input 4, digital-analog conversion Device contains 1 clock pulse generator, counter 2, first decoder 3, device information input 4, digital-analog converters

the outputs of the decoder, and the outputs - with co-25 5 and 6, matrix indicator 7

the corresponding inputs of the matrix indicator, with the second group of inputs of the decoder being the input of the device.

The prior art device has an improved image quality due to the increased contrast. However, the image quality is limited by highlighting a constant number of elements of the symbol selected as the maximum, but with a minimum number of elements in the order, time is also allocated to the empty elements, which leads to a decrease in the overall brightness of the character image.

Before starting a command from input 11 into the memory cells of the block, from input 12, the codes of the elements of input 4 character are written in accordance with the addresses of counter 2. The installation code, for example, P ... 1, recorded by the decoder, is written into the last memory cell. to reset counter 2 (

The aim of the invention is to increase the image brightness by means of outputting 40 and returning the device to the repetition mode of the optimal number of symbolic repetition. By character window.

In the device containing the clock pulse generator, the output of which is connected to the clock input of the counter, the first decoder, the outputs of the first group of which are connected to the inputs of digital-to-analog converters, the outputs

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By recording the change in the polarity of the signal at input 11, the operation of generator 1 is permitted and the initial state of counter 2 is confirmed with the permission of further counting from generator 1.

By the pulses of the generator 1, the indicator 7 alternately highlights the elements of the symbol from the memory of the block 8. After the last element of the symbol is highlighted with the code of the block 8 through the decoder 9, the counter 2 is set to O, and the process of alternately flashing the element

which are connected to horizontal buses of the matrix indicator, the vertical buses of which are connected to the outputs of digital-to-analog converters of the second group, whose inputs are connected to the outputs of the second group of the first

The generator 1 pulses with the indicator 7 alternately highlighting the elements of the symbol from the memory of block 8. After the last element of the symbol is highlighted with the code of block 8 through the decoder 9, the counter 2 is set to O, and the alternator flashing process, the memory block is stuck, and the second symbol repeats is repeated the decoder and the delay element, you-but before the change of information in block 8, the cokhod of which is connected to the synchronization command on input 11. In this case, the delay

the data input of the memory unit, the information element 10 provides reception code

the input of which is the information input of the device, the address gap is connected to the output of the counter, and the output

the memory unit is connected to the information inputs of the first and second decoders, the output of the second decoder is connected to the installation input of the counter, the input of the permission of which account

connected to the memory-read control input of the memory unit and to the control input of the clock generator; it is the control input of the device, the input of the delay element is connected to the clock input of the counter and is the synchronous input of the device.

The drawing shows the structure of a device for controlling a matrix indicator.

The device contains 1 clock pulse generator, counter 2, first decoder 3, device information input 4, digital-to-analog conversions

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a memory block 8, a second decoder 9 a delay element 10, a control input 11, and a synchronous input 12 of the device with the indicated circuit connections o

The device for controlling the matrix indicator operates as follows.

Before starting a command from input 11 into the memory cells of the block, from input 12, the codes of the elements of input 4 character are written in accordance with the addresses of counter 2. The installation code, for example, P ... 1, recorded by the decoder, is written into the last memory cell. to reset counter 2 (

,, t,., „, ... 0 and the device returns to the multiple repetition mode of the symbol. By the window

,, t,., „, ... and return the device to the multiple repetition mode of the symbol. By the window

By recording the change in the polarity of the signal at input 11, the generator 1 is enabled and the initial state of the counter 2 is confirmed with the resolution of further counting from generator 1.

The generator 1 pulses with the indicator 7 alternately highlighting the elements of the symbol from the memory of block 8. After the last element of the symbol is highlighted with the code of block 8 through the decoder 9, the counter 2 is set to O, and the alternate flashing of the elements of the symbol repeats the multiple address from the counter 2 after the transients in the last .

Performing the device in this way and the specified algorithm of its operation simplifies the process of converting information by decoder 3 by eliminating the connection of its input with counter 2. This improves the quality of the displayed information and increases the image brightness by indicating the optimal number of elements in each symbol, eliminating empty elements for the simplest symbol, necessary to highlight the symbol with the maximum number of elements (segments).

Claims (1)

Invention Formula A speaker whose vertical buses are connected to the outputs of digital-to-analog converters of the second group, the inputs of which are connected to the outputs of the second group of the first decoder, characterized in that, in order to increase the image brightness by highlighting the optimal number of symbol segments, a memory block and a second decoder are inserted into it , the delay element, the output of which is connected to the synchronizing input of the memory unit, whose information input is the information input of the device, the address input is connected to the output at the counter, and the output of the memory unit is connected to the information inputs of the first and second decoders, the output of the second decoder is connected to the installation input of the counter, the counting permission input of which is connected to the memory control input-read input of the memory unit and the control input indicator containing a clock pulse generator, the output of which is connected to the clock input of the counter, the first decoder, the outputs of the first dead-25 clock pulse generator and which are connected to the inputs of the digital control input of the device, the input of the analog converters of the first delay element is connected to the synchronization group, the outputs of which are connected to the metering input of the counter and are horizontal tires Dot matrix clock input device. , 0 0 A speaker whose vertical buses are connected to the outputs of digital-to-analog converters of the second group, the inputs of which are connected to the outputs of the second group of the first decoder, characterized in that, in order to increase the image brightness by highlighting the optimal number of symbol segments, a memory block and a second decoder are inserted into it , the delay element, the output of which is connected to the synchronizing input of the memory unit, whose information input is the information input of the device, the address input is connected to the output the counter, and the output of the memory unit are connected to the information inputs of the first and second decoders, the output of the second decoder is connected to the installation input of the counter, the counting permission input of which is connected to the memory input of the read / write memory unit and to the control input of the clock pulse and is the control input of the device, the input of the delay element is connected to the synchronizing input of the counter and is the synchronous input of the device.