SU1267472A1 - Device for displaying information - Google Patents

Abstract

The invention relates to automation and computer technology, in particular, to systems for displaying graphic information on gas discharge display panels. The purpose of the invention is to increase the reliability of the mold. image by leveling the excitation conditions of all the cells when changing the duration of their connection depending on the number of cells. This goal is achieved by introducing into the device the third counter, the elements AND, the frequency divider and the elements 2И-ШШ (Л and ШШ-НЕ. The connection time of the fragment in this device is determined by the pulse period from the output of the controlled frequency divider, which by code the third counter implements the required division to ratio, producing pulses with a higher frequency at Od with a greater number of cells in the fragment and with a lower frequency with a smaller number of 4ib cells. 1 ill. sj th

Description

one

The invention relates to automation and computer technology, in particular, to systems for displaying graphic information on gas discharge display panels.

The purpose of the invention is to increase the reliability of image formation by equalizing the excitation conditions of all cells when changing the duration of their connection depending on the number of cells.

The drawing shows the functional diagram of the device.

The device contains a gas-discharge indicator panel 1 connected via a depressor 2 to the first counter 3 connected to comparison unit 4, memory block 5, second counter 6, first and second registers 7 and 8, clock generator 9 connected to a controlled divider 10 frequencies and element 2И-OR 1 1 ,, third counter 12, element OR-HE13 trigger 14, first 15 and second 16 elements I.

The device works as follows.

In the initial state, in the memory block 5 binary binary codes are stored. nat graphics. The first counter 3 is set to the i-e state, the second counter 6 is set to the last state. Trigger 14 is reset (at the direct output logic zero). The outputs of memory block 5 and block 4 are gated with a logic zero signal from the direct output of trigger 14. In the third counter 12, the code of the number of cells displayed in the i-1-th fragment is written. By this code, the control frequency divider 10 generates the switching pulses of the second counter. In panel 1, hot cells located at the intersection of the i-1th row with columns excited by the output signals of the first register 7.

The decoder 2 is connected to the horizontal tires of the panel 1 in such a way that when the signal at its i-M output is active, the i-1 horizontal bus of panel 1 is excited. With the active signal at the first output of the deflector 2, the panel bus is excited.

When the next pulse arrives at the second counter 6, it is installed in the zero state. pulse output from the counter 6

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trigger 14 is set to one. By cutting the pulse from the inverse output of the trigger 14, the third state is set to zero.

5, the counter 12, and the potential of the logical zero from the same output, inhibits the controlled divider 10 and prevents the passage of pulses from the code of the controlled divider through

10 element 2I-OR 11. The potential of the logical unit from the direct output of the trigger 14 permits operation of the memory block 5, block 4 and the passage of pulses from the generator 9 through the element 2I-OR 11 to the second counter 6. The output of the memory block 5 is output first cell code. If this code is equal to the code from the output of the first counter 3, then the level of the logical unit is expressed at the output of block 4. When it coincides at the input of the first element AND 13 with a pulse from the output of element 2И-OR the state of the third counter 12 changes to

25 units of lower rank. By a pulse slice from the output of element 2I-OR, the logical unit from block 4 is recorded in the second register 8. The information stored in register 8 is shifted to the right by one cell. If the output code of memory block 5 does not coincide with the code of the first counter 3, then the output signal of block 4 is zero. In this state of the third

JJ counter 12 does not change, and a logical zero is written to the first cell of the second .reg 8.

When forming each next pulse at the generator output

0 9 clock frequency, and therefore, at the output of element 2I-OR 11, the operation of the device is repeated until the state of the second counter 6 reaches the maximum value, and the signal determined by the second register 8 is not recorded in the last cell of the second register 8. the code stored in memory block 5. address corresponding to the maximum output code a

50 of the second counter 6. With the arrival of the next pulse, the second counter 6 is set to the zero state, and a signal is generated from its output at the output of the second element I 16 and a pulse is generated that overwrites the information from the second register 8 to the first register 7 and switches the first counter 3 in

next state. The signals from the decoder 2 of the first register 7 on panel 1 display a fragment of the graph corresponding to the i-th bus.

The trigger 1A is set to the zero state, the signal from its inverse output resolves the operation of the I-controlled divider 10 and the passage of pulses from its output through the element 2I-OR 11. The output from the trigger output of the memory block 5 and the block 4 The control inputs: the divider 10 from the third counter 12 receives a code corresponding to the number of cells displayed in this fraction. The controllable divider 10 is constructed in such a way that with a large number of displayed cells at its output a higher frequency is output at a low to a lower frequency. Thus, by increasing the duration of the connection, the likelihood of the fragment cells being ignited increases. After the second counter reaches its maximum value, the second and subsequent segments of the graph are displayed in the same way.

In the case when, at the time of filling in the second register 8, block 4 does not issue any logical units, the third counter 12 remains in the zero state. The code of this state at the output of the OR-NOT 1 element causes the signal of the logical unit by which the trigger 14 is held by the setting input in the one state upon arrival of the switching pulse from the second counter 6. At the same time, the second element 16 transmits an information recording pulse to the first register 7 and the first counter 3 is switched. Logical zeros are written to the first register 7 and the information on the panel is not reproduced. Since the trigger 14 remains in the single state, the operation of the memory block 5 and the block 4 is enabled, the following code word is written to the register 8 with the frequency of the generator 9. If, after the end of the cycle of operation of the second counter 6, the state of the third counter 12 is different from zero, i.e. at least one cell should be displayed, trigger 14 switches to the zero state, and the cells of the next horizontal bus are displayed. If

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the state of the third counter 12 is zero, the first counter is switched, and the content of the next segment of the graph is analyzed.

Thus, the connection time of a horizontal bus consists of two intervals: constant, determined by the formation time

.Q is the control word for the vertical tires with a generator frequency of 9, and an alternating frequency determined by the frequency from the output of the controlled divider 10, depending on the number of cells reproduced in the fragment.

The connection time of the fragment in the proposed device is determined by the pulse following period from the output of the controlled divider 10 hours, which, using the code from the third counter 12, realizes the necessary division factor, producing pulses with a higher frequency at the output with a larger number of cells

25 fragments and with a lower frequency with a smaller number of cells.

The maximum connection time of a fragment is limited by the critical flicker frequency, provided that all the fragments are displayed one by one.

Thus, the proposed device provides an increase in the probability of displaying fragments of a graph with a small number of cells, which leads to the elimination of their blinks and improves the conditions for perception of information by the operator.

Claims (1)

Invention Formula A device for displaying information, comprising serially connected first and second registers, serially connected first counter and decoder, the outputs of which are connected to horizontal buses of a gas discharge display panel, vertical tires of which connected to the outputs in an inexpensive register, a memory unit whose output is connected to the first input of the comparison unit, the second input of which is connected to the output of the first counter, a trigger, a clock pulse generator and a second counter, the output of which is connected to the first input of the memory unit, differing in that, in order to increase the reliability of the device, into it BBBfleifbi the third counter, the first and second elements AND, the frequency divider, element 2I-OR and the element OR NOT, whose inputs are connected to the first outputs of the third counter and frequency divider, and the output to the installation input of the trigger, the direct output of which is connected to the first input of the first And element, the third input of the comparison unit and the second input of the memory unit, the second input first The element And the synchronization input of the trigger is connected to the second output of the second counter; the output of the first element I is connected to the input of the first counter and the control input of the second register, the output of the comparator unit is connected to the information input of the first register 726 and the first input of the second element I, the output of the clock generator is connected to the second input of the frequency divider, the clock generator outputs and the frequency divider is connected to the first and second inputs of element 2И-OR, the output of which is connected to the second input of the second And element, the input of the second counter and the control input of the first register, the inverse output the trigger is connected to the third inputs of element 2I-OR, the frequency divider and the second input of the third counter whose third input is connected to the output of the second element AND, the fourth input of element 2I — OR is connected to the direct output of the trigger.