RU1829045C - Device for input and output of object pictures - Google Patents

Abstract

The invention relates to automation, in particular to a device for inputting and outputting images of objects from memory. An object of the invention is to expand the functionality of a device. This goal is achieved by implementing the functions of selecting the desired image recording format, which is provided by the introduction of a unit for generating memory access signals, a multiplexer, and a switch. 1 s.p. 5, ill.

Description

The invention relates to the field of automation, in particular to a device for inputting and outputting images.

An object of the invention is to expand the functionality of a device.

In FIG. 1 shows a block diagram of a device; in FIG. 2-5 are examples of a particular embodiment of the multiplexer, the signal generation block, and the memory address block and the output block, respectively.

The device comprises a television sensor 1, an analog-to-digital converter (ADC) 2, a multiplexer 3, a memory access signal generation unit 4, an address generation unit 5, a first 6 and a second 7 group of memory units, an output unit 8, and a display unit 9 (ICU) .

The multiplexer (see Fig. 2) contains the element 10 NOT, the first 11 and second 12 switches.

The memory access signal generation unit (Fig. 3) comprises registers 13, a memory unit 14, and a memory unit 15 made in the form of ROMs.

The address generating unit (see Fig. 4) comprises a group of AND elements 16, a counter 17 and a counter 18.

The output unit (see Fig. 5) contains a switch 19 and a digital-to-analog converter 20.

The device operates as follows.

The video signal from the television sensor 1 is fed to the ADC 2, where it is converted to digital form. The television sensor 1 also generates clock signals: SSI, CSI and sampling pulses along the line. The clock signals are fed to the clock inputs of blocks 2, 5, 8 to synchronize the operation of the device. Sampling pulses have a different frequency, depending on the format of the television sensor.

with

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about sl

correspondence with the number of elements in the line of the photodetector (CCD - matrix).

From the output of the ADC-2 digital signal through the multiplexer 3 is fed to the input of these blocks. When a control signal is supplied to the control input of block 3, the data from blocks 6 receives signals from an external device. Due to this, access to the RAM image from the computer by recording is provided. The image read from blocks 6 goes to the output data bus, as well as to block 8. Depending on the external control signal received at block 8, the switch 19 transmits to the DAC20 a digital signal read either from the L blocks or the digital signal of the original image directly from the ADC 2. DAC 20 converts the digital signal into analog form and generates a full TV signal supplied to the VKU 9. Address signals from block 5 are sent to the address inputs of blocks 6 and 7. When accessing blocks b and 7 in the television standard b ca. 5 generates the address signals (row address and a column address for the RAM-matrix) using the clock signal received at its clock terminal. At the same time, the counter 17 columns counts the sampling pulses along the line and is reset to the initial zero state by horizontal sync pulses (SSI), and the counter 18 lines calculates the SSI and is reset by frame sync pulses. Thus, the appeal is organized according to the matrix principle: the address of the line and the address of the column uniquely determines the cell of the RAM matrix.

When accessing the RAM from the computer side, a signal is issued to the control input of the address block 5, which prohibits the passage of clock signals through the And 16 elements to the counting inputs and reset inputs of the counters 17 and 18.

The address of the column and the address of the line are entered into the counter from the input data bus when issuing the installation inputs of the counters of the installation signals via the control bus. The row address and column address are entered into the counters in turn. Thus, from the side of the external device, random access to any memory cell of the matrix of blocks 6 and 7 is provided.

The high-order bits of the counters 17 and 18 are connected to the address input of block 4. The number of high-order bits connected to block 4 depends on the memory capacity of the RAM module and the number of RAM modules in blocks 6 and 7.

Block 4 provides the choice of one of the RAM modules of blocks 6 and 7, depending on

the set number of the RAM array into which it is supposed to enter images when the recording format and address code coming from block 5. Array number

The binary RAM and the recording format code are recorded in the first and second registers of block 13. Recording is done sequentially by setting the code on the data bus of block 4 and issuing a recording signal to the recording input of block 4.

The codes entered in the first and second registers of block 13, as well as the address signals of block 5 (high-order bits of line and column counters) are address signals for ROM 14. The signals read from ROM 14 control the sequence of module selection in blocks 6 and 7 ,

In a similar manner, a recording signal is generated for blocks 6

0 The number of the RAM array into which it is supposed to write, as well as the required recording format, are entered into registers C and 4 of block 13 from an external device. The output signals of the registers, as well as address

5, the signals of block 5 are the address signals for ROM 15.

Image input and output can be implemented in the television standard, i also by random access to the memory from the side of the computer. Moreover, the RAM cells are addressed in a convenient matrix form (row address, column address).

Claims (2)

The claims 51. Device for input and output images zhenie objects containing an analog-to-digital converter, the information input of which is connected to the first outputs of the television sensor, and synchronize The 0 input is connected to the second output of the television sensor, the first and second group of memory blocks, the address inputs of which are connected to the output of the address generation block, the information input / 5 of which is the information input of the device, the control input is with the first control input. devices, and a synchronizing input under the keys to the second output of the television 0 sensor, characterized in that, in order to expand the functional capabilities of the device by implementing 1 function to select the desired image recording format, it contains a block 5 of the memory access signals, the switch and the multiplexer, the first information input of which is connected to the information input of the device, the second information input is connected to the output of the analog-to-digital converter, the control input is connected to the first control input of the device, and the output is connected to the information inputs of the blocks the memory of the first group, the outputs of which are the first information output of the device, the information input of the memory access signal generation unit is connected to the information input ohms of the device, the first control input is the second control input of the device, the second control input is the third control input of the device, the address input is connected to the output of the address forming unit, and the first output is connected to the first control inputs of the blocks the memory of the first and second groups, the information inputs of the switch are connected to the outputs of the memory blocks of the first group and the analog-to-digital converter, the control input is connected to the first control input of the device, and the output is connected to the information input a digital-to-analog converter, the clock input of which is connected to the second output of the television sensor, and the output is the second information output of the device, while the second control inputs of the memory units of the first group are connected to the second output of the memory access signal generation unit, the second and the third control inputs of the memory units of the second group are the fourth and fifth control inputs of the device, and the outputs are the third information output of the device. 2. The device pop. 1, characterized in that the memory access signal generation unit comprises registers, the information inputs of which are the information input of the unit, the synchronization inputs are the first control input of the unit, and the outputs are connected to one address inputs of the corresponding memory nodes, others the address inputs of which are the address input of the block, the output of one memory node being the first output of the block, the output of the other node being the second output of the block, and its control input being the second control input of the block . Sinhr Shch ulr  eleven Sh-5I w yk b Control input From $ L2 AWfalJ sh .g) Vyzh 77 H) 72 FIG. I From 5L 5 (8x. Oresn.) Hnp.Bx. Fig.Z U I Uravl. From RAM 6 I nineteen From ADC 2 Fig. B East fa. FIG. 4 Ршр. twenty to BW3