SU1720168A1 - Tv recorder - Google Patents

Abstract

The invention relates to the registration of television images and is intended to document black and white halftone images on the target medium. The invention can find applications in information recording devices displayed on a television screen, in information television systems, medical diagnostics systems, playback systems and recording information from video disks. The purpose of the invention is to register a halftone television image. The television image is recorded in recording unit 1, the information input 2 of which receives an analog video signal from each element of the vertical decomposition column, and the input 3 of the control - a signal of moving the carrier. With the help of the first counter 4 on the Start signal from the input 5 of the control, the first generator 6, the second counter 7, the comparator oo a 00 36 37

Description

8, the pulse shaper 9, together with the first And 12 element, receiving information from the input 13 for the horizontal sync pulses, form the code of the column number of the record and the code of the element in the column. With the help of block 16 of sampling and storage, which receives video information from input 17, video information of the image element is extracted for the video signal, which

It is digitized in the analog-digital converter 18 and stored in the operational storage unit 20. The multiplexer 25, the permanent storage unit 26, the digital-analog converter 27, the modulator 28, the amplifier unit 11 provide a bit-wise recording of information on the terminal medium. 1 il.

The invention relates to the field of recording television images and is intended to document black and white halftone images at the end. media and can be used in devices for recording information displayed on a television screen, in information television systems, medical diagnostics systems, playback systems and recording information from video disks.

The purpose of the invention is to register a halftone television image.

The drawing shows a structural electrical circuit of a device for recording a television image.

The device for recording a television contains control unit 1, the first, second and nth informational input 2.1, 1.2, 2n and control input 3 of control unit 1, the first counter A, control input 5 of the device for recording a television image, the first generator 6, second counter 7, comparator 8, pulse generator 9, register 10, block 11 N amplifiers, first element 12, input 13 for line pulses of a device for recording a television image, second element 14, input 15 for frame sync pulses of the device registering a television image, block 16 for sampling and storage, input 17 for a video signal of a device for recording a television image, analog-to-digital converter (ADC) 18, third counter 19, real-time storage unit (036) 20, first trigger 21, first single vibrator 22, second , odiovibrator 23, fourth counter 24, multiplexer 25, persistent storage unit 26, digital-to-analog converter (D / A converter) 27, modulator 28, third one-oscillator 29.

the first element OR 30, the second trigger 31, the second generator 32, the fourth one-shot 33, the second element OR 34 and the third trigger 35. The control unit 1 contains lines of writing elements 36, the end carrier 37, the end carrier drive 38.

A television image recording device operates as follows

in a way.

In the mode of registration of semi-tone television images, the input 17 for the video signal of the device is connected to the video output of the TV or the display (not

shown). The input 13 for horizontal sync pulses of the device is connected to the output of the horizontal sync pulses of the TV, the input 15 for frame sync pulses of the device is connected to the output of the sync pulses of the TV. On the TV screen

form an image of the displayed information using a progressive scan television raster. The number of display elements (EO) in the horizontal line of the image is N, the number of display elements in the vertical column of p. For definiteness, we take N p 512. Each 30 can be modulated in brightness and have N gradations of brightness. Image regeneration on the screen. The camera with frame scanning period Tc is carried out by a transmitting device (in the case of using a television receiver) or by a display processor included in the television display. During registration, the image on the screen should not change.

The registration cycle of the image on the target medium is as follows.

A start pulse arrives at the control input 5 of the device, which sets the first counter 4 to zero.

and sets a high level B at the output of the transfer of the first counter 4 and the output Q of the third trigger 35. The frame clock from input 15 through the second element 14 enters the counting input of the first counter 4, sets the third counter 19 to zero, the fourth counter 24, first trigger 21.

The first counter 4 performs a counting of frame sync pulses modulo Nr, equal to the number of display elements in the image row on the TV screen, and forms the code number of the recording column.

A low level inverted low level sync pulse (H) arrives at the input 13 for horizontal sync pulses of the device, and a falling level is established on the falling front of the cotiro O at the output of the first element I 12. In this case, the second counter 7 is reset to the zero state, and the first generator 6 generates in each horizontal scanning period a sequence of clock pulses, the number of which is equal to N display elements in the image line. The first clock pulse of the sequence is associated in time with the position of the first display element in the image row. The second counter 7 performs the counting of clock pulses in each row. The code of the clock pulse number from the output of the counter 7 is fed to the input of the comparator 8. The second input of the comparator 8 receives the parallel code of the column number of the record from the output of the counter 4. With the equal codes on the outputs of the comparator 8, a pulse appears. The impulse from the direct output enters the clocking input of the sampling and storage unit 16, in which the instantaneous value of the video signal from the input 17 is stored. The impulse from the direct output / .a of the comparator 8 is fed to the first input of the pulse shaper 9 and starts it. The third counter 19 is reset to the zero state by the sync pulse from the output of the second element 14, counts the pulses of the former 9 and generates address codes on the address inputs of the AHD corresponding to the pulse number at the output of the comparator 8 and, therefore, the number of the display element in the vertical column of the image. The low level at the output of the first trigger 21 allows writing to the RAM. The pulse from the inverter output of the driver 9 arrives at the first control input d 0315 20 and records data at the specified address. During the time of one frame with the number NK

the numerical values of all elements of the vertical column of the image with the Nc NK number will be recorded in the OZB. After writing NB values, the output of the transfer of the third 5 counter 19 generates a pulse, which transfers the first trigger 21 to the state B. OZB 20 to the read mode, resets the third trigger 35 to the H state, resets the second trigger 31 to the H state and starts

0 the first one-shot 22. In this case, the input of the first element 12 and the second element 14 from the first output of the third flip-flop 35 receives a low level, which closes the inputs for frame and line sync pulse of the device.

The first one-shot 22 forms a pulse at the control input of the register 10 and connects the outputs of the register and the information input of the amplifiers 11.1, 11.2,

0 11.12 electrical signals. The first control pulse does not cause a column to be printed, since the pulse from the output of element 14 has zeroed the register 10. The signal from the inverse output of the first one-vibrator 22 starts the second one-shot 23.

The second one-shot 23 produces a pulse arriving at the counting input of the fourth counter 24, which performs a modulo count equal to the number of bits

0 of the digital code at the outputs of the OZB 20. The code from the outputs of the fourth counter 24 is fed to the control input of the multiplexer 25, which connects the corresponding section of the data output of the OZB 20 to the information input of the register 10. The same code of the counter 24 is fed to the input constant of this memory of the PZB 26, at the output of which a modulation weight code is generated, corresponding to

0 selected data bit. D / A converter 27 converts the weighting factor code to analog form and controls the modulator 28. The output signal of the modulator 28 is fed to the power supply bus of the output amplifiers 11.1,

5 11.2, 11 .p electrical signals. The pulse from the inverse output of the second one-vibrator 23 at a low level at the output of the third trigger 35 starts the third one-shot 30, which generates a reset pulse of the register of the register 10 and sets the second trigger state 31 to the state B. The second generator 32 forms a sequence of pulses arriving at the second input of the pulse generator 9, the direct output of the shaper 9, the pulses arrive at the third counter 19, which forms the data readout addresses from the AHD 20. At the output of the trigger 21, a high level is maintained, allowing read s. The pulses from the inverter output of the imaging unit 9 are fed to the first control input of the OZB 20 and clocks the reading of data that through the multiplexer 25 enters the information input of the register 10. The fourth single vibrator 33 is triggered by the pulses of the second generator 32 and generates the clock input pulses with the necessary delay register 10. As a result, the low-order bit of the data of AZB 20 is rewritten for the periods of the second generator 32 into the register 10. The next transfer pulse of the third counter 19 resets the second trigger 31, There is a first one-shot 22, the pulse of which is fed to the control input of the register 10 and connects the outputs of the register to the information inputs of amplifiers 11.1, 11.2, 11.p of electrical signals. From the outputs of the amplifiers, signals modulated (for example, by voltage) by the modulator 28 are fed to information input 2 of the registration unit 1 and using the ruler 36 of writing elements, recording the lower bits of the samples of the display elements of the vertical column of the image on the destination medium 37. The same pulse from the inverse output of the first one-shot 22 triggers the second one-shot 23, the pulse of which increases the code at the output of the fourth counter 24 and starts the third one-shot 29. At the same time, to the information input Registrar 10 multiplexer 25 connects the second bit of data bus OZB 20, at the output of FBG 26 a weighting code of the second bit is generated, the DAC 27 and the modulator 28 generate a second control signal on the power supply bus of amplifier 11. The second trigger 31 is set to In and includes the second generator 32. A cycle of rewriting of the second bits of the codes from the OZB 20 into the register 10 occurs and they are recorded on the final carrier 37 with an increased supply voltage of the amplifiers 11.1, 11.2.11.p. The number of rewriting cycles and the registration of code bits R Avno bus width data OZB. After registering the higher bit codes for the transfer pulse of the fourth counter 24 through the second element OR 34, the third trigger 35 switches to the state B, the first and second elements And 12 and 14 open for horizontal and frame sync pulses, the third single-oscillator 9 closes for the input pulses. The next frame clock pulse arrives at the input 3 of the control of the registration unit 1, the stepper motor of the drive 38 moves the terminal carrier 37 by one step. Frame sync from the output of the second element And 14

sets to zero position the third counter 19, the register 10, the fourth counter 24, the first trigger 21. At the output of the first counter 4, the code of the next

the column and the recording of the numeric codes of the display elements of the new column and its bit size is recorded on the carrier in the OZB 20, and the first transfer pulse of the third counter 19 does not result in printing

the image of the column, as the register 10 was reset by the frame sync pulse from the output of the second element And 14.

After registering the last 512 vertical column of the image, the pulse

transferring the first low level counter4 closes the first element 12 and the second element 14 and the device goes into standby mode until the next start signal.

The duration of the pulses of the first single-vibrator is 22 n 1 ms and the time of rewriting one bit of data from RAM 20 to register 10 is not more than 200 μs. The recording time of a video signal in RAM is equal to the period of personnel pulses Tk of 20 ms. Thus, the total time of entry and registration of one image column

Ti Tk + (TI + 200 μs) 1.2x,

where Np is the number of bits of the RAM data code. If Np 4, then Ti is 25 ms.

Considering that. that, after printing all the bits, the device is waiting until the next frame sync pulse arrives, the total recording time of the image frame during progressive scan

Tzap 2Tk -Mr.

For the number of elements in the string Mg 512T3ap 20.5 s.

The device can be widely used in information television systems, systems for reproducing and recording information from video disks, in computer science for obtaining hard copies.

Claims (1)

halftone images from display screens, in medical diagnostic systems. Claims An apparatus for detecting a television image comprising the counter, the setup input of which is the control input of the device for recording the television image, the second counter, the counting input of which is connected to the output of the first generator, the comparator, the first input of which is connected to the output of the first counter, and the second input - to the output of the second counter, pulse generator , the first input of which is connected to the forward output of the comparator, a block of N amplifiers, where N is the number of display elements in the image column, the corresponding inputs of which are connected to the same outputs of the reg The country and the corresponding outputs have the same informational inputs of the registration unit, characterized in that, in order to register the halftone television image, the first AND element is inputted, the first input of which is an input for the horizontal sync pulses of the television image recording device, the second input is connected the transfer output of the first counter, and the output connected to the control input of the first generator and the installation input of the second counter, the second And element, the first input of which is the input for frame, sync pulses of the device for recording a television image, the second input is connected to the second input of the first And element, and the output is connected to the counting input of the first counter and to the control input of the recording unit, the sampling and storage unit, the information input of which is an input for the video signal of the device registration of the television image, and the clock input is connected to the direct input of the comparator, an analog-to-digital converter, whose information input is connected to the output of the sampling and faceting unit, and the input clocking - to the inverse output of the comparator, the third counter, the counting input of which is connected to the forward output of the pulse shaper, and the setup input - to the output of the second element I, the operational storage unit, the data input of which is connected to the output of the analog-digital converter, the address input - to the output of the third counter, and the first control input - to the inverted output of the pulse former, the first trigger, the setup input of which is connected to the counting input of the first counter, the reset input connected to the transfer output t of the counter, and the output is connected to the second input. control of the operational storage unit, the first one-shot, the input of which is connected to the transfer output of the third counter, and the direct output is connected a second monoblock, whose input is connected to the inverse output of the first one-vibrator; a fourth counter, whose counting input 5 is connected to the direct output of the second single vibrator; a setup input is connected to the output of the second And element, a multiplexer whose information input connected to an information outlet 0 of the operational storage unit, the control input is connected to the output of the bits of the fourth counter, and the output is connected to the information input of the register, the permanent storage unit, the information5 input of which is connected to the output of the bits of the fourth counter, digital-analog converter, the input of which is connected to output of a permanent storage unit, a modulator, the input of which is connected to the output of the digital-analog converter, and the output is connected to the power bus of the first, second, n-th amplifiers, the third one-oscillator, the first whose second input is connected to the inverse output 5 of the second one-shot, the first OR element, the first input of which is connected to the output of the third one-shot, the second input is connected to the output of the second element AND, and the output is connected to the setup input of the registry, the second trigger, the installation input of which is connected to the output of the third one. and the reset input is connected to the transfer output of the third counter, the second generator, the control input of which is co5 connected with the output of the second trigger, and the output connected to the second input of the pulse shaper, the fourth one-shot. the input of which is connected to the output of the second generator, and the inverse output is connected to the register clock input, the second OR element, the first input of which is connected to the installation input of the first counter, the second input is connected to the transfer output of the fourth counter, the third trigger, the installation input of which is connected to the output of the second element OR, the reset input is connected to the transfer output of the third counter, the output is connected to the third inputs of the first and second elements And the second input 0 third one-shot.