SU1483674A1 - Device for controlling vertical buses of tv matrix screen - Google Patents

Abstract

The invention relates to a television technique. The purpose of the invention is to simplify the device by reducing the number of elements and inter-element compounds. The device contains ADC 1, shift registers 2, K -discharge buffer register 3, synchronization unit 5. To achieve the goal, K / Q - logical switches 4 are entered into each of the N -1 first lines of shift registers 2 (K is the number of columns television matrix screen, Q - the number of bits of shift registers). Since the information being pushed onto the outputs of the device is stored on the outputs for a time proportional to the weight of the corresponding bit in the source digital codes, the device performs digital-analog conversion of binary codes in the duration of the pulse bursts on the outputs of the device. 2 Il.

Description

The invention relates to the technique of television and can be used in devices for displaying television information with LED matrix screens.

The purpose of the invention is to simplify the device. by reducing the number of elements and interelement compounds. '

Figure 1 shows a structural electrical diagram of a vertical bus control device for a television matrix screen; figure 2 diagrams explaining the operation of the device.

The vertical bus control device of the television matrix screen comprises an analog-to-digital converter 1, shift registers 2Q 2, a K-bit buffer register 3, logical switches 4 and a synchronization unit 5.

The device operates as follows. 25

The television signal (Fig. 2a) is converted by means of an analog-to-digital converter 1 into an N-digit digital code.

During the active part of line 30 of the television signal, K binary Q-bit numbers corresponding to the instantaneous values of the television signal at the time of exposure to clock pulses coming in 35 s are allocated to it. the first output of block 5 sync.

In this case, under the influence of a positive pulse generated at the third output of synchronization block 5 (Fig. 26), the logical switches 4 are set to a mode in which in all horizontal lines the shift registers 2 are switched on in series. Under the influence of clock pulses, the information generated at the outputs of the analog-to-digital converter 1 begins to fill the shift registers 2, moving along their horizontal ‘rulers. By the end of the active part of the line of the television signal, the shift registers 2 are fully loaded with information. Next, the signal fed to the control input $$ logical switches 4, takes a value of logical zero. Moreover, in the first (Ν-1) horizontal lines, the logical switches 4 go into a state in which the signals from their second input go to the output and the structure of the shift registers 2 connected in series from one another changes from vertical to vertical. After that, a positive write enable pulse (Fig. 2d) is received at the write enable input of the buffer register 3 and the least significant bit of all samples of the signal of one television line recorded in the shift registers is set to the outputs of the device. Immediately after that, Q clock pulses arrive at the inputs of the shift registers 2 from the synchronization unit 5 (Fig. 2c). In this case, the information recorded in the second horizontal ruler of the shift registers 2 according to the scheme (Fig. 1) is copied to the first horizontal ruler, the information recorded in the third horizontal ruler is copied to the second, etc. With the arrival of the second write enable pulse in the buffer register (Fig. 2d), information on the second bit of all K binary samples of the television signal is written to the device outputs. The time for which the information on the second bit of binary samples is set to exit is twice the time spent on the output of the previous information. During this time, the next Q pulses (Fig. 2c) are received at the inputs of the shift registers 2 and, with the arrival of the third recording resolution pulse (Fig. 2d), information about the third category of samples of the television signal is set to output, but already for a time twice as long as the storage time by output of the previous discharge, etc. When displaying every second line of the television signal, the last bit of recorded information is in buffer register 3 and is set to the device outputs for the duration of one television line. During this time, the next line of the television signal, etc., is recorded in the shift registers 2.

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Since the information put forward at the outputs of the device is bitwise stored at the outputs for a time proportional to the weight of the corresponding discharge in the source digital codes, the device performs digital-to-analog conversion of binary codes into the duration of the bursts of pulses at the outputs of the device.

Claims (1)

Claim A device for controlling the vertical buses of a television matrix screen containing N rulers, each of which consists of K / Q shift registers, where N is the number of bits of the analog-to-digital converter, the input of which is the input of the television signal, and the Nth output is connected to the information input of the first shift register of the N-th line, K is the number of columns of the television matrix screen, Q is the number of bits of the shift registers, the synchronization block, the input of which is the input of the television clock signal, and the first output is connected it is connected to the control inputs of the analog-to-digital converter and shift registers, the K-bit buffer register, the information inputs of which are connected to the corresponding outputs of the shift registers of the first line of shift registers, the second output of the synchronization unit is connected to the control input of the K-bit buffer register, the outputs of which are the outputs of the control signals of the vertical buses of the television matrix screen, and the shift registers of the Nth line of shift registers are connected in series, exc which, in order to simplify the device by reducing the number of elements and interconnections, K / Q logical switches are introduced into each of the N-1 first lines of shift registers, while the output of the ί-th logical switch is connected to the i-ro information input the shift register, the first information input of the ΐ-th logical switch is connected to the output of the last bit (il) -ro of the shift register, and the second information input j-ro of the logical switch of the j-th line of shift registers is connected to the output of the last of the discharge of the i-ro shift register (j + D-th line of shift registers, the first information input of the first logical switch of the j-th line of shift registers is connected by the j-th output of the analog-to-digital converter, where 1 <i <K / Q, 1 ij ί έ (Ν-1), and the control inputs of the logical switches are combined and connected to the third output of the synchronization block.