SU1734210A2 - Adjustable fractional ratio divider for dividing pulse repetition rate - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation devices and computer technology. The purpose of the invention is to improve the division accuracy by reducing the side components in the output signal spectrum - by introducing a pulse counter 16 and an OR 17 element into the device and forming new functional connections. In addition, the device contains a reference frequency generator 1, counters 2, 4, 6, and 8 pulses, a code comparison element 3, registers 7, 13 of memory, an inverter 9. an element OR 10, a delay element 11. 2 Il.

Description

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The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to improve the accuracy of the division by reducing the side components in the output signal spectrum.

FIG. 1 shows the electrical functional scheme of the device; in fig. 2 - timing diagrams for the operation of the device.

The device contains a reference frequency generator 1, the output of which is connected to the counting input of the first counter 2 pulses, whose information outputs are connected to the information inputs of the code comparison element 3, the second group of information inputs of which are connected to the information outputs of the second pulse counter 4, and the output to the output bus 5 and the transfer output of the third counter 6 pulses is connected to the counting input of the second counter 4 pulses, and the information inputs to the information outputs of the first register 7 of the memory, The first input of the fourth pulse counter 8 is connected to the output of the inverter 9, and the transfer output to the first input of the first element OR 10, the output of which is connected to the write enable inputs of the second and third counters 4 and b of the pulses, and the output of the code comparison element 3 is connected to the input of the element 11 delay, the output of which is connected to the counting input of the third pulse counter 6, to the input of the inverter 9, the second input of the first element OR 10 is connected to the control bus 12, the information inputs of the second pulse counter 4 of the pulse are connected to information The second outputs of the second memory register 13, the information inputs of the first memory register 7 are connected to the code bus 14 for setting the fractional part of the division factor, and the information inputs for the second memory register 13 are connected to the code bus 15 for setting the integer part of the division factor, the device also contains the first counter of 16 pulses and the second element IL-17, the counting input of the fifth counter of 16 pulses is connected to the output of the reference frequency generator, the installation input to O is connected to the control bus, and the transfer output to the first input of the second element OR 17, the second input of which is connected to the output of the delay element 11, and the output to the input of the installation in O of the first counter of 2 pulses.

The frequency divider works as follows.

On a Start command from bus 12 (fig. 26), the counter 16 is set to the zero state (fig. 2n), as a result, a pulse is generated at the output P of the counter 16 (fig.

2o), which, through the OR element 17 (Fig. 2m), sets counter 2 (Fig. 2i) to the zero state. In addition, on command Start at the output of the element OR 10 (Fig. 2c) a pulse appears, which in counter 6 (Fig. 2e)

write the contents of register 7 (Fig. 2d) - coefficient K2, and in counter 4 (Fig. 2h) - the contents of register 13 (Fig. 2e) - coefficient K1.

Counter 2 pulses of reference frequency and

a pulse counter 16 performing a time correction reads the pulses of the reference frequency generator 1 (Fig. 2a). When the state of the counter 2 (Fig. 2i) will be equal to the code recorded in the counter 4 (Fig.

2e), at the output of the comparison element 3 a pulse is formed (Fig. 2k), which is fed to the output bus 5. In addition, this same pulse, passed through the delay element 11 (Fig. 2n), goes to the counting input of the counter 6,

increasing the contents of counter 6 by one (Fig. 2e), through the element NOT 9, the content of the counter 8 increases its content by one (Fig. 2p), and through the element OR 17 (Fig. 2m) the counter is zeroed

2 (FIG. 2i) and the cycle of formation of the output pulse is repeated.

After the output of the divider will be formed (p-K2) pulses (Fig. 2k), where p - the capacity of the counters 6 and 8, the counter

6 will be set to zero (Fig. 2e). At its output, a Wits pulse (Fig. 2g) which increases the contents of counter 4 by one (Fig. 2h). After that, the output pulses (Fig. 2k) will be formed through (K1 + 1)

impulse (Fig. 2 &, and).

The generation of output pulses with a modified period will occur until the counter 8 is filled (Fig. 2p), since the capacity of the counter 6 is equal to

the capacity of counter 8, it will be in state K2 (Fig. 2e), and at the output P of counter 8, a pulse appears (Fig. 2c), which through the OR 10 element (Fig. 2c) restores the state of counters 6 and 4 ( Fig. 2e, h) according to the state of the registers 7 (Fig. 2d) and 13 (Fig. 2e).

The instability of the output frequency of the frequency divider depends on the values of the coefficients: K1 is the integer part of the division coefficients; K2 - fractional part of the coefficient

division; p - the capacity of the counters 8 (6), and can be determined by the formula

1/9

Af freH-feb, x (K1 +)

while Af is always less than K1.

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If we assume that Af K1, then in this case an extra pulse appears at the output of the frequency divider.

The values of the coefficients K1, K2 and p are determined as follows. The division ratio of the frequency divider is determined by the formula

 fon.reH 1/1 i K2

 k.1 +

Tvmhtvikh

It is desirable in the scheme to have a capacity of counters 6 and 8, equal to the value of feux. In this case, Af 0.

This can easily be done if the frequency divider has a constant division factor.

In case we need to have a frequency divider with a variable division factor, it is not always convenient to change the division coefficients of counters 6 and 8, as a result, the output frequency of the frequency divider appears on the basis of formula (1), and the coefficient K2 of conditions

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however, K2 is the largest of the integers satisfying this condition. If

Tvmh P

output frequency instability appears.

To eliminate this, it is necessary to make an additional correction of counter 2, for which counter 16 is inserted into the divider circuit, which performs time correction and the OR element 17.

Due to the fact that the frequency is the number of pulses per second, it is to ensure that

The second splitter correction needs to be performed once in 1 second, the counter 2 will go from state Af to state O.

Based on the foregoing, the capacity of the counter 16 must be equal to the frequency of the reference generator 1.

Due to the fact that counter 1 is corrected once every 1 second, the output frequency of the frequency divider is stable for any values of K1, K2, and p.

Since the formation of the output themK2N pulses is necessary (K1-NBUX + -)

pulses, which is less than the frequency of the reference oscillator 8 by the value of Af, the signal at the output of the counter 16 (Fig. 2p) will appear when the counter 2 pulses of the reference frequency are in the state Af (Fig.

2i), setting it to the zero state (Fig. 2i) through the OR element 17 (Fig. 2m).

As a result of this, the state of the counters 6, 4, 2, 8, and 16 is repeated every second, which ensures an increase in the stability of the divider at any values of the coefficients K1. K2 and p.

Claims (1)

Invention Formula Pulse frequency divider with variable fractional division factor for aut. St. 1670788, characterized in that, in order to improve division accuracy by reducing side components in the output signal spectrum, a fifth pulse counter and a second OR element are inserted in it, the count input of the fifth pulse counter is connected to the output of the reference frequency generator. in О - to the control bus, and the transfer output - to the first input of the second OR element, the second input of which is connected to the output of the delay element, and the output to the installation input in the O first pulse counter.  “A d- Ir, In to 01 G four - Li g Lq r - V; ll r WITH , v:. u-.  it $ s I