SU1713100A1 - Reversal counter - Google Patents

Abstract

The invention relates to digital technology and can be used to recalculate pulses. The purpose of the invention, the simplification of the device, is achieved by the introduction of new functional connections by inter-circuit elements. The device contains a clock bus 1, a K-bit reversible counter 2 and counting bits 3, each of which, except for the M-th bit, contains two elements AND-NO 4 and 5, two switching triggers 6 and 7 and t | The eigger 8 is a memory, and the Mth bit contains an unbalanced T-flip-flop 9, performed on two switching triggers 6 and 7 and one flip-flop 8 of memory, 10 addition and 11 subtracting buses. The first switching trigger 6 is made on the AND-HEY elements 12 and 13, the second switching trigger 7 is made on the AND-HRE elements 14 and 15, and the memory trigger 8 is made on the I-^ HE elements 16 and 17. The device can be implemented in basis IL AND-NOT. 1 il.

Description

The invention relates to digital technology and can be used to recalculate pulses.

The purpose of the invention is to simplify the device.

The drawing shows the proposed device, the structural scheme.

The device contains a clock bus 1, a K-bit reversible counter 2 and counting bits, each of which, except for the M-th (), contains the first 4 and second 5 AND-NOT elements, the first 6 and the second 7 of the switching triggers and trigger 8 memory, which is executed in the INE basis, and the Mth () bit contains an asymmetrical T-trigger 9, which is performed on two switching triggers 6 and 7 and one trigger 8 memory in the basis IS-NOT, with the inputs of the first A 4-bit NAND element is connected to the add-on bus 10, the direct output of the first switching trigger 6 and the inverse output of the second the switching trigger 6 and the inverse output of the second switching trigger 7 of the same bit, and the subtracting bus 11 of the subtracting and the direct output of the second switching trigger 7 of the same bit, the output of the first element AND-HE 4 of each bit, except for the (M-1) -th () bit, is connected to the reset and installation inputs of the first switching trigger 6 of the next bit, and the output of the second AND-NE element 5 of each bit, except () -th () , is connected to the input of the installation of the second switching trigger 7 and to the reset inputs of the switching triggers 6 and 7 of the subsequent discharge, the outputs of both elements of AND-NOT 4 and 5 (M-1) -th) bits are connected to the reset inputs of the switching triggers 6 and 7 of the M-th () bit, and in each bits the inverse output of the second switching trigger 7 is connected to the reset inputs of the memory trigger 8 and the first switching trigger 6, the inverse output of which is connected to the memory trigger input 8 of the memory, the forward output of which is connected to the installation input of the first switching trigger 6, and Mm () bit direct output first switching The second trigger b is connected to the installation input of the second switching trigger 7, the addition bus 10 and the subtraction 11 are connected to the corresponding inputs (+ and -) of the K-bit reversing counter 2, the carry outputs (and P-) of which are connected to the reset inputs of all switching triggers 6 and 7 counting bits 31-3 M, clock bus 1 is connected to the synchronous input of the SSK-bit reverse counter 2 and to the reset inputs of all switching triggers 6 and 7 counting bits, and in each of the counting bits the direct output of the first switching trigger 6 soy Dinen with the input of the installation of the second switching trigger 7 of the same bit.

The first switching trigger b is executed on the NAND gate 12 and 13, the second switching trigger 7 is executed on the AND gate 14 and 15, and the trigger 8 of the memory is executed on the gate 16 and 17.

The device works as follows.

The direct status code of the reversible counter is removed in the first Krazr s from the direct outputs of the reversible counter 2, and in bits 3 1-3 M - from the direct outputs of the trigger 8 memory (K - the number of bits of the reversible counter 2).

Reversible counter 2 generates a transfer signal Р + 1 (Р- 1) for each 2nd pulse on bus 1, depending on the device operation mode. Moreover, the transfer signal P-t- (P-) switches in the pause between pulses on bus 1.

Suppose we have an add mode, i.e. On bus 10 Log.1 is present, and on bus 11 - Log.O. Consider the operation of a reversible counting device from the initial state of Log.1 at the direct outputs of a K-bit reversing counter 2 and triggers 8 of the memory of countable bits. Under these conditions, the signal at the output of the transfer P + is equal to Log.1. /

The front of the first pulse on the strip 1 switches the signals on the direct outputs of the K-bit reversing counter 2 and to the Log to the Log.O. G signal at the direct output of the trigger 8 memory of the discharge. By the cut of the first pulse on bus 1, the signals at the transfer output P + of the reversing counter 2 and at the direct output of the first switching trigger of discharge 6 are switched to the transfer output, and the signal at the output of the first logical element AND – HE is then switched to Log.1. yes 3-1, then Log. The signal at the direct output of the first switching trigger 6 bits, then switches to the Log. G signal at the output of the first logic element AND IS NOT 4 bits, and so on. Then, the signals are sequentially switched at the direct output of the first switching trigger. The bit in Log.O and at the output of the first logic element INE 4 of the same bit in Log.G. In order for the reversible counting device to work correctly in a control mode with maximum speed, it is necessary that the last switching takes place before the K-edge of the bus 1. This is possible only if the -2-2 condition is fulfilled, from which the parameters M: K. So, for example, if K will take the values 1, 2, 3 ..., then M will take the values 4, S 10, 22 ..., i.e. with these values of K, a reversible counting device can be built up to a maximum of 5, 12, 25, etc. bits

In spite of the fact that the end-to-end transfer of inter-bit information is organized in the bits, the reversible counting device operates in a control mode with a minimum clock pulse repetition period of 6Ta, where Ts is the maximum delay time of the AND-NOT logic element.

Similarly, the reversing counting device works in the subtraction mode, provided that bus 10 has a L o., And bus 1 T has a Log. one.

Thus, while maintaining the maximum speed of the device, its structure is simplified by reducing the number of connections by an amount equal to 3M-4, and using elements with a lower coupling coefficient at the input.

A reversible counting device can be implemented in the basis of OR-NOT.

Claims (1)

Claims An inverse calculating device containing a clock bus, a K-bit reversible counter and countable bits, each of which, besides the M-th bit, contains two AND-NOT elements, two switching triggers and a memory trigger, which the IS-NOT basis, and the M-th bit contains an unbalanced T-flip-flop, which is performed on two switching triggers and one memory flip-flop in the IS-NOT basis, the input bus is connected to the inputs of the first AND-NOT bit, the direct output of the first switching trigger and the inverse output of the second switching trigger of the same bit, and with the inputs of the second element AND-NOT the connection of the subtraction bus and the direct output of the second switching trigger of the same bit, the output of the first AND element of each bit, except for (M-1) -th bit, is connected to the reset and installation inputs of the first switching trigger of the next bit, and the output of the second AND-NOT element of each bit, except (M-1) -th bit, connected to the setup input of the second switching trigger and with the reset inputs of both switching triggers of the subsequent discharge, the outputs of both elements of NAND (M-1) -th bit are connected to the reset inputs of switching triggers of the M-th discharge, in each of the bits the zero output of the second switching trigger is connected to the reset inputs of the memory trigger and the first switching trigger, the inverse output of which is connected to the installation input of the memory trigger, the direct output of which is connected to the installation input of the first switching trigger, and in the mth discharge direct output of the first switching the trigger is connected to the installation input of the second switching trigger, the addition and subtraction buses are connected to the corresponding inputs 1 and K-bit reversible counter, the carry outputs of which are connected to the reset inputs of all switching triggers of the counting bits, the clock bus is connected to the synchronous input K-bit reversible counter and reset inputs of all switching triggers of countable bits, characterized in that. that, in order to simplify it, in each of the counting bits, except for the Mth bit, the direct output of the first switching trigger is connected to the input of the installation of the second switching trigger of the same bit.