SU1598167A1 - Synchronous binary counter - Google Patents

Abstract

The invention relates to discrete and impulse technology. The purpose of the invention is to increase the speed of the counter. Each I-th digit of the counter contains two commuting and one output triggers, built on the elements AND - NOT. The purpose of the invention is achieved by introducing four AND-NOT elements, generating counter overflow signals and group transfer, additional inputs to AND-NOT output and switching triggers. 1 il.

Description

The invention relates to the discrete and pulse technology and can be used in various computing devices for pulse counting,

The aim of the invention is to increase the speed of the counter.

The drawing shows a functional diagram of a 4-bit synchronous binary counter.

The counter contains the elements AND-NOT 1-1- 1-4: 2-1-2-4: 3-1-3-4 .- 4-1-4-4; 5-1-5-4: 6-1-6-4; 7-10.

In each discharge, the output of element 1 is connected to the first input of element 2, and in the first discharge to the second input of element 6. The output of element 2 is connected to the first inputs of elements 1 and 3. The output of element 3 is connected to the first input of element 4. a the output of the latter is with the first input of the element 5. In the first discharge, the output 4-1 is also connected to the third input of the element 1-1. The output of element 5 in each bit is connected to the first input of element 6 and is the direct output of the discharge of the counter. The output of element 6 is the inverse output of the counter discharge and is connected to the second input of the element 2 of its discharge. JaK-to-T input of the counter is connected to the second inputs of the elements 1-1-1-4. 4-1-4-4. 7 and 10. The output of element 2-1 is connected to the third inputs of elements 2-2 - 2-4 and to the second input of element 8. The output of element 2-2 is connected to the fourth inputs of elements 2-3 and 2-4 and to the third input of the element 8. whose fourth input is connected to the second input of element 2-4 and to the output of element 2-3. and the output of element 2-4 is connected to the fifth input of element 8. In addition, the output of element 4-3 is connected to the second input of element 6-2. the output of the element 4-4 to the second input of the element 6 and to the third input of the element 6-2. the output of element 10 is connected to the fourth input of element 6-2. with the third input of element 6-3 and with the second input

WITH

with

ate yu cx

five

4f

element 6-4, and the output of element 9 is the output of the transfer signal of the counter. Each of the elements 4-1-4-4 contains m additional inputs, and je additional inputs of these elements are interconnected, with 0 + 2) -m input element 1U and with JM input 11 transfer counter /

Synchronous binary counter works as follows.

Let the initial state of the counter be zero, i.e. a-iaaaaai 0000, and on bus T - a signal of logical zero. In this state, all elements 1 and 4 and elements 7 and 10 support a logical 1 signal at the outputs. and elements 2-2 to 2-4 and element 8 are locked with a signal O from the output of element 2-1. The closed states of elements 4-2 through 4-4 (and element 10) are maintained by signals

0c outputs of elements 3-2: 3-4 (and element 9).

With the arrival of the first counting pulse T-1, only element 4-1 is opened; the first output trigger of the counter is set to 1: а4аза2а1 0001. After that, element 2-1 acquires the output state

1, allowing the operation of elements 2-2 to 2-4 and 8. which are locked with signals O from the outputs of elements 2-1 to 1-4 and 7, triggered by T to 1. During a pause (T 0), elements 1-1 are locked - 1-4, 4-1 - 4-4 and 7.10, and at the output of element 2-2, a signal O appears; the locking elements 2-3, 2-4 and 8. On the second counting pulse, the counter assumes the state 0010. Note that the first digit of the counter is a known Dt-flip-flop circuit based on three triggers that operate in the counting mode, regardless of the states of the elements of the remaining bits. During the second pause (), a prohibitory level O is generated.

from the output of element 2-1. and on the third, the counter takes on the state 0011. During the third pause, the output signal of element 2-3 is O, and elements 2-4 are locked. On the fourth pulse, the first discharge is reset to O, and signal O from element 4-3 is set to O the second bit and the third in T; thus, the state of the counter will become 0100.

Next, the counter with each new pulse adds one unit to its content, up to the 15th pulse, after which the counter assumes state 1111, according to which all bans on the inputs of element 8 from the outputs of elements 2-1-2-4 will be cleared, and then on the 16th pulse

five

ten

25

the signal O from the output of element 10 will be set to O, the bits of the second, third and fourth, and the first discharge will be reset to and the signal O from the output of element 4-1. Thus, the counter returns to its original state.

Claims (1)

Formula of the invention Synchronous binary counter, which has n bits and contains six IS-NOT elements in each bit, in each bit the output of the first one is connected to the first input of the second, -the output of which is connected to the first inputs of the first and third elements NAND, the output of the last 15 is connected to the first input of the fourth NAND element, the output of which is connected to the second input of the third and first input of the fifth NAND element, the output of the last f / fuc input of the sixth element (3 AND NOT the output of which is connected with the second inputs of the second and fifth e the second inputs of the first and fourth elements of the NAND. are connected to the clock input of the counter, the first discharge of the counter, the output of the first AND – NOT element is connected to the second input of the sixth element of NAND, and the output of the fourth element is NAND It is connected with the third input of the first NAND element, which is based on the fact that, in order to increase its speed of the JO, the seventh and tenth AND NAND elements, as well as m inputs of transfers, and the J-th input of the transfer. t) is connected to the j-th additionally entered inputs of the fourth elements of the AND NOT all bits and with (j + 2) -M input of the tenth element AND-NOT, the output of the second element AND-NOT 1-bit (1-1, n) is connected to the additionally entered (i-t2) -M to the inputs of the second AND-NOT elements of the 40 most significant bits and to the input of the eighth element of the IS-NOT, the output of the fourth element of the AND-NO of the 1st bit is connected to the (1-1 + 1) th input of the sixth AND element NOT 1 st bit (G 2GGN; To I), the output of the seventh AND-NAND element is connected to the first input of the eighth AND-NEA element, the output of which is connected to the first inputs of the seventh and ninth AND-NEA elements, the output of the last one is the transfer output of the counter and is connected to the first input of the tenth element AND-NOT, the second input of which is connected to the second input of the seventh element AND-NOT and with the clock input of the counter, and the output of the tenth element AND-NOT connected to the additionally entered (n + 2-1) -th inputs of the sixth elements AND-NOT 1 bit 35 five 0 five 77 , W