SU1485399A1 - Cycle-time by prespecified-duration-interval divider - Google Patents

Description

The invention relates to a pulse technique and can be used in computing, technology

2

communication and measurement technology.

The purpose of the invention - povypenie reliability while maintaining the type of output pulse sequence - is achieved by simplifying the device. The device contains a trigger 1 cycle, the input bus 2, the shift register 3 on η triggers with a division factor n, the output bus 4 and the driver 5 pulses. The operation of the device is illustrated by time diagrams. The shift register is made on the elements OR-HE and η D-type triggers. The specified implementation of the shift register is the preferred option for the proposed

properties. 1 hp

schemes for the implementation of devices - § f-ly, 2 ill.

Fig1

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The invention relates to a pulse technique and can be used in computing, communication technology and measurement technology.

The aim of the invention is to improve reliability while maintaining the appearance of the output pulse sequence by simplifying the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - timing diagrams explaining the operation of the device.

The device contains a trigger 1 cycle, the clock input of which is connected to the input bus 2 devices, register

3 shifts on η triggers with a division factor n, the outputs of all digits of which are connected to the output bus

4 devices, and a pulse shaper 5, whose input is connected to the discharge output of the shift register 3, as well as to the K input of the trigger 1, whose direct output is connected to the clock input of the shift register 3.

The device works as follows.

When the first input pulse (Fig. 2a) arrives from cycle 1 trigger, a positive differential arrives at the shift input of shift register 3 (Fig. 2?), Which switches the first trigger of shift register 3 (FIG. 2)> upon receipt of subsequent input pulses at the outputs of the shift register 3, 1,2, ..., n-1, pulses of duration 2 T _{in <are formed} (Fig. 2 {> - 1р.

With the arrival of the (2n-1) th pulse, a differential is formed at the output of the n ~ th digit of the shift register 3, from which the pulse shaper 5 generates a short pulse (Fig. 2 g) that enters the K-input of the cycle trigger,

causing it to switch before the next input pulse arrives. As a result, at the output of the ηth digit of the shift register 3, a pulse is formed, the duration of which is T _y (Fig. 2e). The division ratio of the device is (2η-1).

Claims (2)

Claim 1. A device for dividing the cycle time into intervals of a given duration, containing a cycle trigger, the clock input of which is connected to the device input bus, the shift register on η triggers with a division factor n, the discharge outputs of which are connected to the device output bus, characterized by the fact that in order to improve reliability by simplifying while maintaining the type of output pulse sequence, a short pulse shaper is inserted into it, the input of which is connected to the output of the register discharge, on which a pulse is generated for telnostyu equal to the duration of the period of the input signal, and output - with the K-input of flip-flop cycles, the output of which is connected to the input of shift register taktovm. 2. Device by π. 1, characterized in that the shift register contains the element OR - NOT and η ϋ-type triggers, clock inputs of which are combined and connected to the register input, direct outputs of all the triggers, except the last, are connected to the ϋ-input of subsequent triggers and inputs of the OR-NOT element, the output of which is connected to the ϋ-input of the first trigger, and direct outputs of all triggers are connected by bit register outputs. 1485399 1 g 5 ch-1p-2 gp-1 g "1p * 1 _a l _ ^ _ л1_п_л_я_п_я — п— Fi »L