SU1416980A2 - Digital correlator - Google Patents

Abstract

(The invention relates to computing technology and can be used in automatic control and monitoring systems. 1 pulse generator, adder, synchronization unit. The purpose of the invention is to improve the accuracy of estimates of the values of the correlation functions. The goal is achieved by introducing an RS flip-flop and an I-2CLE element An analysis is made of the state of the second most significant bit of a larger number. 1 Il.

Description

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The invention relates to computing and can be used in automatic control and monitoring systems.

The purpose of the invention is to increase the precision of the digital correlator.

The drawing shows a digital correlator circuit.

The digital correlator contains a first Q digital audio converter 1, a first register 2, a first memory block 3, a second register 4, a second analog to digital converter 5, an EXCLUSIVE OR 6 element, a comparator 7, 15 a switch 8, a third 9 and the fourth 10 registers, the generator of 11 clock pulses, the adder 12, the second memory block 13, the logic element I 14, the synchronization block 15, the RS flip-flop 16, the first-20 out 17 and the second 18 inputs of the correlator, the output 19 of the correlator, s the first to thirteenth outputs 20-32 of the synchronization unit 15 and the I-2ILI 33 element,

The digital correlator operates in the following way.

. At the inputs 17 and 18 of the device, the signals are received X (t) and Y (t). Passing through analog-to-digital converters 1 and 5, their digitized modular units, presented in natural form, after being stored in the corresponding registers 2 and 4 and delays in the first memory block 3 are fed to the inputs of the comparator 7 and the switch 8. This is a software module for a digital code module in the third register 9, and a larger one in the fourth register 10. This distribution of digital codes in registers 9 and 10. actually provides a relay method for calculating the estimate of the path of calculation of the estimate of the correlation function, since in the future all

computational operations are carried out

only over one smaller digital module located in the third register 9. In addition, two higher bits of the modular value of the larger digital code are analyzed in the correlator to obtain a higher accuracy of the calculation of intermediate products. The modular values of the products thus obtained are fed to the input of the adder 12, to the sign input of which from the output of the EXCLUSIVE OR element 6 enters the sign of the product. In the adder 12 together with the second

the memory unit 13 forms the final estimate of the correlation function

...} and -4- - signX ,; signY,; x

, (Kat) in

and

1x, 1- at (h.k1,4 (YV

Iy

2 at 1X ,,. K1 lYvl.

de K (К „) is a coefficient equal to the number of zeros (the number of shifts) between the comma and the first significant digit of the input code X 1 (Y);

a (p) is a coefficient taking into account the incremental shift, which is determined from the condition

1 with a (b) O,

 (R) )

 O with a (b, |) 1, the value of the second most significant bit of the normalized input code X.i (Y).

d.

five

five

To organize the synchronous-individual bins in the digital correlator and calculate the correlation function estimate in a parallel-sequential way according to expression (1), the synchronization block .15 is used. The operation of the digital correlator is synchronized by four sequences of pulses generated by block 15.

Claims (1)

Invention Formula Digital correlator to auth. St. By 1251107, characterized in that, in order to increase accuracy, an RS flip-flop and an I-2ILI element are entered into it, with this 1G-RS flip-flop input connected to the forward output of the nth digit of the fourth register, inverse the output of the (n-1) -th bit of which is connected to the second input of the I-2ILI element. the third and fourth inputs of which are connected to the output of the clock generator, the inverse output of the nth digit of the fourth register is connected to the fifth input of the I-2Sh1I element, the sixth input of which is connected to the forward output of the RS flip-flop, the 8th input of which is connected to the tenth output of the sync block. i 77