SU1270890A1 - Threshold m-from-n logic device - Google Patents

Abstract

The invention relates to the field of automation and computing and can be used in control systems and information processing. The purpose of the invention is to expand the function; of the device’s capabilities, is achieved due to the fact that each AND element is added to the AND-OR element, m additional AND-OR elements are added, m comparison elements, m additional delay elements, D triggers 4, 5, inverter 6, p-bit ds B ; universal universal shift register 8. In this case, all the elements AND-OR AND-NOT and the delay elements are combined in the order O 00 00

Description

interpretive chains 9, having sociated e k and cascades. The device allows you to process information in both parallel and serial

1270890

binary code for any code combinations The use of chips with a medium degree of integration allows reducing the cost of the device „2 Il.

The invention relates to automation and computing and can be used in pulse control and information processing systems. The aim of the invention is to extend the functionality of the threshold logic device m from n due to the possibility of signal processing in both parallel and serial code. Fig. 1 is a schematic diagram of the device. It contains element 1, element AND-OR 2, element 3 comparing the first D-flip-flop 4, second B-t) eigger 5, inverter 6, element IS-NE 7, universal shift register 8, circuit 9 containing K serially connected stages , circuit 10, comprising cascades connected in series. Figure 2 shows the time diagrams of the voltages at the points indicated in Figure 1 by the corresponding letters. The device comes to its initial state when applying to its input 11 (A) a signal of logical zero. In this case, the first trigger 4 is set to the zero state. If by this time the second trigger 5 was in the single state, then after the logical unit was added at the output of the circuit 9 consisting of k stages (point), the trigger 5 will also be set to the zero state. At the same time, at the output of the element AND-NOT 7 and at the outputs of all elements of the AND-OR circuit 10, consisting of 1n cascades, there is a single logical signal, and at the outputs of all elements of the AND-OR 2 circuit 9, a zero logic signal. The value of the signals at the outputs of the universal register can be any. The launch of the device is carried out by applying to its input 11 (A) a single ghost signal. This results in a zero logical signal at the output of the NAND 7 element, which enters the input of the circuit 10 and the input C of the universal shift register 8 (point B). At this point, the input information is recorded in the register 8. The transit time is negative The difference in the signal from the output of the NAND 7 element over the 10 T circuit depends on the number of zero bits of information recorded in the last tn bits of register 8, and is determined by the expression,. .,. (1) where X is the number of bits having a logical zero value; - the delay time of the delay element 1; 2 - time off element AND-OR 2; Il is the number of cascades of the circuit 10. When the output of circuit 10 (point B) has a zero logical signal, a positive signal will appear at the output of the AND-NOT 7 signal. This differential will go to input C of the second D-flip-flop 5 and bring it to the unit state, The positive differential signal from the direct output of this trigger will go to the input of circuit 9 (point D). The transit time of the positive differential from the output of the second P-flip-flop 5 through the circuit 9 1 depends on the number of zero bits recorded in the first k bits of register 8 and is determined by the expression, 2) where y is the number of bits having a logical zero value; I k - the number of cascades of chain 9; .j is the delay time of delay element 1; the activation time of the element AND-OR 2.

The time of passage of a positive voltage drop from the output element

10 T is determined by the AND-NOT 7 chain

P

the number of single bits of information recorded in the m bits of register 8, since now the output of circuit 10 (point B) and, accordingly, at the first inputs of comparison elements 3, a logical zero signal is present. This time is determined by the formula

Tj (tn-x) t. (3) If 1d is less than T ,, then the positive voltage drop from the output of circuit 9 to the input C of the first T) trigger 4 arrives earlier than its input from the logical unit from the output of circuit 10, and the trigger 4 does not change its condition At the same time, the logical zero signal from the output of the inverter 6 will establish the second D-flip-flop 5 in the zero state, which leads to the appearance of the logical zero signal at the output of circuit 9 (point E) and the signal of the logical unit — at the output of the inverter 6. At the same time The output 12 of the element AND-NE 7 (point B) re-emerges a negative signal drop, a new information is written to register 8 and the device operation cycle repeats. If it turns out that T is greater than T, then the signal of the logical unit at the output of circuit 10 turns out earlier than at the output of circuit 9. Then at the moment of occurrence of a positive voltage drop from the output of circuit 9 (point D) at the input of the first D -trigger 4, the latter will go into one state, since at this moment its signal of the logical unit from the output of circuit 10 (point B) comes to its D-input. The inverse output of the first trigger 4 at the fifth input of the element IS-NE 7 receives a logical zero signal, which prohibits the appearance of the signal of the logical zero at the output of the element IS-NOT 7 of the signal zero, after the second I) trigger 5 is reset to the zero state and at the output of the inverter 6, the signal of the logical unit reappears. The operation of the device is suspended until the appearance of a logical zero signal at the device A input. The presence of a logical unit signal at the output of the first D-flip-flop 4 (point E), which is the output of the device, means that in register 8 a "-digit binary number, code which contains the number of zero bits in excess of the number of.

When a logical zero signal is applied to the device A input, the first D trigger 4 is set to the zero state and the device returns to its initial state.

The new binary information is recorded in register 8 at the time of the appearance at input A of a single signal. The input information can be recorded in two different ways, depending on the signal applied to the register mode selection input Vj. code that is present at the inputs of the p ... the moment of occurrence of the rational increment at the input C of the register 8. If the input V | If a single logic signal is applied, the -speed in the sequential code, the previously recorded information is shifted by one bit, and the first bit of register 8 records the information bit from the input. Regardless of the mode of operation of the device, the cycle of operation of the device will be constant and equal to i. period Y Following negative pulses from the output of the element AND-HE 7 (point B) with continuous cyclic operation of the device when the condition T .. T is met. 9. Substituting this condition for T, t |, (see expressions 2 and 3 descriptions), we get (tx) q + tT 2 - niT.i (x + + y) + (km) l, If we choose the element delay time 1 delay so that the inequality | (t-m) 0.5i |, then the time of the element deviation is AND-OR. 2 -T | can be ignored, and the condition of continuous cyclic operation of the device will take the form L-i (x + y) T m ie m x + y, where m is the number characterizing the device response threshold, equal to the number of cascades of circuit 10; x + y is the total number of beats having a logical zero value in the h-bit of the binary code received

to device from source

information.

Claims (1)

This means that after launching, the device periodically polls the source of information until a code dialing is found, the number of zeros in which exceeds the threshold of Ip. The period can be calculated using (1) and (2) T x T, +111 (mx ) t + t1 x - -x ct + t (i + l, H 1) -vniТ, If the threshold is exceeded, the device is paused, while in code 8 the code combination is saved, causing a stop, and at the output of the device is a signal. To restart the device, at its input A it is necessary to supply a zero logical signal, when the output of which is reset, the output signal, and when removed, register 8 records new information and the device resumes operation. Formula Invention Threshold logic device vn from h containing k elements I and k of the delay elements (where K lm the output L-ro of which is connected to the first input L-ro of the element AND, the input of the first delay element is connected to the second inputs of all the elements AND, which is, so that expanding functionality capabilities due to the possibility of processing signals in parallel and in sequential codes, each AND element is added to the AND-OR element, as well as m additional AND-OR elements, n-bit universal shift register, m comparison elements are entered , n- (additional delay elements, two D-flip-flops, an inverter and an AND element - NOT; all AND-OR elements and delay elements are combined into two successive circuits containing, respectively, k cascade needles, in which the first inputs of the additional AND elements are connected with entrances from the corresponding delay elements, which are connected to the Vlokhoda of the corresponding previous AND-OR elements, in the first circuit of k elements, the second inputs of the additional I elements are connected to the k output outputs of the first delay element connected to the forward output of the second D- trigger, and the output of the last of the l-elements AND-OR with the C input of the first p-trigger and through the inverter with the first input of the element AND-NOT and - the input of the second P-trigger, in the second circuit of the pack elements the first inputs of the first and second groups of inputs by And each of additional elements AND-OR are connected respectively to the output and input of the corresponding additional delay element, which in each of the stages, except the first, are connected to the output of the previous element AND-OR, the second inputs of the AND elements are connected to the inverse outputs of the comparison elements, the second inputs of the additional AND elements connected to the direct outputs of the comparison elements, the input of the first of the UE delay elements is connected to the output of the NAND element and the C inputs of the second D-flip-flop and the universal register, the output of the last lementa AND-OR circuit that is connected to the second input of AND-NO, s) input of the first) -triggera and to the first inputs of the comparison element, the second inputs of comparator elements connected to the remaining m universal register outputs, data inputs 1). , .6g, and whose are the information inputs of the device, and the input V is the mode selection input, the inverse input of the second 1) trigger is connected to the third input of the NAND element, the fourth input of the latter is connected to the D input of the second P-trigger, R input the first D-flip-flop is the device start input, the fifth input of the NAND element is connected to the inverse output of the first D-flip-flop, the direct output of which is the device output. FIG. 2