SU1213533A1 - Frequency doubler - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital measuring systems. The doubler contains resistors 1, 2, and 3, capacitor 7, and IS-NE logic gates 4,5,6,8 and 9. The introduction of a doubler of resistors 1–3 and capacitor 7 at the input, as well as the formation of new connections between logic elements to increase its accuracy and stability in operation with changing climatic conditions. 1 il. H

Description

one

The invention relates to a pulse technique, in particular to devices for converting a pulse frequency, and can be used in digital measuring systems.

The purpose of the invention is to improve the accuracy and stability in operation when changing climatic conditions.

FIG. 1 shows a structured electrical frequency doubler; in fig. 2 - temporary dia-; grammers, which show him the work.

The frequency duplicator contains in series the middle middle first 1, second second third 3 resistors connected to the combined first inputs of the first A and second 5 logical elements of AND-NES, the outputs of which are connected to the first and second inputs of the third 6 logic element NAND, respectively, the capacitor 7 connected between the common point of connection of the first 1 and second 2 resistors and the total width of the Zero potential, the fourth 8 and the fifth 9 logical elements AND IS NOT connected in series between the common point of the second 2 and third 3 resist ores and the combined first inputs of the first 4 and second 5 logical elements of AND-NOT. The second input and output of the first 4 I-NOT logic element are connected to the output and the second input of the fourth 8 I-NE element, respectively, and the second inputs of the second 5 and 5 9 I-NOT logic elements are combined with the input of the first resistor 1 and are doubler input .

The frequency doubler operates in the following way.

The input pulse sequence with a period T (Fig. 20) is fed to an integrating circuit consisting of a first resistor 1 and a capacitor 7 d also at the second inputs of the second and fifth logical elements AND-NOT 5 and 9, respectively. The integrated circuit performs a time shift of the input pulse sequence, as shown in FIG. 25. Further, these pulses arrive at the first input of the fourth 8 logical element IS-NOT, which, together with the fifth 9, forms the pulse shaper of the Ymitt trigger type. Second 2 and third 3 resi

13533

The stores determine the threshold value of the Schmitt trigger, as well as the magnitude of its hysteresis. Input and Formed by Schmitt Trigger

5 (FIG. 26), the pulses at the moments of coincidence form, at the output of the fifth 9 logic element AND –NE, the expanded to 3 / 4T pulses, shown in FIG. 2g, delayed by 0.25T

10 relative to the input. These pulses, together with the output pulses of the Schmitt trigger, form, at the output of the first 4 NAND gate, pulses of duration 3/4 T (FIG. 23),

15 in-phase with input. In addition, the output pulses of the fifth 9 logical element AND-NOT together with the input form at the output of the second 5 logical element AND-NOT pulses

20 3 / 4T duration, late

by 1 / 2T relative to the input (figv), as a result of the logical multiplication of these pulses with in-phase and inverting the result at the output

25 of the third 6 NAND logic element, a pulse sequence of doubled following frequency is formed (Fig. 2g).

thirty

Claims (1)

Invention Formula five five 0 five A frequency doubler containing the first, second, third, fourth and fifth logical elements of AND-NOT, the first, second and third resistors, the capacitor, and the outputs of the first and second logical elements of AND-NOT are connected respectively to the first and second inputs of the third logical element AND - NOT, the output of which is the output of the doubler, which is due to the fact that, in order to maintain accuracy and stability in operation under changing climatic conditions, the first, second and third resistors and a capacitor are inserted into it, the fourth and fifth i-NIC elements are connected in series between the first and second inputs of the first and second NAND logic gates, first, second and third resistors are connected in series between the first input of the first NAND logic gates and the first input of the second NAND logic gates and a capacitor is connected between the point of connection of the first and second wires. with a common bus and doubler, 31213533. This is the second input of the fourth element, the swarm of the input of the first logic element is connected to the junction point of the NAND connected to the output of the fourth and third resistors, the second logical element of the NAND. Editor N. Gunko Compiled by V. Tsekhansky Tehred T. Dubinchak Order 785/60 Circulation "18Subscription VNIIPI USSR State Committee for inventions and discoveries. 113035, Moscow, a, Zh-35, Raushsk nab., 4/5 Branch PPP Patent, Uzhgorod, st. Design - 4 e.g. Proofreader L. Patay