SU1318921A1 - Voltage ratio-to-time interval converter - Google Patents

Abstract

The invention relates to radio engineering and can be used in measuring the standing wave ratio in microwave technology. The purpose of the invention is to expand the functionality of the converter. To do this, switches 13, 14, resistor 15, comparator 16 are entered into it. The converter also contains sources I and 2 signals, source 3 reference voltage, integrator 4 consisting of integrating capacitor 5 and amplifier 6, comparator 7, logic 8 , key 9, inputs 10, 19 of the logic circuit and its outputs 11, 12, 17, 18, 20 - 25. The goal is achieved by measuring the following parameters of the input signal during one measurement cycle: voltage ratio, value inverse to the second input signal , the time constant of the measuring circuit, the logarithm of the ratio of the input voltages, the logarithm of each input-. new voltage. 1 zi f-ly, 3 ill. I (L I2i Z / izzi 236 2 "i 4 i g Tt. 5 s device outputs Phi & 1

Description

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The invention relates to the field of radio engineering and can be used in measuring the coefficient of standing wave in microwave technology, as well as circuits of spectrometers and spectrophotometers.

The aim of the invention is to enhance the functionality by simultaneously measuring the ratio of voltages, the reciprocal of one of the voltages, the logarithm of the ratio of voltages, the time constant of the measuring circuit, and the logarithms of each of the input voltages. Figure 1 shows the block diagram of the device; figure 2 is an embodiment of the logic circuit; in FIG. 3, the time diagram of the operation of the device (T i is the time of the operation of the comparators. T ,, is the time of occurrence of the sync pulse).

The device contains the first 1 and second 2 sources, the source 3 of the reference voltage, the integrator 4, consisting of the integrating capacitor 5 and the amplifier 6, the output of which is connected to the first output of the integrating capacitance 5 connected to its input by the second output, the first comparator 7, the logical circuit 8 and key 9, the integrator 4 output being connected to the first input of the first comparator 7, the second input of which is connected to the second j signal source 2, and its output is connected to the first 10 input of the logic circuit 8, the first 11 output of which is connected to governing th input key 9 ,. and the second output is the first J2 output of the device. The device also contains the first 13 and second 14 switches, a resistor 15, the second comparator 16, and the first input of the first switch 13 is connected to

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thirty

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terminal minus the first 1 signal source, terminal plus connected to the first input of the second switch 14, the second input of which is connected to the output of the integrator 4, the first input of the second comparator 16 and the input of the key 9, the output of which is connected to the input of the integrator 4 and through a resistor 15 with the output of the second switch 14, the control input of which is 55 of the third element ZI 39, the R input is connected to the third 17 output of the logic circuit 8, the fourth 18 output of which is connected to the control input of the first switch 13, the second

rygo trigger 27 is connected to the output element 2I-NOT 30; the fifth output 21 is connected to the direct output of the third trigger 28, the second output 12 is connected to you

the input of which is connected to the source 3 of the reference voltage, and the output to the second input of the second comparator 16, the output of which is connected to the second

19 input logic circuit 8, the third

The 20 input of which is connected to the synchronization bus, and from the fifth to the ninth 21-25 its outputs are the outputs of the device.

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Logic circuit 8 consists of the first 26, second 27, third 28 and fourth 29 triggers, element 2I-NOT 30, element 2I 31, delay line 32, first 33, second 34 and third 35 inverters, element ZI-NO 36 and first 37 the second 38 and third ZI elements, the third input 20 is connected to the S inputs of the second 27, third 28 and fourth 29 flip-flops, the second input 19 is connected to the input of the first inverter 33, the output of which is connected to the second input of the ZI element NO 36 and R-input 5 of the third trigger 28, G-input of the first trigger 26 and the first input of the element 2I-NOT 30, the second input d, through a delay line 32 is connected to the direct output of the first trigger 2b, the inverse output of which is connected to its D-input, the fourth output 18 and the second input of the second element ZI 38, the first input of which is connected to the first input of the first 37 and third 39 elements ZI, the first output 11 (key 9) and direct output of the fourth 29 trigger, the R-input of which is connected to the output of the element ZI-HE 36, the first input of which is connected to the second inputs of the first 37 and third 39 elements of the ZI and inverse output of the second trigger 27, my way out which connect with the third 17 and sixth 22 outputs, the third input of the second 5th 38 ZI element and the first input of the 2I element 31, the second input of which is connected to the third input of the ZI NE element 36 and the output of the second inverter 34, whose input is connected to the first the output input 10 and the third input of the first element ZI 37, the output of which is connected to the seventh output 23 and the input of the third inverter 35, whose output is connected to the third input

rygo trigger 27 is connected to the output element 2I-NOT 30; The fifth output 21 is connected to the direct output of the third trigger 28, the second output 12 - to the OUTPUT of element 2I 3), the eighth output 24 - to the output of the second element ZI 38 and the ninth exit 25 - to the output of the third element ZI 39.

The device works as follows.

In the initial state before the appearance of the sync pulse, through the switch 14, the resistor 15 is connected to the output of the integrator 4, through the switch 9 the input and output of the integrator 4 are combined, and through the switch 13, the source 3 of the reference voltage is connected to the second input of the comparator 16.

From the moment of occurrence of the clock (time Td), the key 9 is opened, and through the switch 14, the source 1 of the signal (+ and) is connected to the resistor 15. A linear increase in the output voltage of the integrator 4 (U) begins when comparing it with the source 3 of the reference voltage (time T) at the output 12 of the logic circuit 8, a signal is generated, the duration of which is equal to

At, (КСи, „) I where and

op

Ui

the magnitude of the reference voltage source 3;

R is the resistance value of the resistor 15;

C - the value of the integrating capacitance 5.

At the moment of time T. the comparator 16 is triggered and through the inverter 33 returns the trigger 28 to the initial state, and at its direct output we get a signal whose duration is proportional to the reciprocal of the first signal. The delay line 32 does not allow the state of trigger 27 to change at the moment of the transient, since the trigger 26 changes its state, the switch 13 connects the input of the comparator 16 to the reverse polarity of the source 1 and it returns to the initial state.

At time T, the output signal of the integrator is compared with the voltage (Uj) gToporo of source 2. Comparator 7 generates a signal and at the output of the terminal 31 a signal is generated whose duration is equal to

At (RC) J {- - 1

At time T, the output signal of the integrator 4 will be compared with the voltage of the first source 1. This moment captures the comparator 16, which returns the trigger 27 to the initial state with its signal, changes the state of the trigger 26 and prevents the signal from passing to output 22 , while at the output 22 a signal is formed with the duration At Atc.

Through switch 13, the output of the integrator 4 is connected via a resistor 15 to its input. The process of exponential discharge of capacity 5 begins.

At time T, the output signal of the integrator 4 will be compared with the voltage of the second 2 signal source. This moment is fixed by the comparator 7, and at the output of the element 37 a signal is formed, the duration of which is equal to

dt -RCb (U / i,).

At time Tj, a source 3 of the reference voltage is connected via the switch 13 to the input of the comparator 16, at the time TJ, the output voltage of the integrator 4 is compared with the voltage of the source 3 of the reference voltage. This moment is fixed by the comparator 16 and returns the device to its original state, prohibiting the passage of signals to the outputs 24 and 25.

Output 24 generates a signal of duration

4tj RCEn (1 / and, „) - and, at exit 25

utf, RCVn (l / uon.

The device has returned to its original state and is ready for the next measurement cycle.

Claims (2)

1. A voltage ratio converter in a time interval containing the first and second signal sources, a reference voltage source, an integrator consisting of an integrating capacitor and an amplifier whose output is connected to one of the terminals of the integrating capacitor connected by a second output to its input, the first a comparator, a logic circuit and a key, with the integrator output connected to the first input of the first comparator, the second input of which is connected to the second signal source, and the output connected to the first input of the logic circuit We, the first output of which is connected to the control input of the key, and the second output is the first output of the converter, characterized in that, in order to expand the functionality due to simultaneous measurement of the ratio of voltages, the reciprocal of one of the voltages , the time constant of the measuring circuit and the logarithms of both input voltages, the first and second switches, the resistor, the second comparator are entered into it, with the first input of the iepBoro switch connected to the terminal minus the first signal source connected by the plus terminal to the first input of the second switch, the second input of which is connected to the output, the integrator, the first input of the second comparator and the key input, the output of which is connected to the integrator input and through a resistor with the output of the second switch, whose control input connected to the third output of the logic circuit, the fourth output of which is connected to the control input of the first switch, the second input of which is connected to the source of the reference voltage, and the output to the second input of the second com Arathor, the output of which is connected to the second input of the logic circuit, a third input connected to the synchronization bus, and the fifth to ninth its outputs are with outputs of the second to sixth transducer respectively. 2. The converter according to claim 1, T - is personal, in that the logic circuit consists of the first, second, third and fourth triggers of element 2I-NO, element 2I, delay line, first, second and third inverters, element ZI-NOT and first, second and third elements sixteen ZI, the third input of the logic circuit is connected to the S-inputs of the second, third and fourth flip-flops, the second input is connected to the input of the first the inverter, the output of which is connected to the second input of the ZI-NE element and the R-BXO-house of the third trigger, the C-input of the first trigger and the first input of the 2I-NOT element, the second input of which through the delay line is connected to the direct output of the first trigger, the inverse output of which is connected to its D-input, the fourth output of the logic circuit and the second input of the second ZI element, the first input of which is connected to the first inputs of the first and third ZI elements, the first output of the logic circuit and the direct output of the fourth trigger, the R input of which is connected to the output of the ZI NE element, the first input of which is connected to the second inputs of the first and third ZI elements and inverse output of the second trigger, the direct output of which connected to the third and sixth outputs of the logic circuit, the third input of the second ZI element and the first input of the 2I element, the second input of which is connected to the third input of the element ZI-NOT and the output of the second inverter, whose input is connected to the first input of the logic circuit and the third input of the first ZI element, the output of which is connected to the seventh output of the logic circuit and the input of the third inverter, whose output is connected to the third input of the third ZY element, R the input of the second trigger is connected to the output of the element 2I-NOT, the fifth output ogical circuit: connected to direct the output of the third trigger, the second exit - with the output of element 2I, the eighth output - with the output of the second element ZI and the ninth output - with the output the third element ZI. Figure 2 Ears Ui Editor L.Gratillo That T, Gg Tj T 75 Phage. Compiled by I. Mostovy Tehred M. Khodanich Proofreader A. Obruchar Order 2505/38 Circulation 730 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., A