SU1164747A1 - Device for solving boundary problems - Google Patents

Abstract

A DEVICE FOR SOLVING THE EDGE TASKS, containing two blocks of forming a private solution, each of which contains a code-controlled R grid, two grid switches, two AND elements, two decoders, and two encoders, the output of the first of which is connected to the first input of the first decoder and to the first the input of the first element I, the output of which is connected with the first input of the assignment of the conductivity of the code-controlled R-grid, the first group of internal and boundary nodes of which is connected to the group of information inputs of the first switch of the grids whose input input is connected to the first decoder's output and to the second input of the first element, the output of the second encoder is connected to the first input of the second decoder, and to the first input of the second evil input, whose output is connected to the second input of the conductivity setting of the co-guided R-grid, second the corpse: whose internal and boundary nodes are connected to the group of information inputs of the first switch of control grids whose input is connected to the output of the first decoder and to the second input of the second element I, the first and second swarm switches, the outputs of which are connected respectively to the inputs of the first and second analog-to-digital converters, configuration switch, address code encoder, address code register, configuration code register, first firmware control program consisting of microinstructions register, memory node, microinstructor address switch , microinstructor counter, command register and conditional switches, the output of which is connected to the control of the microinstruction address switch input, output to (L togo connected to the enable input, counting from etchika microinstructions and to the input node memory, the group of outputs of which is connected to a group of microinstructions register inputs, the address output / input is connected to counter preset code recording microinstructions which byhod connected to the first data input of microinstruction addresses kommu05 Tatorey second in4 ;; the formation input of which is connected to the output of the unconditional transition of the microcomputer hiker reciever, the output of the conditional transitional Kl of which is connected to the control input of the condition switch, the output of the command register is connected to the third information input of the microcommand switch the first firmware control block, the input of the dashboard recording is connected to the information

Description

jIHOHHbiMH inputs of the register of the code of the address and the register of the configuration code and with the input of the register of the commands of the first microprogrammed control unit, the code of the micro-operations register of the microcommands of the first microprocessor control register connected to the inputs of the register of the address code and the register of the configuration codes whose output is connected to the control BXO home the encoder of the address code and with the control of the input of the switch of the configurations, the first group of outputs of which is connected to the first group of edge nodes of the code-controlled R-grid of the first block of shape private solution, the second group of boundary nodes of which is connected to the first group of information inputs of the configuration switch, the second group of outputs of which is connected to the first group of boundary nodes of a code-controlled R-grid of the second block of formation of a private solution, the second group of boundary nodes of which is connected to the second group of information inputs switch configuration days, the outputs of the first switch of the grids of the first and second blocks of the formation of a private solution are connected respectively to the first and second info mation inputs of the first switch, the second switch outputs the first and second grids forming blocks are joined by partial solutions to the first and second information inputs of the second commutator of m and l. In order to improve speed, two registers, two code format encoders, a scale factor code register, a switch, a counter and a second microprogram control unit, a microprogram register register output of the second microprogram block, were entered into it. control is connected to the third inputs of the elements AND both blocks of the formation of a private decision to the control inputs of both registers, to the control input of the register of the address code, to the inputs of the first and second conversion resolution, analogue o-digital converters, and to the first information input of the switch for the conditions of the first microprogram control unit, the second information input of which is connected to the output of the counter, from the input; mi of the end of the transformations of analog-digital converters and the register of the address code and with the second information 24 input. the condition switch of the second firmware control unit, the first information input of which is connected to the entry of the configuration register record, with the control inputs of the scale factor code register, the first and second code format encoders, and the data switch, the output of which is the output of the device whose data record input is connected to the input of the register of commands of the second firmware control block, to the information inputs of the first and second code format encoders and to the information input of the register of the mas code headquarters ratio, the first output of which is connected to the control inputs of analog-digital converters, the second output of the scale factor code register is connected to the first data output of the data switch, the second and third information inputs of which are connected to the outputs of the first and second analog-digital converters, respectively, register output address code is connected to the information input of the address code encoder, the output of which is connected to the information inputs of the first and second registers, the first the output of the first register is connected to the control inputs of the first decoders, the second output of the first register is connected to the inputs of the encoders and the control input of the first switch, the first output of the second register is connected to the control inputs to the second decoders, the second output of the second register is connected to the inputs of the second encoders and the control input of the second switch, the first code format encoder is connected to the fourth inputs of the first AND elements, and the output of the second code format encoder is connected to the fourth inputs of the second AND elements, start input unit is connected to the counting input of the counter and to the input of the microinstruction register write microinstructions BTojporo Firmware block; lot control. The invention relates to computing and can be applied to solving boundary value problems described by partial differential equations with functional and nonlinear dependencies of coefficients, methods of discrete modeling. The purpose of the invention is to increase speed; FIG. 1 is a block diagram of the device; FIG. 2 shows a block diagram of microprogram control blocks. The device contains frequency decision forming blocks 1, the set of which includes code control R-grid 2, switches 3 and 4 of grids, elements 5 and 6, decoders 7 and 8, encoders 9 and 10 , Switch 11 configurations, register 12 of configuration codes, encoder 13 of address code, register 14 of address code, registers 15 and 16, switches 17 and 18, analog-digital converters 19, 20, scale factor register 21 input device data recording input 22, encoders 23 and 24 code formats, blocks 25 and 26 of firmware control, data switch 27, device output 28, counter 29, device start input 30. Blocks 25 and 26 contain a micro-command register 3, a memory node 32, a micro-command address switch 33, a micro-command counter 34, a command register 35 and a condition switch 36. The device works as follows,. Data and commands to the machine arrive at the input data bus 22 sequentially byte by byte. To perform any operation in the command registers 35 of the blocks 25 w 26 from the input data bus, the command bytes are inserted. The command code of blocks 25 and 26 is used as the address for the transition to the corresponding microprograms by transferring it via the switch 33 of the microcommand addresses to the input of the node 32 pages. At this address, a micro-command is selected from node 32 and its register S is written in 31 micro-commands. From the microinstructions register 31, from the first output, the transition address and the source selection address of the next microcommand address are fed to the second input of the microcommand address switch 33. From the second output, control signal 472 enters the condition switch 36, and from the third output, the control signal goes to the second input of microinstruction counter 34, From the output group, the control signals go to other units. The corresponding coding of node 32 allows the firmware to perform all functions by sequentially checking the conditions of branching of the microprograms entered at the input of the switch 36 of conditions and sampling the field of control signals in register 31 of microcommands. The first command is to set the configuration of the R-grids 2 matrix. By this command, from the register 31 of the micro-commands, the write enable signal from the input data bus 22 receives the configuration write code into the configuration register 12, from which the configuration code goes to the first input of the encoder 13 of the address code and to the input of the switch 11 configurations. According to this code, the configuration switch 11 connects the border nodes of the R grids 2 of blocks 1, the next command executes the command for setting the address of block 1, the control signal from the register 31 of micro-instructions is written to the register 14 of address code 14 via the input bus 22, which is supposed to be addressed by subsequent Commands, the Address Code of Block 1 from the first output of the Register 14 of the Address Code goes to the second input of the Address Code Code Encoder 13, where, in accordance with the configuration code, the Address Code is converted from the representation in the coordinates of the base The KOH Ig power fields in the physical address code of block 1, the even physical address codes for the signal from block 25 are entered in the first register 15, the odd physical address codes on the signal 26 are entered in the second register 16. From the output of the first register 15, the address code of the module goes to the input of the decoder 7, the address code from the output of the second register 16 is supplied respectively: to the input of the encoder 1O and the second input of the decryptor 8, this code selects block 1 for service; for transferring data through AND elements 5, 6 and for analog cxebfij solutions from the matrix of R-grids 2 through switchboards 3 and 4 grids. The encoders 9 and 10 are provided with means for determining the physical address of block 1. The adjustment of the matrix of R-grids 2 to the solvable task is carried out by executing the data entry command. The data in the device comes in the form of words in a 4-byte-long floating-point format. The procedure for entering data into the matrices of R-grids 2 occurs in a series-parallel fashion. Consistently executing data entry commands in K-grids 2 for all the parameters GS, GY, GZ, GT, UI of the device are tuned to the problem to be solved. Forcing a decision from the R-grids 2 executes the command for setting the scale factor of the solution to be removed (voltage). The scale factor bytes from the output data bus 22 by the signal 25 are loaded into the register 21 of the scale factor code. The scale factor code contains the characteristic and mantissa. Then, the address 14 of the address code is written to the starting address from which the access to the R-grids 2 begins. The decision removal command goes to block 26, which, in accordance with the low-order code in address code register 14, loads the corresponding register 15 or 16 code of the physical address of the unit 1 with the output of the encoder 13 address code. According to this code, the decoder 7 (8) and the encoder 9 send a sampling signal to switch 3. Switch 3 connects the corresponding output of R-network 2 to the second input of switch 17. The potential of the corresponding node through the switch switch 17 is fed to the first input of the analog-digital converter 19, to the second input of which the scale factor code mantissa arrives from the output of the register 21 of the scale factor code, in order to perform hardware scaling. Then block 26 starts analog-to-digital converter 19 and loads counter 29 with code to count the start-up shift interval of analog-to-digital converter 20. At the same time, block 26 builds up the contents of register 14 of the address code, preparing a sample of the next node. By. Is474 — the trigger shift time interval, the readiness signal from the output of counter 29 enters block 26. By this signal, block 26 converts a control signal to the control input of register 16 and the output signal from the encoder 13 of the address code 13 records the register 16, in which the decoder 8 and the encoder 10 sends the sampling signal to the switch 4. The switch 4 grids connects the output of the R-grid 2 to the second input of the switch 18. The potential of the corresponding node is fed to the first input of the analog-digital converter 20, to the second input of which the output register and 21 of the scale factor code, the scale factor mantissa arrives. Then block 25 increases the contents of register 14 of the address code and loads counter 29 to re-read the start shift interval of the analog-digital converter 19. After the conversion of the analog-digital converter 19 from its second output is completed, a conversion end signal is received at the third input of the block 26. On this signal, block 26 sends a signal confirming the readiness of the conversion result to block 25i, which proceeds to form a sequence of four bytes of the word by means of the control- and switchboard 27. The code from the output of the analog-digital conversion 19 is sent to the first input of the switch 27 The third input of which is supplied with the characteristic code from the second output of the register 21 of the scale factor code 21. From the switch output 27, the code in the form of a floating point enters the output data bus. After issuing the first word of the result of the decision, block 25 proceeds to wait for the next signal confirming the readiness of the result from block 26, which after the expiration of the shift interval triggers analog-to-digital converter 19. By this time ends;; Converting analog-to-digital converter 20 and its output Four bytes of the decision result word arrive on the output data bus. Thus, the decision removal command is executed prior to polling all the nodes of the R grids 2.

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Claims (1)

DEVICE FOR SOLVING BOUNDARY VALUE PROBLEMS, containing two blocks for forming a particular solution, each of which contains a code-controlled R-grid, two grid switches, two AND elements, two decoders and two encoders, the output of the first of which is connected to the first input of the first decoder and to the first input the first element And, whose output is connected · · is not connected with the first input of the conductivity task of the code-controlled R-grid, the first group of internal and boundary nodes of which is connected to the group of information inputs of the first grid switch, whose input is connected to the output of the first decoder and to the second input of the first element And, the output of the second encoder is connected to the first input of the second decoder and to the first input of the second element And, the output of which is connected to the second input of the conductivity setting of the code-controlled R-grid, the second group of internal and the boundary nodes of which is connected to the group of information inputs of the first grid switch, the control input of which is connected to the output of the first decoder and to the second input of the second element And, the first and second switches the outputs of which are connected respectively to the inputs of the first and second analog-to-digital converters, a configuration switch, an address code encoder, an address code register, a configuration code register, a first microprogram control unit consisting of a micro-command register, a memory node, a micro-command address switch, a counter microcommands, a command register, and a condition switch, the output of which is connected to the control input of the 3 ”switch of the microcommands address, the output of which is connected to the permission input; with in; the house of the memory node, the group of outputs of which is connected to the group of inputs of the micro-command register, the address output of which is connected to the input of the preliminary record of the code of the micro-command, the output of which is connected to the first information input of the micro-address switch, the second information input of which is connected to the output of the unconditional jump micro-command register, the conditional transition output of which is connected to the control input of the conditions switch, the output of the command register is connected to the third information input of the switch and microinstructions start input device is connected to the counting input of the counter and to the input of the microinstruction register microinstruction first microprogram control unit, the input dangalh ^recording; the device is connected to information 1164747 A ^ ion inputs of the register of the address code and register of the configuration code and to the input of the command register of the first microprogram control unit, the output of the microoperation field of the microcommand register of the first microprogram control unit is connected to the recording inputs of the address code register and the configuration code register, the output of which is connected to the control input of the address code encoder and with the control input of the configuration switch, the first group of outputs of which is connected to the first group of boundary nodes of the code the avaliable R-grid of the first block of forming a private solution, the second group of boundary nodes of which is connected to the first group of information inputs of the configuration switch, the second group of outputs of which is connected to the first group of boundary nodes of a code-controlled R-grid of the second block of forming a private solution, the second group of boundary nodes of which is connected with the second group of information inputs of the switch of configurations, outputs of the first switch of grids of the first and second blocks of the formation of a private solution are connected respectively, to the first and second information inputs of the first switch, the outputs of the second switch of the grids of the first and second blocks of forming a particular solution are connected respectively to the first and second information inputs of the second switch, which is due to the fact that, with In order to improve performance, it introduced two registers, two code format encoders, a scale factor code register, a data switch, a counter and a second microprogram control unit, an output of the microoperation field of the second block microcommands register The microprogram control is connected to the third inputs of the AND elements of the private decision making unit, ”to the control inputs of both registers, to the control input of the address code register, to the resolution enable inputs of the first and second analog-to-digital converters, and to the first information input of the switch of conditions of the first microprogram block control, the second information input of which is connected to the output of the counter, with the inputs of the end of the conversion of analog-digital converters and the code register address and with the second information input. of the conditions switch of the second microprogram control unit, the first information input of which is connected to the input of the configuration register record, with the control inputs of the scale factor code register, the first and second code format encoders and the data switch, the output of which is the device output, the recording input whose data is connected to the input of the command register of the second microprogram control unit, to the information inputs of the first and second code format encoders, and to the information the scale register code register input, the first output of which is connected to the control inputs of analog-to-digital converters, the second scale factor code register output is connected to the first information input of the data switch, the second and third information inputs of which are connected to the outputs of the first and second analog-to-digital converters, the output of the address code register is connected to the information input of the address code encoder, the output of which is connected to the information inputs of the first second registers, the first output of the first register is connected to the control inputs of the first decoders, the second output of the first register is connected to the inputs of the encoders and the control input of the first switch, the first output of the second register is connected to the control inputs of the second decoders, the second output of the second register is connected to the inputs of the second encoders and with the control input of the second switch, the output of the first code format encoder is connected to the fourth inputs of the first AND elements, and the output of the second code format encoder is connected to the even ertymi second inputs of AND gates, the start input of the device connected to the counting input of the counter and to the input of the microinstruction register write microinstructions BTojporo microprogram control unit. I 1164747