SU1145336A1 - Data input device - Google Patents

Abstract

An information input device containing the first switch, a command decoder, an address counter, a control unit, a buffer drive and an analog switch, whose information inputs are device information inputs, the address input of the buffer accumulator is connected to the output of the address counter, which differs in topics. that, in order to simplify the device, it contains the second switch, adder, block, analog memory, address decoder, counter, clock generator, first and second triggers, AND block, shift and 5 registers and data inputs, parallel shift register and register inputs data are the input-output of the device data and the inputs of the command register are the device control input-output, one outputs of the command register are connected to the inputs of the command decoder and to the address input of the analog-digital converter, and through If the address identifier is connected to the first input of the control unit j, the first output of the command decoder is connected to the control inputs of the shift and data registers, the second output to the second input of the control unit, the third output to the third input of the control unit, to the counting input of the address counter, to the installation inputs in 1 of the first and second triggers, a quarter output to the reset input of the address counter and to the installation input O of the second trigger, the non-inverting output of which is connected to the control input of the analog memory block whose outputs are connected to information ma (the analog-digital converter inputs, the inputs with the analog switch outputs, to the control inputs of which the analog output of the analog-digital converter is connected, and to the gate input {the first output of the control unit, the second output of which is connected to input 4) About the first trigger, non-inverting, the output of which is connected to the input of the pulse generator, the output of which is connected to O) the fourth input of the control unit, to the synchronous input of the analog-digital converter and to the counting move counter whose output is connected to a fifth input of the control unit, the digital output of the analog-digital converter and an output buffer storage means are respectively connected to the address and data inputs of the first switch, whose output is connected to the first adder data input, the second information

Description

the input of which is connected to the input of the second switch, the control input of which is connected to the second output of the control unit, the address input to the digital output of the analog-digital converter, the outputs of the adder are connected to the information inputs of the block of elements And the information inputs of the buffer accumulator, the output of the block of elements And are connected with the input of the parallel input of the data register, read write and write buffer buffer are connected respectively to the third and fourth outputs of the control unit, the fifth output to The acy is connected to the input of the serial input of the shift register, the output of which is connected to the input of the setpoint input of the analog-digital converter, and the sixth and seventh outputs of the control unit are connected to the control inputs of the adder, and the seventh output is connected to the control input of the unit of elements And, the eighth output of the unit control is connected to the control input of the first switch, the other outputs of the command register are connected to the inputs of the command desigrator, the data register outputs are connected to the information inputs of the second switch Ator. 2, the apparatus of claim 1, wherein the control unit comprises a third trigger, a first and a second delay elements, first to sixth elements, and the non-inverting output of the third trigger is the first and second outputs of the block and connected to the first inputs of the first, second and the third And elements, the outputs of which are the fifth, fourth and sixth outputs of the block, the inverting output of the third flip-flop is the Bocbfaw output of the block and is connected to the first inputs 11 6. fourth and fifth elements. And the outputs of which are the third and seventh outputs of the unit, the installation input to 1 of the third trigger is connected to the output element I, whose inputs are the first and third inputs of the block, the installation input to the third trigger is the second input of the block, the input of the first delay element is the fourth input of the block, the output is connected to the second input of the first element And, the second inputs of the second and fifth elements And are connected to the output of the second delay element, which is the second output of the block, the input of the second delay element nen to second inputs of the third and fourth AND gates and is a fifth input unit. 3. A device according to claim 1, characterized in that the analog-digital converter contains a comparators, a multiplexer, a serial approximation register and a digital-analog converter, the output of which is the analog output of the analog-digital converter and connected to the first inputs of the comparators, the second inputs of which are informational the analog-to-digital converter inputs, one multiplexer information input, ad) the multiplexer's standard input, the clock input and the output of the register of successive approximations are with the inputs of the setpoint, the address clock input and the digital output of the analog-digital converter, respectively, the outputs of the comparators are connected to other information inputs of the multiplexer, the output of which is connected to the information input of the serial approximation register, the output of which is connected to the input of the digital-analog converter.

The invention relates to automation and computing and can be used as a precision system for collecting and measuring high-speed analog information, as well as in training systems and complexes, providing control and tracking of dynamic objects. A device for inputting information is known, comprising an input amplifier, an analog-to-digital converter, two comparison circuits, four registers, two counters, two memory blocks, a display unit, a control unit, a clock generator, a cultivator, a subtractor, a scaling unit, and a driver tl The disadvantage of the device is its complexity. The closest to the invention to the technical essence is a device for inputting information, comprising a control unit, successively connected sensors, a sensor switch, an analog-digital converter, a reproduction recording unit, as well as serially connected block for storing the approximated characteristics of sensors, arithmetic unit , registration unit, decryption unit of the processing section number, polling switch of the channel number storage unit, current channel number counter, buffer akopitel, the switch polling buffer accumulator, comparing element L21, Lack device - complexity. The aim of the invention is to simplify the device. The goal is achieved by the fact that the device for entering information, containing the first switch, the command decoder, the address counter, the control unit, the buffer accumulator 1 and the analog switch, whose information inputs are the information inputs of the device, the address input of the buffer accumulator is connected to the output of the address counter, contains the second commutator, adder, analog memory block, address decoder, counter, clock generator, first and second triggers AND block, shift registers, commands, and yes GOVERNMENTAL, parallel inputs. The inputs of the shift register and the data register are the input-output of the device data, and the inputs of the command register are the input-output of the device control, the ONE instructions of the command register are connected to the inputs of the command decoder and to the address input of the analog-digital converter, and the address decoder is connected to the first input of the control unit, the first output of the command decoder is connected to the control inputs of the shift and data registers, the second output to the second input of the control unit, the third output to the third input of the control unit, to the counting input the address counter to the inputs-, installation in 1 of the first and second triggers, the fourth output - to the reset input of the address counter and to the installation input in O of the second trigger, the non-inverting output of which is connected to the control input of the analog memory block, the outputs of which are connected to information inputs of analog-to-digital / converter, inputs - with the codes of the analog switch, to the control inputs of which the analog output of the analog-digital converter is connected, and the first output of the control unit is connected to the gate input, D which is connected to the installation input O of the first trigger, the non-inverting output of which is connected to the input of the pulse generator, the output of which is connected to the fourth input of the control unit, to the synchronous input of the analog-digital converter and to the counting input of the counter whose output is connected to the fifth input of the control unit , digital, analog-digital converter code and output of the buffer accumulator are connected respectively to the address and information inputs of the first switch, the output of which is connected to the first input the formation input of the adder, the second information input of which is connected to the output of the second switch, the control input of which is connected to the second output of the control unit, the address input to the digital output of the analog-digital converter, the outputs of the adder are connected to the information and inputs of the I block and to the information inputs of the buffer the accumulator, the output of the block of elements And is connected to the input of the parallel input of the data register, the inputs for reading and writing the buffer accumulator are connected to the third and even The digital output of the control unit, the fifth output of which is connected to the input of the sequential input of the shift register, the output of which is connected to the input of the setpoint input of the analog-digital converter, and the sixth and seventh outputs of the control unit are connected to the control inputs of the adder, and the seventh output is connected to the control And the eighth output of the control unit is connected to the control input of the first switch, the other outputs of the command register are connected to the inputs of the command decoder, the outputs of the data register connected to the information inputs of the second switch. Moreover, the control unit contains the third trigger, the first and second elements of the first, sixth And elements, the non-inverting output of the third trigger is the first and second outputs of the block and is connected to the first inputs of the first, second and third elements And, the outputs of which are the fifth, fourth and sixth outputs of the block, the inverting output of the third flip-flop is the eighth output of the block and is connected to the third inputs of the fourth and fifth And elements, the outputs of which are the third and seventh outputs of the block, the installation stroke in 1 of the third trigger is connected to the output of the sixth element I, whose inputs are the first and the inputs of the block; the installation input in the third trigger is the second input of the block; the input of the first delay element in the / / fourth input block, the output is connected to the second input of the first element And, the second inputs of the second and fifth elements And are connected to the output of the second delay element, which is the second output of the block, the input of the second delay element is connected to the second inputs third The first and fourth elements AND are the fifth input of the block. In addition, the analog-to-digital converter contains a multiplexer comparator, a serial approximation register, and a digital-to-analog converter, the output of which is the analog output of the analog-digital converter and connected to the first inputs of the comparators, the second inputs of which are the information inputs of the analog-digital converter, one multiplexer information input, the multiplexer address input, the clock input and the output of the serial approximation register are setpoint input inputs, address By the synchronous input and digital output of the analog-digital converter, respectively, the outputs of the comparators are connected to other information inputs of the multiplexer, the output of which is connected to the information input of the serial approximation register, which is connected to the input of the digital-analog converter. The drawing shows a diagram of the device. The circuit contains sensors 1 analog signals, analog switch 2, block 3 of analog memory, comparators 4, multiplexer 5, register 6 successive approximations, D / A converter 7, second 8 and first 9 ko1 1 watchers, adder 10, block 11 And elements, input- device data output 12, buffer storage 13, data register 14, shift register 15, control input / output 16, command register 17, command decoder 18, sixth element AND 19, third trigger 20, command decoder 21, second 22 and first 23 triggers 24 clock pulse generator, counter 2 5 addresses, the first element of delay 26 ,. the first element is And 27, the counter 28, the third and fourth element And 29, 30, the second delay element 31, the second element And 32, the fifth element And 33 is the control unit 34, the analog-to-digital converter 35. The device works as follows. To introduce an accurate measurement process taking into account additive errors, the processing cycle of the input analog information is carried out in two steps, which are provided by the following main modes: test and actual measurement. The test mode is designed to determine the individual errors of each measurement channel and is divided into two submodes. The first submode ensures that the code of the reference value is entered into the DAC and begins with reception at input-output 16 to register 17; as a result, a signal is generated. The reception of the code to registers 14 and 15, to which the reference data code arrives. The next command, taken on register 17, is decoded by decoders 21 and sets the triggers 23 and 22 to the one state, and by the coincidence of the signals on the element 19 And the trigger 20 is also set to the single state. The code of the address of the direction taken from register 17 switches on the multiplexer 5 the output of register 15, which stores the code of the reference value, to the input of register data 6. The transition of the trigger 23 to one state ensures the start of the generator 24, the pulses from which are output through the delay element 26 enter the open element AND 27 and shift the contents of the register 15. Thus, the code of the reference value is bitwise through multiplexer 5 enters the register 6 of successive approximations, where the DAC 7 is turned and transformed The voltage level that is applied to the inputs of analog switch 2 and comparators 4. The command is completed by overflowing the counter 28. The first sub-mode ends by issuing a command to the register 17, tipping the counter 2 addresses and trigger 22. The second test sub-modes provide the calculation of individual errors for each channel and begins with the arrival of the command and address to the register 17, sets the triggers 22, 23 to one and increases the content of the counter 25, which provides the addressing corresponding and the memory in the accumulator 13, the trigger 22 controls the mode of sampling-storage of the analog memory block 3 and ensures the fixation of the reference voltage coming from the CDL 7 through the switch 2. Thus, the voltage of the DAC 7 corresponding to the equivalent code is fixed all sensors. By the next start of the generator 24, the conversion cycle (using the ADC 35) of the voltage of the first channel begins. The digital equivalent of this voltage is set at the output of register 6, over the time required to recalculate counter 28, and the counter overflow signal performs the error calculation operation in adder 10 with data from registers 6 and 14 through switches 9 and 8. Result operations after some time provided by the delay element 3 is recorded in the drive 13 (on impulse from the element 32) in the cell. ; addressable by the counter 25. Thus, in the first cell of the accumulator, the mismatch code is recorded between the reference code stored in register 14 and the code obtained as a result of conversion to the ADC. This code characterizes the additive error of the individual channel of the converter (quantization error, drift of the analog memory block, comparator error, etc.) over the time required to measure the first channel. This operation is repeated for all the other channels and, accordingly, in the cells of the accumulator 13, the values of the correction coefficients reflecting the quality of the electronic components of the device are fixed. In the measurement mode, following the test mode, with the command issued, decoded in block 21, the trigger 20 is switched to the zero state, which means a change in the operating mode. Next, the sequence of actions that is necessary to start the ADC to convert the voltage of the selected channel is repeated. The trigger state 20 in this mode reads the correction factor on the first cell of accumulator 13 after measuring the first channel and summing these values on the adder 10, the result of which is transmitted through the block of elements 11 to the input-output 12. Thus, the device o6jecnetizes a precise measurement multi-channel information with automatic correction of the additive error of each channel of the converter. The device has the potential to allow the state of all sensors, i.e. receive a time slice of multi-channel information, and implement operational control of the operation of the converter channels for measurement accuracy. To achieve the same effect in the prototype device, it is not necessary to use parallel analog-digital converters and additional equipment. Equal the effectiveness of the two options through the reduced costs of equipment necessary to provide the same functionality and given accuracy.

The costs of the basic and proposed options can be estimated by the following values:

+ c + c

Cc, C „

com

2С, «- СЫЧС |« 4 «+ с

SSAI

PC + + C

de C cost of single-channel / analog-to-digital converter;

C - the cost of the adder;

Sd is the cost of the buffer accumulator;

Cj is the cost of the control unit;

koM switch cost;

Cc - the cost of the counter;

- With - cost of generator;

C - the cost of the shift register;

Cpnh is a register of successive approximations;

C - the cost of the comparator;

С „- cost of multiplexer Сс - cost of digital-analogue converter.

If we consider that C

C, C, Cf, t ,,, C 5

Com5

"N

UN

 CjjoMu exclude the same parts, then you can get the following estimate of the cost of organizing calculations for the basic and proposed options

 (N-1) (Cn and CJ,

com + Wed + 2C (.

 CCM + 2C (N-1) Cd + CM.

PC

To compare the above expressions, it is necessary to reduce them to the cost of an equivalent functional element, for example, to the cost of a trigger. If the data size is K, and N. is the number of channels, then С, КC, Се СYKj, Ср Сц С, m (N + I) CT, С, КС, с р КСт, с ,. С „+ К-Сч., Ср„ „КСт, Сг А,

and, c then C to (N-1) (A + K A + K A + A)

2A (N-1) (K + 1), G. „K A + K-A + 21og.jK 4- 2A + K A +

(N-1) A + (N + 1) A ЗМ + 2А “

2AN + 2Alog., K.

The effectiveness of the proposed option can be estimated by the relative coefficient

C) - (K + D

ZKA + 2A + 2AN- + 2A logjK (N-t) (K + 1)

IK + 1 -f N +

that, for example, with the number of channels, the N 16 catch and the conversion size of K 12 gives the value of the coefficient iC 5 and means that the efficiency of the above basic and increases with increasing N according to the law determined by the discharge for D.S.

Claims (4)

1. A DEVICE FOR INFORMATION INPUT, comprising a first switch, a command decoder, an address counter, a control unit, a buffer drive and an analog switch, the information inputs of which are information inputs of the device, the address input of the buffer drive is connected to the output of the address counter, characterized in that, in order to simplify the device, it contains a second switch, an adder, an analog memory unit, an address decoder, a counter, a clock generator, the first and second triggers, a block of AND elements, registers yoke, commands and data, inputs of parallel input of the shift register and data register are the input-output of the device data, and the inputs of the command register are the input-output of the device control, some outputs of the command register are connected to the inputs of the command decoder and to the address input of the analog-to-digital converter, and through the address decoder - to the first input of the control unit; the first output of the command decoder is connected to the control inputs of the shift and data registers, the second output is to the second input of the control unit, the third output is to the third input of the control unit, to the counting input of the address counter, to the 1 ”setting inputs of the first and second triggers, the fourth output - to the reset input counter of the address and to the setting input 0 of the second trigger, the non-inverting output of which is connected to the control input of the analog memory unit, the outputs of which are connected to the information inputs of the analog-to-digital converter, odes - with the outputs of the analog switch, to the control inputs of which the analog output of the analog-to-digital converter is connected, and to the gate of the single-output control unit, the second output of which is connected to the setting input to ”0 of the first trigger, the non-inverting output of which is connected to the input of the pulse generator -, owl, the output of which is connected to the fourth input of the control unit, to the clock input of the analog-to-digital converter and to the counting input of the counter, the output of which is connected to the fifth input of the control unit, digitally the output of the analog-to-digital converter and the output of the buffer storage device are connected respectively to the address and information inputs of the first switch, the output of which is connected to the first information input of the adder, the second information input of which is connected to the output of the second switch, the control input of which is connected to the second output of the control unit, address input to the digital output of the analog-to-digital converter, the adder outputs are connected to the information inputs of the block of AND elements and to the information inputs buffer drive, the output of the block of elements AND is connected to the input of the parallel input of the data register, the read and write paths of the buffer drive are connected respectively to the third and fourth outputs of the control unit, the fifth output of which is connected to the input of the serial input of the shift register, the output of which is connected to the input of the setpoint input analog-to-digital Converter, and the sixth and seventh outputs of the control unit are connected to the control inputs of the adder, and the seventh output is connected to the control input of the electronic And, the eighth output of the control unit is connected to the control input of the first switch, the other outputs of the command register are connected to the inputs of the command decoder, the outputs of the data register are connected to the information inputs of the second switch, 2, The device according to claim 1, characterized in that the control unit comprises a third trigger, first and second delay elements, first to sixth elements AND, a non-inverting output of the third trigger is the first and second outputs of the unit and connected to the first inputs of the first, second and of the third AND element, the outputs of which are the fifth, fourth and sixth outputs of the block, the inverting output of the third trigger is the eighth output of the block and is connected to the first inputs of the fourth and fifth elements. And, the outputs of which are the third and seventh outputs of the block, the installation input in 1 of the third trigger is connected to the output of the sixth element And, the inputs of which are the first and third inputs of the block, the installation input in O of the third trigger is the second input of the block, the input of the first delay element is the fourth block input; the output is connected to the second input of the first element And, the second inputs of the second and fifth elements And are connected to the output of the second delay element, which is the second output of the block, the input of the second delay element is connected to the second inputs of the third and fourth elements And is the fifth input of the block. 3. The device according to claim 1, characterized in that the analog-to-digital converter contains comparators, a multiplexer, a register of successive approximations and a digital-to-analog converter, the output of which is an analog output of an analog-to-digital converter and is connected to the first inputs of the comparators, the second inputs of which are information inputs of an analog-digital converter, one information input of the multiplexer, the address input of the multiplexer, the clock input and the output of the sequential approximation register are the setpoint input steps, the address clock input and the digital output of the analog-to-digital converter, respectively, the comparator outputs are connected to other information inputs of the multiplexer, the output of which is connected to the information input of the sequential approximation register, the output of which is connected to the input of the digital-to-analog converter. and complexes providing control and tracking of dynamic objects. A device for inputting 5 information containing input