SU1320827A1 - Device for adaptive compression of information - Google Patents

Abstract

The invention relates to a technique for processing and transmitting information and can be used in telemetry for data compression. The known devices for compressing data using the first-order prediction method are characterized by low speed due to sequential processing of samples or low accuracy. In the proposed device, the speed of the device is improved by using conveyor processing, and by implementing a piecewise linear approximation its accuracy is increased. The processing of samples in the proposed device is carried out in an arithmetic unit performed on two registers, three adders and a multiplier, the output of the arithmetic unit is connected to registers designed to read information from the device. 2 Il. with GS about OS GhE

Description

The invention relates to the processing and transmission of information and can be used in telemetry systems for data storage.

The purpose of the invention is to improve the accuracy of the device by providing a piecewise linear approximation with a given accuracy.

FIG. 1 shows a functional diagram of the device; in fig. 2 - functional scheme of the arithmetic unit.

The device contains an analog-to-digital converter (ADC) 1, chronizer 2, frequency divider 3, counter 4, arithmetic unit 5, first and second adders 6 and 7 (accumulating adders-), unit 8 of comparison, third register 9, first and second registers 10 and P.

Arithmetic unit (Fig. 2) contains the first and second registers 12 and 13 of the shift, the multiplier 14, the first, second and third adders 15-17.

The device works as follows.

The input analog signal is fed to the information input of the ADC 1. In accordance with the sampling frequency, which is set by the chronizer 2 and the divider 3 frequencies, the signal from the output of the ADC 1 is fed to the information input of the arithmetic unit 5. Simultaneously, the clock pulses from the output of the divider 3 frequencies are fed to the second (counting) input of counter 4 and to the control input of the arithmetic unit 5.

The frequency of the clock pulses at the output of the splitter 3 is two times less than the frequency of the pulses at the output of the chroniser 2. In turn, the frequency of the pulses at the output of the chroniser 2 is determined by the delay time of the accumulating adder and comparator unit. These pulses arrive at the first control input (synchronization input) of the first accumulating adder bis with a corresponding delay (for the duration of the addition operation) to the first control input (synchronization input) of the second accumulating adder 7.

In the arithmetic unit 5, the input signal samples are sequentially recorded in the first 12 and second 13 registers and from the first output of block 5 are fed to the first register 10. The multiplier 14 multiplies by -1 count of the signal recorded in register 12. The adder 15 performs the summation samples from the information input of block 5 and from the output of the multiplier 14. At the same time, the adder 16 performs the summation of the samples at the outputs of the multiplier 14 and the register 13.

From the outputs of the adders 15 and 16, the results of the summing go to the third adder 17. At the output of the adder 17, 0

five

0

five

a finite second order difference is obtained at the sampling point I,

A-f (t,) - f (t, -,) (t, -) + f (t,.,),

where ((, |) is the signal count at the output of the register 13;

f (t,) is the signal at the output of the register 12;

f (t, + i) is the signal from the output of the ADC 1.

Such an operation is performed by the arithmetic unit 5 for each sample of the input signal in a pipeline mode, i.e., the samples are simultaneously recorded in registers 12 and 13, the summation of previous samples recorded in these registers is summed by 15-17. From the output of the sum of the matrix 17, the finite difference code of the second order is fed to the information input of the first accumulating adder 6. For each sampling point, at the output of the accumulating adder 6, as a result of successive accumulation of the corresponding finite differences of the second order,

S, (t, -) f (t, +,) - f (t, -) f X (, (t),

where (i) is the current signal reading;

(th;) - the last defined essential (non-redundant) count of the input signal.

From the output of accumulating adder 6, the code of the value Si (t,) is fed to the information input of the second accumulating adder 7. At its output, for each sampling point t, a code of the number

S2 (t,) (t, .f,) - f (t,) (i-k) f (U +,)

0 --f (U)

The module of the current value jS2 (t,) | is compared in comparison block 8 with threshold value b, the movable code of which is stored in register 9. If | S2 (t,), then the output of comparison block 8 is the signal "1, which goes to the second control inputs (reset inputs) accumulating adders 6 and 7, with the result that they are set to zero. At the same time, the signal "1 from the output of the comparison unit 8 is fed to the second inputs (write control inputs) of the first and second registers 10 and 11 and with some delay to the first input (reset input) of the counter 4.

As a result of this, the value register of a certain sample f (t,) is written to the register 10 from the first output of the arithmetic unit 5. In the second register 11 with the second output of the arithmetic unit 5 records 0

five

five

0

five

There is a difference code f (t; -, - i) - f (t;). The second output of the arithmetic unit is the output of the adder 15, in which the difference code of two consecutive samples of the input signal appears.

The outputs of the registers 10 and 11, the output of the counter 4, as well as the output of the comparison unit 8 are the corresponding outputs of the device. Using counter 4, the length of the time interval between two successive samples of the signal is determined.

The output of comparator unit 8 is used to communicate with other devices, for example, to output an interrupt signal to the microprocessor or a signal to write the output values of counter 4 and registers 10 and 11 to the buffer memory of the input compressed signal.

If the value of | S2 (t,) | b, the current signal readout is redundant, and the signal "O" appears at the output of comparison unit 8. This continues the accumulation of the values of S | (tj) and S2 (t,) in accumulating adders 6 and 7.

Thus, the proposed device realizes the adaptive compression of the input information by implementing a piecewise linear approximation of the input signal with a given error b. Using additionally to represent a compressed signal, in addition to the values of essential samples of the difference code f (tfc + i) -f (t), the recovery accuracy of the compressed signal is improved, since in this case the recovery error of the compressed signal may exceed b, but it is less than 26. The proposed device has an increased speed due to pipelining of information in the arithmetic unit. The sampling rate of the input signal is determined only by the delay time of the two accumulating adders and the comparison unit. In the known device, redundant signal samples are extracted by determining the linear portions of the input signal, while in the proposed device a piecewise linear approximation is performed with a given accuracy. In addition, the proposed device has enhanced functionality compared with

with known ones, in which a piecewise linear approximation of the input signal is performed. In these devices, only significant signals are extracted, and in the proposed device, in addition, the difference between each significant count and the next CHI-count is determined. This improves the accuracy of the compressed air recovery.

ten

Claims (1)

Invention Formula A device for adaptive information compression comprising an analog-to-digital converter, the output of which is connected to 5 by the information input of the arithmetic unit, the first output of the arithmetic unit is connected to the first input of the first register, the comparison unit, the output of which is connected to the first and second inputs of the counter and the first register, respectively, and  the chronicler, the control inputs of the analog-digital converter and the arithmetic unit and the second input of the counter are combined, the information input of the analog-digital converter is the device input, the output of the first register, the output of the counter and the output of the comparison unit are respectively , characterized in that, in order to improve the accuracy of the device, a frequency divider has been introduced into it, 0 adders, the second and third registers, the output of the chroniser is connected to the first control inputs of the first and second adders and, through a frequency divider, to the control input of the analog-digital converter, the second and third outputs 5 of the arithmetic unit is connected respectively to the first input of the second register and the information input of the first adder, the output of which is connected to the information input of the second adder, the output of the second adder is connected to the first input of the comparison unit, the output of which is connected to the second input of the register and the second control inputs of the first and the second adders, the output of the third register is connected to the second input of the comparison unit, the output of the second register is the fourth output of the device. 0 ta Cj he o ffm case and te lt t frequency Entrance oIndzorm. entrance Exit about Exit (Fig. 2. Compiled by V. Borodin Editor and KasardaTehred I. VeresKorrektor M. Sharoshi Order 2662/53 Circulation 543 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Design. four