SU1656571A1 - Adaptive data compression unit - Google Patents

Abstract

The invention relates to the processing and transmission of information and can be used by telemetric systems where compression of the transmitted information is required. The purpose of the invention is to increase the information content of the device. The device contains an analog-digital converter 1, a clock 2, a memory block 3. two registers 4 and 5, two multipliers 6 and 7, two adders 8 and 9, a block 10 for determining the sign, a counter 11, an input 12 of the device, an information 13, control 14 outputs and a group of 15 information inputs of the device. 1 il.

Description

The invention relates to the processing and transmission of information and can be used in telemetry systems where compression of the transmitted information is required.

The purpose of the invention is to increase the information content of the device.

The drawing shows a functional diagram of the device.

The device comprises an analog-to-digital converter 1, a chroniser 2, a memory unit 3, the first 4 and second 5 registers, the first 6 and second 7 multipliers, the first 8 and second 9 adders, the sign determination unit 10 and the counter 11, input 12, 13, 14 and 15 - information 13, control outputs 14 and a group of information outputs 15 of the device.

The device operates as follows.

The input analog signal is fed to the information input 12 of the analog-to-digital converter 1. In accordance with the sampling frequency, the signal samples from the output of the converter 1 are sent to the information input of the first adder 8 and sequentially written to the first 4 and second 5 registers, from the output of the last to block 3 memory. At the same time, the clock pulses from the chroniser 2 are fed to the counting input of the counter 11 and to the clock inputs of the first 4 and second 5 registers, the first 8 and second 9 adders, the first 6 and second 7 multipliers, memory block 3 and reference sign determination unit 10. The multiplier 6 multiplies by (-1) the count of the signal recorded in the register 4. The adder 8 sums the samples from the input of the register 4 and the output of the multiplier 6. At the same time, the adder 9 sums the samples at the outputs of the multiplier 6 and register 5. From the outputs of the adders 8 and 9, the summation results go to the multiplier 7, the output of which is the product of two adjacent finite differences at the sampling point ti y (ti) = Δ x (ti) Δχ (ίι + ι), where Ax (ti) = x (tf) - x (ti _: i);

Δχ (ίι + ι) = x (ti + i) - x (ti);

x (ti-i) - samples of the signal at the output of register 5;

x (ti) - samples of the signal at the output of register 4;

x (ti + i) - samples of the signal at the output of the Converter 1.

The device performs these operations for each signal sample in the pipelined mode, i.e. simultaneously, the samples are recorded in registers 4 and 5, the summation of the previous samples recorded in these registers by the adders 8 and 9, and the product of these sums are determined in the multiplier 7. The signal value from the output of the multiplier 7 goes to block 10, in which the signal sign is determined: if the signal is positive or equal to zero, i.e. y (ti)> 0. then the count at the point q is excessive and it is not transmitted, otherwise, i.e. when y (ti) <0, the count is not redundant, and it is read from the output 13 of the device. _s The signal from the output of block 10 is fed to the control inputs of the counter 11 and block 3 of the memory. If the count at ti is not redundant, then the code of this count is read from the memory unit 3 and the distance code between two consecutive non-redundant samples is recorded, which is recorded in counter 11, since counter 11 counts the number of clock pulses between two non-redundant samples of the signal. The signal from the output of block 10 with some delay also arrives at the control input of the reset counter 11 to the zero state. The device has a delay of information at the time of formation of the first finite difference. Therefore, block 10 also includes a delay element, which can be implemented in the form of a shift register, in the first bit of which 1 is written before the device starts operation, and 0 in the rest. This is done so that the first signal counting is defined as non-redundant and read .

The output of block 10 is used as the control output 14 of the device with the aim of interfacing with other digital signal processing devices, for example, microprocessors, to generate an interrupt signal.

Claims (1)

Claim A device for adaptive compression of information containing an analog-to-digital converter, the information input of which is the information input of the device, a chronizer, the output of which is connected to the clock inputs of the analog-to-digital converter, a memory unit, a counter, the first and second registers, the first and second adders and the first input first multiplier. the output of the analog-to-digital converter is connected to the information input of the first register and the first information input of the first adder, the output of the first register is connected to the second input of the first multiplier and the information input 1656571 * of the second register, the output of the latter is connected to the first information input of the second adder and the information input of the memory unit, the output of which is the information output of the device, the output of the first multiplier is connected to the second information inputs of the first and second adders, the control inputs of the memory unit and counter are combined, the outputs of the last are the outputs of the group of information outputs of the device, characterized in that, in order to increase information content, a second multiplier and a block are defined in it of the sign, the output of the chronizer is connected to the clock inputs of the second multiplier and the unit for determining the sign, the outputs of the first and second adders are connected to the first and second inputs of the second multiplier, respectively, the output of which is connected to the input of the sign determination unit, the output of which is connected to the control input of the memory unit and is the control output of the device.