SU1424058A1 - Variable delay unit - Google Patents

Abstract

The invention relates to computing and can be used in beamforming antennas, simulator signals of linear antennas, correlation analyzers, and other equipment for real-time processing of low-frequency signals. The purpose of the invention is to expand the field of application of the device by increasing the frequency of the delay time of the input signals. The goal is achieved in that a controllable delay unit containing an analog-to-digital converter 1, a recirculator - a torus 2, a register 4, a digital-to-analog converter 5, a pulse generator 7, counters 8 and 12, a comparator block 10 and a low-pass filter 6 are entered. OR 9, recirculator 3, and comparator block 1 1, with the sampling rate of the input signal and the total memory capacity of both recyclers increased several times. Recirculators have multiple memory capacities. The period of information circulation is recirculation equal to the sampling period of the input signal. The sequential inclusion of recirculators allows writing to the first recirculator 2 during the circulation period. several samples, remember them for a long time, and when dubbing to the second recirculator 3, restore a compressed copy of the signal. This makes it easier to synchronize the scans of the signal and restore the time scale of the signal at the output of the device. 1 and l. (Ls

Description

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The invention relates to computing and can be used in antenna pattern makers, linear antenna signal simulators, correlation analyzers and other equipment for real-time processing of low-frequency signals.

The aim of the invention is to expand the area of the device's operation by increasing the frequency of the delay of the input signals.

The drawing shows a block diagram of the device.

The device contains analog-to-digital converter 1, recirculators 2 and 3, register 4, digital-to-logic converter 5, low-pass filter 6, pulse generator 7, first counter 8, element OR 9, first comparison unit 10, second the comparison unit 1 and the second counter 12, the input signal is fed to the input 13, the control codes for the delay time are for the inputs 1D and 15, the output for the delayed signal is for output 16, and the output for the delayed compressed copy of the signal is output 17.

In accordance with the Kotelnikov theorem, the upper frequency of the input signal in the prototype device is equal to f, 1 / 2Td 1/2 TaT, d, where Td is the sampling period of the input signal, equal to the recirculation cycle (Tc); N is the volume of the recirculator memory; - the period of the shift of information pulses in the recirculation torus.

Considering that ycTpoficTBa is operated at the maximum values of the shift frequency, an increase in the delay time due to an increase in the memory capacity of the recirculator leads to a decrease in the upper frequency of the signal. For this purpose, two recirculators are connected in series in the device, the first recirculator with a large memory space equal to -KN + 1, and the second one with a memory capacity equal to N 1 (an additional cell is necessary for organizing compression and information shift with respect to clock pulse recording). The input samples are written to both recirculators with a period equal to NTc: d, with the write pulse to the recirculator being the counting pulse for the first recirculator. So

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Thus, for the period of circulation, the first recirculator is recorded with K pi.i-boxes, however, the sequence number of the zip-off samples relative to the write clock pulse is not saved, i.e. in the first recirculation torus there is no compressed signal copy. The prince's nocturnal recording does not violate the sequence of signal samples when it is read from the recirculator, however, the signal delay step is equal to the information circulation period in the first TIJ recirculator (KN -t-,. To obtain the initial step for 1 delay equal to (N 1 ) T, dd, the signal samples are copied by the second recirculator, and the compressed signal copy is restored. The readout and signal organization is similar to the prototype. A compressed compressed output signal can be used to build different correlation signals. x real-time analyzers.

The maximum signal delay time in the first recirculator is t :, N (Klv + Otsdr., And about the second, t sg N (N 1). Thus, the total delay time t: (K + 1) N +, b in K + 1 times longer than the delay}. The delay of the signal in device 1 is continuous. Changing the values of K and N (i.e., the amount of memory of recirculators), you can change the length of the gauge by wide limits of the input signal bandwidth, within wide limits , if the volume of the first recirculator is equal to 3.5 N ;, and the second is N / 2, then the delay time and frequency band of the input signal will increase

2 times.

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The main unit of the device is a recirculator, intended (for recording), a time compression and a signal delay. It can be in analog or digital form and have various known hardware solutions. 3 The device uses digital recirculators The 505 and 155 series microcircuits are used to synchronize the recording and shifting of the signal in the recirculation torus using the last OA aerial link — i from the output of the pulse generator 7, followed by a period, and recording the signal into the rectifier, barely .d (n

blowing with period T, - TC, respectively, from the output of the element OR 9 of the recirculator 2 or from the output of the block 10 comparing the recirculator 3. The period of circulation of the signal sample in the recirculator is (KN 1) T .. fromS-D O

varies by magnitude from T ,,,,. This leads to the fact that the sampling of the output signal, recorded from the recirculator at the moment of arrival of the recording pulse, with each circulation shifts by Tcd, relative to the recording pulse. Therefore, if we select the mth clock pulse from the output of the generator 7 pulses and use it as a recording pulse in recirculator 3, the input samples will be recorded for, held for a time t :, (KN + 1) . Similarly, if there is an nth clock pulse relative to the write pulse in the second recirculator 3 and use it to write information to the register 4, then the signal delay in the recirculator 3 will be equal to t ,,

+ 1).

The device works as follows: im image.

The sequence from the output of the generator 7 pulses is fed to the input of the counter 8, which has the conversion factor N. When the zero code is set at its output, the output of the OR 9 element generates a pulse arriving at the inputs of the analog-python converter 1 and the recirculator 2, which serves and recording the sample of the input signal, and in one period of information circulation in recirculator 2, K signal samples will be recorded. Due to the inclusion of an additional (KN + 1) memory cell in the circulation ring, the recorded samples in each circulation are shifted by one clock cycle relative to the write pulse, which allows to organize reading of the delayed signal, extracting the corresponding clock pulse relative to the write pulse that is used for overwriting signal samples to the recirculator 3. The code of the extracted pulse is fed from input 14 to the input of the comparison unit 10, to another input of which the code from the output of the counter 8 arrives. The pulse from the output of the comparison unit 10 odaets on the record entry of the torus 3 recirculation for rewriting sample

the signal and the reset reset input of the counter 12 for assigning a null code at its output to the overwrite pulse; and. The recalculation factor of counter 12 is also equal to N. Due to the fact that the overwriting period of the signal ri, recirculator 3 corresponds to the period of sample circulation, the output

The recirculator 3, when overwritten, forms a compressed copy of the input signal, which is fed to the input 17 of the device. The counting of the signal from the recirculator 3 occurs in the same way as the reading from the first using the comparator block 11 and counter 12. The pulses from the output of the comparator block 11 are fed to the synchronous input of register 4 to write the countable signal samples into it. These samples are then fed to the digital-to-analog converter 5, which restores the analog waveform, and through the filter 6 of the lower frequencies, the delayed input

The signal arrives at the output 16 of the device.

The delay time of the signal in the device, set by the codes at the inputs 15 and 14, is equal to t тТ (, д5 (KN + 1) - пТ | - дц (N + 1), where the type is corresponding) about the delay code of the first and second recircules tori. The step of tuning the signal delay is.

Claims (1)

Invention Formula The controllable delay block containing the first recirculator, whose information inputs are connected to the outputs of the analog-digital converter, the inputs of which are of the same name as the device, the pulse generator, the output of which is connected to the clock inputs of the first and second counters and the first recirculator, the write input of which is the enable input of the device record, v1.1 the inputs of the first counter are connected to the inputs of the first first comparison unit, the inputs of the second group of which are the first group of inputs of the time code ennoy delay unit, a register, characterized in that, in order to expand the field of application by increasing the length of the delay frequency input signals, it comprises a second recirculating Torr, and comparing the second block zle- cop-OR the inputs of which are connected с1424058 6 to the outputs of the first counter, the output, the inputs of the second group of which element OR connected to the input is recorded the second group of inputs code b of the first recirculate, the output of the device time-out delay, the output second comparison unit connected to the second comparison unit connected to the reset input of the second counter and the input register input, the outputs of which are recorded in the second recirculator, which is the first group whose information input is connected to the device's output outputs, the outputs the generator of the clock pulse generator and the second recirculator are connected to the clock input of the second counter, YOU-IQ information register inputs and the inputs of which are connected to the input of the second group of information the first group of the second unit compared to the device outputs.