SU769595A1 - Adaptive telemetering device - Google Patents

Description

The invention relates to the field of measuring information technology and can find application in systems for transmitting signals with a minimum of data that allow you to restore the signal with a given accuracy.

Four categories of practical methods of recording and corresponding data processing are known [1], which serve to reduce the frequency band and reduce power in telemetry systems. These include the selection of parameters - adaptive sampling, reduction of redundancy and coding.

Adaptive sampling includes a method of changing the sampling frequency of a particular sensor in accordance with the frequency of information input, in contrast to the method of reducing redundancy, in which the initial signal is first sampled by level and time, and then insignificant samples are eliminated.

The invention relates to devices that implement the method of reducing redundancy, and in particular to devices that implement the extrapolation procedure for searching for significant ordinates [2]. In this case, extrapolation is carried out according to the current discrete values of the signal in the direction

the beginning of the adaptive time interval.

A device is known for reducing the redundancy of discrete signals [3], which contains an input memory unit, a comparison circuit, an approximation accuracy setting unit, a control circuit, an adder, a pulse counter, and a pulse packet generator.

The operation of this device is based BUT on the criteria for the selection of significant samples in accordance with the expression

Kf / i + i — yi) · i— (Y · - Yo) \> 5 (0

The disadvantage of this device is its low speed, due to the fact that, to obtain the values (yi ι - - yi) 'i, the quantity (yi + ι - tjt) is introduced into the adder i times by the number of pulses generated by the pulse train generator 20 (summation with accumulation )

The closest in technical essence to the invention is an adaptive telemetry device [4], containing a sensor, the output of which is connected to the 25th input of an analog-to-digital converter (ADC), the output of which is connected to the first input of the summation and comparison unit, the second input of which is connected to the output of the block setting the permissible approximation error, the output is connected to

A ₃ and increments of K1 over the last two clock cycles of the ADC 2 and 6. The resulting amount is taken modulo and compared with the value of the code L ' ₂ = 7, o op' by the first input of the buffer storage unit connected to the output of the device, wa, block control and multiplication unit.

The device verifies the relation ί b) (1 / (- 1 — l / o) _i _ ₁ - (Hi Yo) I> / - Г which after simple transformations reduces to an expression of the form (1).

Due to the fact that in this device the multiplication unit is used to obtain the quantity (yi-i - Yo) ———, the speed of the device is higher than that of the device [3] ,. however, it is limited by the time of multiplication of values given in digital form.

To register and further reduce the redundancy of the data stream of fast processes, it is necessary that the signal transit time through the redundancy reduction devices is less than or equal to the time of one ADC operation cycle. If an ADC with direct comparison is used as a discretizer, then the most stringent requirements for their speed are presented in the device for reducing redundancy.

The aim of the invention is to improve the performance of the device.

In the proposed ego device, the goal is achieved by integrators, an additional ADC and a reference voltage source, the output of which and the sensor output are connected respectively to the first inputs of the integrator and the memory-subtracting unit, the second inputs are connected to the output of the summing and comparing unit. The outputs of the integrator and the storage-subtracting unit are connected to the inputs of the additional ADC, the output of which is connected to the third input of the summing and comparing unit.

The drawing shows a structural diagram of the device.

The device comprises a sensor 1, ADC 2, a summing and comparing unit 3, a unit for setting the permissible approximation error 4, a buffer storage unit 5, a memory-subtracting unit 6, an additional ADC 7, an integrator 8, and a voltage reference source 9.

The device operates as follows.

At time Ts, the output of the ADC 6 contains a code whose value is proportional to the value of y (β —y (G) y (A>) - y Ok)

Ar - fik ί =, ι

J U on ’at Uon 't' b a at the output of the ADC 2.

) 1Y = —---, which arrives at each beat

Uon ’k operation from the output of the unit for setting the permissible approximation error 4.

If the specified difference exceeds the value of K ₂ , then an impulse appears at the output of the summing and comparing unit 3, which resets the integrator 8 to zero and allows the next significant value to be written in digital form to the buffer storage unit 5 and the new analogue value to the storage-subtracting unit 6.

That is, at time Ts, the ratio of analog values is digitally checked.

At OS — At Ok)

V OP t k y Ok)

U about .;

y Ok) and _op ςΔΖ> V _m -t _K 'which, with an appropriate choice of quantity, is equivalent to checking the expression \ Y (* o) - y (Ts) + [y (t _k ) - y (Ts _1)] · / <! >"

Thus, the delay time of the passage of the signal through the device for reducing redundancy is determined by four operations of summation, which can significantly increase the speed of the device.

Claims (4)

1. Reduce redundancy. Thematic issue. Proceedings of the Institute of Electrical and Electronics Engineers, Pross, I EEE, 1967, March, V 55, No. 3, Mir, 1967, p. 8/20. 2.Olhovsky Yu. B. et al. Data Compression for Telemetry, “Owls. radio, 1971. 3. USSR author's certificate number 386424 Cl. G 08 C 19/16, 1970. 4. USSR author's certificate number 525148, cl. G 08C 19/28, 1974 (prototype).