SG98431A1 - Low profile integrated circuit packages - Google Patents
Low profile integrated circuit packagesInfo
- Publication number
- SG98431A1 SG98431A1 SG200006023A SG200006023A SG98431A1 SG 98431 A1 SG98431 A1 SG 98431A1 SG 200006023 A SG200006023 A SG 200006023A SG 200006023 A SG200006023 A SG 200006023A SG 98431 A1 SG98431 A1 SG 98431A1
- Authority
- SG
- Singapore
- Prior art keywords
- integrated circuit
- thinning
- low profile
- circuit packages
- profile integrated
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
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- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/0554—External layer
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- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2924/12—Passive devices, e.g. 2 terminal devices
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Dicing (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/425,706 US6251705B1 (en) | 1999-10-22 | 1999-10-22 | Low profile integrated circuit packages |
Publications (1)
Publication Number | Publication Date |
---|---|
SG98431A1 true SG98431A1 (en) | 2003-09-19 |
Family
ID=23687695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200006023A SG98431A1 (en) | 1999-10-22 | 2000-10-19 | Low profile integrated circuit packages |
Country Status (6)
Country | Link |
---|---|
US (1) | US6251705B1 (de) |
EP (1) | EP1094511A3 (de) |
JP (1) | JP2001168275A (de) |
KR (1) | KR20010060183A (de) |
SG (1) | SG98431A1 (de) |
TW (1) | TW521356B (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3936840B2 (ja) * | 1997-12-22 | 2007-06-27 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
JP2000091273A (ja) * | 1998-09-11 | 2000-03-31 | Sony Corp | 半導体パッケージの製造方法およびその構造 |
US20020014702A1 (en) * | 2000-03-10 | 2002-02-07 | Nazir Ahmad | Packaging structure and method |
US6639321B1 (en) * | 2000-10-06 | 2003-10-28 | Lsi Logic Corporation | Balanced coefficient of thermal expansion for flip chip ball grid array |
US6672947B2 (en) * | 2001-03-13 | 2004-01-06 | Nptest, Llc | Method for global die thinning and polishing of flip-chip packaged integrated circuits |
JP3788268B2 (ja) | 2001-05-14 | 2006-06-21 | ソニー株式会社 | 半導体装置の製造方法 |
FR2829291B1 (fr) * | 2001-08-31 | 2005-02-04 | Atmel Grenoble Sa | Procede de fabrication de capteur d'image couleur avec ouvertures de contact creusees avant amincissement |
FR2829292B1 (fr) | 2001-08-31 | 2004-09-10 | Atmel Grenoble Sa | Procede de fabrication de capteur d'image couleur avec substrat de support soude plot sur plot |
DE10147877B4 (de) * | 2001-09-28 | 2011-08-11 | Epcos Ag, 81669 | Verfahren zur Herstellung eines Bauelementträgers geringer Bauhöhe |
US6867501B2 (en) | 2001-11-01 | 2005-03-15 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing same |
TW584950B (en) | 2001-12-31 | 2004-04-21 | Megic Corp | Chip packaging structure and process thereof |
TW544882B (en) | 2001-12-31 | 2003-08-01 | Megic Corp | Chip package structure and process thereof |
US6673698B1 (en) | 2002-01-19 | 2004-01-06 | Megic Corporation | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers |
TW503496B (en) | 2001-12-31 | 2002-09-21 | Megic Corp | Chip packaging structure and manufacturing process of the same |
US7018268B2 (en) * | 2002-04-09 | 2006-03-28 | Strasbaugh | Protection of work piece during surface processing |
US6713366B2 (en) | 2002-06-12 | 2004-03-30 | Intel Corporation | Method of thinning a wafer utilizing a laminated reinforcing layer over the device side |
JP3910493B2 (ja) | 2002-06-14 | 2007-04-25 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
KR100442699B1 (ko) * | 2002-07-19 | 2004-08-02 | 삼성전자주식회사 | 인접 수동소자 칩이 전기적으로 연결된 웨이퍼, 수동소자및 이를 이용한 반도체 패키지 |
US7250330B2 (en) * | 2002-10-29 | 2007-07-31 | International Business Machines Corporation | Method of making an electronic package |
JP4056854B2 (ja) | 2002-11-05 | 2008-03-05 | 新光電気工業株式会社 | 半導体装置の製造方法 |
US7190082B2 (en) * | 2003-03-24 | 2007-03-13 | Lsi Logic Corporation | Low stress flip-chip package for low-K silicon technology |
US7244663B2 (en) * | 2004-08-31 | 2007-07-17 | Micron Technology, Inc. | Wafer reinforcement structure and methods of fabrication |
US20060141666A1 (en) * | 2004-12-29 | 2006-06-29 | Infineon Technologies Ag | Method for producing a module including an integrated circuit on a substrate and an integrated module manufactured thereby |
DE102005022017B3 (de) * | 2005-05-12 | 2006-10-26 | Infineon Technologies Ag | Verfahren zur Herstellung von Chip-Stapeln sowie zugehörige Chip-Stapel |
KR100817078B1 (ko) * | 2006-12-05 | 2008-03-26 | 삼성전자주식회사 | 시스템-인 패키지 및 시스템-인 패키지의 제작 방법 |
US7932180B2 (en) | 2008-07-07 | 2011-04-26 | Infineon Technologies Ag | Manufacturing a semiconductor device via etching a semiconductor chip to a first layer |
KR101601793B1 (ko) * | 2009-10-08 | 2016-03-09 | 삼성전자주식회사 | 멀티칩 모듈들을 위한 개선된 전기적 연결들 |
US8114707B2 (en) * | 2010-03-25 | 2012-02-14 | International Business Machines Corporation | Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip |
KR100987116B1 (ko) * | 2010-04-15 | 2010-10-11 | (주)유일엔지니어링종합건축사사무소 | 입체적 외벽 및 그 시공방법 |
US9768128B2 (en) * | 2014-01-29 | 2017-09-19 | Infineon Technologies Ag | Chip and method for detecting an attack on a chip |
CN112582285B (zh) * | 2020-12-15 | 2023-07-25 | 青岛歌尔微电子研究院有限公司 | 封装结构的减薄方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US5698474A (en) * | 1996-02-26 | 1997-12-16 | Hypervision, Inc. | High speed diamond-based machining of silicon semiconductor die in wafer and packaged form for backside emission microscope detection |
US5952247A (en) * | 1994-11-23 | 1999-09-14 | Intel Corporation | Method of accessing the circuitry on a semiconductor substrate from the bottom of the semiconductor substrate |
US5963781A (en) * | 1997-09-30 | 1999-10-05 | Intel Corporation | Technique for determining semiconductor substrate thickness |
US6069366A (en) * | 1998-03-30 | 2000-05-30 | Advanced Micro Devices, Inc. | Endpoint detection for thinning of silicon of a flip chip bonded integrated circuit |
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JPH0231437A (ja) * | 1988-07-21 | 1990-02-01 | Oki Electric Ind Co Ltd | 半導体チップの実装方法 |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US5516728A (en) * | 1994-03-31 | 1996-05-14 | At&T Corp. | Process for fabircating an integrated circuit |
KR100443484B1 (ko) * | 1996-02-19 | 2004-09-18 | 마츠시타 덴끼 산교 가부시키가이샤 | 반도체장치및그제조방법 |
DE19707887C2 (de) * | 1997-02-27 | 2002-07-11 | Micronas Semiconductor Holding | Verfahren zum Herstellen und Trennen von elektronischen Elementen mit leitfähigen Kontaktanschlüssen |
JPH10335383A (ja) * | 1997-05-28 | 1998-12-18 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH1167979A (ja) * | 1997-08-13 | 1999-03-09 | Citizen Watch Co Ltd | フリップチップ半導体パッケージの実装構造及びその製造方法 |
-
1999
- 1999-10-22 US US09/425,706 patent/US6251705B1/en not_active Expired - Lifetime
-
2000
- 2000-10-19 SG SG200006023A patent/SG98431A1/en unknown
- 2000-10-19 TW TW089121960A patent/TW521356B/zh not_active IP Right Cessation
- 2000-10-20 KR KR1020000061794A patent/KR20010060183A/ko not_active Application Discontinuation
- 2000-10-23 JP JP2000322417A patent/JP2001168275A/ja active Pending
- 2000-10-23 EP EP00309323A patent/EP1094511A3/de not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US5952247A (en) * | 1994-11-23 | 1999-09-14 | Intel Corporation | Method of accessing the circuitry on a semiconductor substrate from the bottom of the semiconductor substrate |
US5698474A (en) * | 1996-02-26 | 1997-12-16 | Hypervision, Inc. | High speed diamond-based machining of silicon semiconductor die in wafer and packaged form for backside emission microscope detection |
US5963781A (en) * | 1997-09-30 | 1999-10-05 | Intel Corporation | Technique for determining semiconductor substrate thickness |
US6069366A (en) * | 1998-03-30 | 2000-05-30 | Advanced Micro Devices, Inc. | Endpoint detection for thinning of silicon of a flip chip bonded integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
TW521356B (en) | 2003-02-21 |
EP1094511A3 (de) | 2005-09-07 |
EP1094511A2 (de) | 2001-04-25 |
US6251705B1 (en) | 2001-06-26 |
KR20010060183A (ko) | 2001-07-06 |
JP2001168275A (ja) | 2001-06-22 |
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