SG72653A1 - Semiconductor device having field isolation and a process for forming the device - Google Patents

Semiconductor device having field isolation and a process for forming the device

Info

Publication number
SG72653A1
SG72653A1 SG1996006732A SG1996006732A SG72653A1 SG 72653 A1 SG72653 A1 SG 72653A1 SG 1996006732 A SG1996006732 A SG 1996006732A SG 1996006732 A SG1996006732 A SG 1996006732A SG 72653 A1 SG72653 A1 SG 72653A1
Authority
SG
Singapore
Prior art keywords
forming
field isolation
semiconductor device
semiconductor
isolation
Prior art date
Application number
SG1996006732A
Other languages
English (en)
Inventor
George R Myer
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of SG72653A1 publication Critical patent/SG72653A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
SG1996006732A 1995-04-06 1996-03-25 Semiconductor device having field isolation and a process for forming the device SG72653A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/417,524 US5665633A (en) 1995-04-06 1995-04-06 Process for forming a semiconductor device having field isolation

Publications (1)

Publication Number Publication Date
SG72653A1 true SG72653A1 (en) 2000-05-23

Family

ID=23654347

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996006732A SG72653A1 (en) 1995-04-06 1996-03-25 Semiconductor device having field isolation and a process for forming the device

Country Status (4)

Country Link
US (3) US5665633A (ko)
JP (1) JPH08288380A (ko)
KR (1) KR100355692B1 (ko)
SG (1) SG72653A1 (ko)

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US6117748A (en) * 1998-04-15 2000-09-12 Worldwide Semiconductor Manufacturing Corporation Dishing free process for shallow trench isolation
KR100280487B1 (ko) * 1998-06-05 2001-03-02 김영환 반도체소자에서의소자격리구조및그격리방법
FR2785090B1 (fr) * 1998-10-23 2001-01-19 St Microelectronics Sa Composant de puissance portant des interconnexions
KR100280809B1 (ko) * 1998-12-30 2001-03-02 김영환 반도체 소자의 접합부 형성 방법
US6396158B1 (en) 1999-06-29 2002-05-28 Motorola Inc. Semiconductor device and a process for designing a mask
TW445572B (en) * 1999-07-20 2001-07-11 Taiwan Semiconductor Mfg Inter-metal dielectric forming method in metallization processing
US6229640B1 (en) 1999-08-11 2001-05-08 Adc Telecommunications, Inc. Microelectromechanical optical switch and method of manufacture thereof
US6316282B1 (en) * 1999-08-11 2001-11-13 Adc Telecommunications, Inc. Method of etching a wafer layer using multiple layers of the same photoresistant material
US6350659B1 (en) * 1999-09-01 2002-02-26 Agere Systems Guardian Corp. Process of making semiconductor device having regions of insulating material formed in a semiconductor substrate
JP4307664B2 (ja) 1999-12-03 2009-08-05 株式会社ルネサステクノロジ 半導体装置
US6482716B1 (en) * 2000-01-11 2002-11-19 Infineon Technologies North America Corp. Uniform recess depth of recessed resist layers in trench structure
US7061111B2 (en) * 2000-04-11 2006-06-13 Micron Technology, Inc. Interconnect structure for use in an integrated circuit
IT1317516B1 (it) * 2000-05-11 2003-07-09 St Microelectronics Srl Dispositivo integrato con struttura d'isolamento a trench e relativoprocesso di realizzazione.
JP4843129B2 (ja) * 2000-06-30 2011-12-21 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
DE10041084A1 (de) * 2000-08-22 2002-03-14 Infineon Technologies Ag Verfahren zur Bildung eines dielektrischen Gebiets in einem Halbleitersubstrat
DE10041691A1 (de) * 2000-08-24 2002-03-14 Infineon Technologies Ag Halbleiteranordnung
US6614062B2 (en) 2001-01-17 2003-09-02 Motorola, Inc. Semiconductor tiling structure and method of formation
KR100428804B1 (ko) * 2001-02-23 2004-04-29 삼성전자주식회사 반도체 제조 공정의 막질 형성 방법, 이를 이용한 트렌치 격리 형성 방법 및 그에 따른 소자 분리 트렌치 격리 구조
JP4982921B2 (ja) * 2001-03-05 2012-07-25 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US6801682B2 (en) 2001-05-18 2004-10-05 Adc Telecommunications, Inc. Latching apparatus for a MEMS optical switch
US6611045B2 (en) 2001-06-04 2003-08-26 Motorola, Inc. Method of forming an integrated circuit device using dummy features and structure thereof
US6514805B2 (en) * 2001-06-30 2003-02-04 Intel Corporation Trench sidewall profile for device isolation
WO2003044863A1 (en) * 2001-11-20 2003-05-30 The Regents Of The University Of California Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
US6693357B1 (en) * 2003-03-13 2004-02-17 Texas Instruments Incorporated Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity
EP1706899A4 (en) * 2003-12-19 2008-11-26 Third Dimension 3D Sc Inc PLANARIZATION PROCESS FOR MANUFACTURING SUPERJUNCTION DEVICE
US7091106B2 (en) * 2004-03-04 2006-08-15 Advanced Micro Devices, Inc. Method of reducing STI divot formation during semiconductor device fabrication
FR2878081B1 (fr) * 2004-11-17 2009-03-06 France Telecom Procede de realisation d'antennes integrees sur puce ayant une efficacite de rayonnement ameliore.
US7256119B2 (en) * 2005-05-20 2007-08-14 Semiconductor Components Industries, L.L.C. Semiconductor device having trench structures and method
JP4991134B2 (ja) * 2005-09-15 2012-08-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20080245258A1 (en) * 2007-04-06 2008-10-09 General Electric Company Pressure-balanced electric motor wheel drive for a pipeline tractor
US7985655B2 (en) * 2008-11-25 2011-07-26 Freescale Semiconductor, Inc. Through-via and method of forming
US7923369B2 (en) * 2008-11-25 2011-04-12 Freescale Semiconductor, Inc. Through-via and method of forming
CN102709227A (zh) * 2012-06-21 2012-10-03 上海华力微电子有限公司 浅沟槽隔离平坦化方法以及半导体制造方法
US20150097224A1 (en) * 2013-10-08 2015-04-09 Spansion Llc Buried trench isolation in integrated circuits
US9437470B2 (en) 2013-10-08 2016-09-06 Cypress Semiconductor Corporation Self-aligned trench isolation in integrated circuits
US9312135B2 (en) * 2014-03-19 2016-04-12 Infineon Technologies Ag Method of manufacturing semiconductor devices including generating and annealing radiation-induced crystal defects
JP2014187377A (ja) * 2014-05-23 2014-10-02 Renesas Electronics Corp 半導体装置及びその製造方法

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JPS59186342A (ja) * 1983-04-06 1984-10-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6015944A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd 半導体装置
FR2562326B1 (fr) * 1984-03-30 1987-01-23 Bois Daniel Procede de fabrication de zones d'isolation electrique des composants d'un circuit integre
JPS618945A (ja) * 1984-06-25 1986-01-16 Nec Corp 半導体集積回路装置
US4980311A (en) * 1987-05-05 1990-12-25 Seiko Epson Corporation Method of fabricating a semiconductor device
US4958213A (en) * 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
US4916087A (en) * 1988-08-31 1990-04-10 Sharp Kabushiki Kaisha Method of manufacturing a semiconductor device by filling and planarizing narrow and wide trenches
JPH0272745A (ja) * 1988-09-08 1990-03-13 Fujitsu Ltd 波形整形回路
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JPH0324762A (ja) * 1989-06-22 1991-02-01 Hitachi Ltd 半導体集積回路装置
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JP2715581B2 (ja) * 1989-07-31 1998-02-18 松下電器産業株式会社 半導体装置及びその製造方法
US5223736A (en) * 1989-09-27 1993-06-29 Texas Instruments Incorporated Trench isolation process with reduced topography
US5064683A (en) * 1990-10-29 1991-11-12 Motorola, Inc. Method for polish planarizing a semiconductor substrate by using a boron nitride polish stop
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JPH05109886A (ja) * 1991-10-17 1993-04-30 N M B Semiconductor:Kk フイールドシールド分離構造の半導体装置およびその製造方法
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DE69232648T2 (de) * 1991-11-29 2003-02-06 Sony Corp Verfahren zur Herstellung einer Grabenisolation mittels eines Polierschritts und Herstellungsverfahren für eine Halbleitervorrichtung
JPH05190663A (ja) * 1992-01-07 1993-07-30 Iwatsu Electric Co Ltd 半導体集積回路の製造方法
US5292689A (en) * 1992-09-04 1994-03-08 International Business Machines Corporation Method for planarizing semiconductor structure using subminimum features
US5358884A (en) * 1992-09-11 1994-10-25 Micron Technology, Inc. Dual purpose collector contact and isolation scheme for advanced bicmos processes
US5350941A (en) * 1992-09-23 1994-09-27 Texas Instruments Incorporated Trench isolation structure having a trench formed in a LOCOS structure and a channel stop region on the sidewalls of the trench
JP3157357B2 (ja) * 1993-06-14 2001-04-16 株式会社東芝 半導体装置
US5434446A (en) * 1993-07-07 1995-07-18 Analog Devices, Inc. Parasitic capacitance cancellation circuit
US5494857A (en) * 1993-07-28 1996-02-27 Digital Equipment Corporation Chemical mechanical planarization of shallow trenches in semiconductor substrates
US5387540A (en) * 1993-09-30 1995-02-07 Motorola Inc. Method of forming trench isolation structure in an integrated circuit
US5374583A (en) * 1994-05-24 1994-12-20 United Microelectronic Corporation Technology for local oxidation of silicon
US5380671A (en) * 1994-06-13 1995-01-10 United Microelectronics Corporation Method of making non-trenched buried contact for VLSI devices
TW299458B (ko) * 1994-11-10 1997-03-01 Intel Corp
US5534462A (en) * 1995-02-24 1996-07-09 Motorola, Inc. Method for forming a plug and semiconductor device having the same
US5789793A (en) * 1995-07-31 1998-08-04 Kurtz; Anthony D. Dielectrically isolated well structures

Also Published As

Publication number Publication date
KR960039279A (ko) 1996-11-21
JPH08288380A (ja) 1996-11-01
US6285066B1 (en) 2001-09-04
KR100355692B1 (ko) 2002-12-28
US5665633A (en) 1997-09-09
US5949125A (en) 1999-09-07

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