SG68074A1 - Method and apparatus for wire bonded package for integrated circuits - Google Patents

Method and apparatus for wire bonded package for integrated circuits

Info

Publication number
SG68074A1
SG68074A1 SG1998003577A SG1998003577A SG68074A1 SG 68074 A1 SG68074 A1 SG 68074A1 SG 1998003577 A SG1998003577 A SG 1998003577A SG 1998003577 A SG1998003577 A SG 1998003577A SG 68074 A1 SG68074 A1 SG 68074A1
Authority
SG
Singapore
Prior art keywords
ring
bond wires
ground
power
signal traces
Prior art date
Application number
SG1998003577A
Other languages
English (en)
Inventor
John W Orcutt
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of SG68074A1 publication Critical patent/SG68074A1/en

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Classifications

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
SG1998003577A 1997-09-19 1998-09-07 Method and apparatus for wire bonded package for integrated circuits SG68074A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US5953997P 1997-09-19 1997-09-19

Publications (1)

Publication Number Publication Date
SG68074A1 true SG68074A1 (en) 1999-10-19

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SG1998003577A SG68074A1 (en) 1997-09-19 1998-09-07 Method and apparatus for wire bonded package for integrated circuits

Country Status (6)

Country Link
US (1) US6194786B1 (enExample)
EP (1) EP0903780A3 (enExample)
JP (1) JPH11251355A (enExample)
KR (1) KR19990029932A (enExample)
SG (1) SG68074A1 (enExample)
TW (1) TW436949B (enExample)

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Also Published As

Publication number Publication date
US6194786B1 (en) 2001-02-27
EP0903780A3 (en) 1999-08-25
JPH11251355A (ja) 1999-09-17
TW436949B (en) 2001-05-28
KR19990029932A (ko) 1999-04-26
EP0903780A2 (en) 1999-03-24

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