GB1224562A - An etching process - Google Patents

An etching process

Info

Publication number
GB1224562A
GB1224562A GB1937468A GB1937468A GB1224562A GB 1224562 A GB1224562 A GB 1224562A GB 1937468 A GB1937468 A GB 1937468A GB 1937468 A GB1937468 A GB 1937468A GB 1224562 A GB1224562 A GB 1224562A
Authority
GB
United Kingdom
Prior art keywords
layer
etched
chromium
cavity
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1937468A
Inventor
Hall Edward Jarman
Ernest Gerald Bylander
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of GB1224562A publication Critical patent/GB1224562A/en
Expired legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/02Local etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14665Imagers using a photoconductor layer
    • H01L27/14669Infrared imagers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

1,224,562. Etching. TEXAS INSTRUMENTS Inc. 24 April, 1968 [16 May, 1967 (2)], No. 19374/68. Heading B6J. [Also in Division H1] A cavity with a high depth to width ratio is etched in the surface of a body 10, Fig. 9, by directing an etchant fluid through an aperture 30 in a malleable mask 24a, and periodically bending the edges of the mask that extend over the cavity down into the cavity to protect the wells thereof, Fig. 14. The edges may be bent by brushing. The body 10 may comprise germanium semi-conductor material which is bonded to a degenerate semi-conductor substrate 12. The body 10 may be covered with a first chromium layer 22, a gold layer 24 and a second chromium layer 26. The layer 26 is etched through a photomask with hydrochloric acid and methyl alcohol in the presence of zinc dust to leave strips 26a, Fig. 7. The layer 24 is etched through a further photomask using potassium iodide and the layer 22 is then etched with a similar etchant to that used for layer 26. The apertures in layers 24 and 22 define aperture 30. After etching body 10 in a stream of hydrofluoric acid etching liquid, portions 24a of the gold layer are removed with potassium iodide and chromium strips 26a and the portions of the chromium layer 22a are removed with hydrochloric acid and methanol.
GB1937468A 1967-05-16 1968-04-24 An etching process Expired GB1224562A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US63891567A 1967-05-16 1967-05-16
US63891467A 1967-05-16 1967-05-16

Publications (1)

Publication Number Publication Date
GB1224562A true GB1224562A (en) 1971-03-10

Family

ID=27093208

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1937468A Expired GB1224562A (en) 1967-05-16 1968-04-24 An etching process

Country Status (4)

Country Link
DE (1) DE1771344A1 (en)
FR (1) FR1567408A (en)
GB (1) GB1224562A (en)
NL (1) NL6806905A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2206443A (en) * 1987-06-08 1989-01-05 Philips Electronic Associated A method of manufacturing a semiconductor device
EP0903780A2 (en) * 1997-09-19 1999-03-24 Texas Instruments Incorporated Method and apparatus for a wire bonded package for integrated circuits

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL170348C (en) * 1970-07-10 1982-10-18 Philips Nv METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE APPLYING TO A SURFACE OF A SEMICONDUCTOR BODY AGAINST DOTTING AND AGAINST THERMAL OXIDICATION MASK MATERIAL, PRE-FRIENDLY COVERING THE WINDOWS OF THE WINDOWS IN THE MATERIALS The semiconductor body with the mask is subjected to a thermal oxidation treatment to form an oxide pattern that at least partially fills in the recesses.
US3989946A (en) * 1975-03-31 1976-11-02 Texas Instruments Incorporated Arrays for infrared image detection
FR2359511A1 (en) * 1976-07-20 1978-02-17 Philips Nv IR detector elements prodn. - uses IR sensitive plate on support with parallel channels and thickness reducing process with edge rounding step
NL7800583A (en) * 1978-01-18 1979-07-20 Philips Nv PROCESS FOR THE MANUFACTURE OF A DEVICE AND DEVICE MANUFACTURED USING THE PROCESS.
GB2027556B (en) * 1978-07-31 1983-01-19 Philips Electronic Associated Manufacturing infra-red detectors

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2206443A (en) * 1987-06-08 1989-01-05 Philips Electronic Associated A method of manufacturing a semiconductor device
EP0903780A2 (en) * 1997-09-19 1999-03-24 Texas Instruments Incorporated Method and apparatus for a wire bonded package for integrated circuits
EP0903780A3 (en) * 1997-09-19 1999-08-25 Texas Instruments Incorporated Method and apparatus for a wire bonded package for integrated circuits

Also Published As

Publication number Publication date
DE1771344A1 (en) 1971-11-25
FR1567408A (en) 1969-05-16
NL6806905A (en) 1968-11-18

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