SG153720A1 - Semiconductor device and method of forming integrated passive device module - Google Patents

Semiconductor device and method of forming integrated passive device module

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Publication number
SG153720A1
SG153720A1 SG200807731-5A SG2008077315A SG153720A1 SG 153720 A1 SG153720 A1 SG 153720A1 SG 2008077315 A SG2008077315 A SG 2008077315A SG 153720 A1 SG153720 A1 SG 153720A1
Authority
SG
Singapore
Prior art keywords
substrate
over
insulation layer
layer
polymer film
Prior art date
Application number
SG200807731-5A
Other languages
English (en)
Inventor
Yaojian Lin
Jianmin Cao
Qing Zhang
Kang Chen
Jianmin Fang
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of SG153720A1 publication Critical patent/SG153720A1/en

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    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30105Capacitance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
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    • H01L2924/30107Inductance
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0352Differences between the conductors of different layers of a multilayer
    • HELECTRICITY
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09509Blind vias, i.e. vias having one side closed
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    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09509Blind vias, i.e. vias having one side closed
    • H05K2201/09518Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
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    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0147Carriers and holders
    • H05K2203/016Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
SG200807731-5A 2007-12-18 2008-10-16 Semiconductor device and method of forming integrated passive device module SG153720A1 (en)

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Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1940989B1 (en) * 2005-09-29 2010-12-15 Dow Corning Corporation Method of releasing high temperature films and/or devices from metallic substrates
US8409970B2 (en) 2005-10-29 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of making integrated passive devices
US8158510B2 (en) 2009-11-19 2012-04-17 Stats Chippac, Ltd. Semiconductor device and method of forming IPD on molded substrate
US8791006B2 (en) 2005-10-29 2014-07-29 Stats Chippac, Ltd. Semiconductor device and method of forming an inductor on polymer matrix composite substrate
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US8900921B2 (en) * 2008-12-11 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
JP5438980B2 (ja) * 2009-01-23 2014-03-12 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US7998853B1 (en) * 2009-04-06 2011-08-16 Xilinx, Inc. Semiconductor device with through substrate vias
TWI388019B (zh) * 2009-09-02 2013-03-01 Unimicron Technology Corp 封裝結構之製法
TWI404149B (zh) * 2009-12-18 2013-08-01 Univ Nat Pingtung Sci & Tech 半導體封裝件之對位接合方法
TWI412114B (zh) * 2009-12-31 2013-10-11 Advanced Semiconductor Eng 半導體封裝結構及其製造方法
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8624353B2 (en) * 2010-12-22 2014-01-07 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device over semiconductor die with conductive bridge and fan-out redistribution layer
DE102011013228B4 (de) 2011-03-07 2014-05-28 Austriamicrosystems Ag Verfahren zur Herstellung eines Halbleiterbauelements für 3D-Integration
TWI425886B (zh) * 2011-06-07 2014-02-01 Unimicron Technology Corp 嵌埋有電子元件之封裝結構及其製法
TWI447864B (zh) * 2011-06-09 2014-08-01 Unimicron Technology Corp 封裝基板及其製法
CN105789199B (zh) * 2011-11-28 2019-05-21 日月光半导体制造股份有限公司 具有整合被动元件的半导体元件及其制造方法
KR101987367B1 (ko) * 2011-12-15 2019-06-11 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법
US8717136B2 (en) 2012-01-10 2014-05-06 International Business Machines Corporation Inductor with laminated yoke
US9064628B2 (en) 2012-05-22 2015-06-23 International Business Machines Corporation Inductor with stacked conductors
KR101947722B1 (ko) * 2012-06-07 2019-04-25 삼성전자주식회사 적층 반도체 패키지 및 이의 제조방법
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US10622310B2 (en) * 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US9385102B2 (en) * 2012-09-28 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
US10418298B2 (en) 2013-09-24 2019-09-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual fan-out semiconductor package
KR101530066B1 (ko) * 2014-05-19 2015-06-18 삼성전기주식회사 공통 모드 필터 및 그 제조 방법
US10556317B2 (en) 2016-03-03 2020-02-11 P.R. Hoffman Machine Products Inc. Polishing machine wafer holder
US10128192B2 (en) * 2016-07-22 2018-11-13 Mediatek Inc. Fan-out package structure
KR102039887B1 (ko) * 2017-12-13 2019-12-05 엘비세미콘 주식회사 양면 도금 공정을 이용한 반도체 패키지의 제조방법
US11031289B2 (en) 2018-10-31 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and methods of forming the same
WO2020254691A1 (en) * 2019-06-21 2020-12-24 Analog Devices International Unlimited Company A thermal platform and a method of fabricating a thermal platform
US11551777B2 (en) * 2019-08-09 2023-01-10 Micron Technology, Inc. Apparatus with circuit-locating mechanism
TWI752514B (zh) * 2019-11-19 2022-01-11 力成科技股份有限公司 半導體封裝及其製造方法
US20220302081A1 (en) * 2021-03-18 2022-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JP3987573B2 (ja) 1994-10-31 2007-10-10 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 能動素子及び受動素子を有する集積化された半導体装置
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US6976056B1 (en) 1999-06-14 2005-12-13 E.Piphany, Inc. Apparatus and method for company representatives to monitor and establish live contact with visitors to their website
US20070176287A1 (en) 1999-11-05 2007-08-02 Crowley Sean T Thin integrated circuit device packages for improved radio frequency performance
JP3591524B2 (ja) * 2002-05-27 2004-11-24 日本電気株式会社 半導体装置搭載基板とその製造方法およびその基板検査法、並びに半導体パッケージ
US6803303B1 (en) * 2002-07-11 2004-10-12 Micron Technology, Inc. Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts
TWI233188B (en) * 2003-10-07 2005-05-21 United Microelectronics Corp Quad flat no-lead package structure and manufacturing method thereof
US7259077B2 (en) 2004-04-29 2007-08-21 Sychip Inc. Integrated passive devices
US20060217102A1 (en) 2005-03-22 2006-09-28 Yinon Degani Cellular/Wi-Fi combination devices
US7300824B2 (en) * 2005-08-18 2007-11-27 James Sheats Method of packaging and interconnection of integrated circuits
US20070065964A1 (en) 2005-09-22 2007-03-22 Yinon Degani Integrated passive devices
US8669637B2 (en) 2005-10-29 2014-03-11 Stats Chippac Ltd. Integrated passive device system
US7851257B2 (en) 2005-10-29 2010-12-14 Stats Chippac Ltd. Integrated circuit stacking system with integrated passive components
US20070235878A1 (en) 2006-03-30 2007-10-11 Stats Chippac Ltd. Integrated circuit package system with post-passivation interconnection and integration
US7868445B2 (en) 2007-06-25 2011-01-11 Epic Technologies, Inc. Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer

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