SG11201809861XA - Method for fabricating a strained semiconductor-on-insulator substrate - Google Patents
Method for fabricating a strained semiconductor-on-insulator substrateInfo
- Publication number
- SG11201809861XA SG11201809861XA SG11201809861XA SG11201809861XA SG11201809861XA SG 11201809861X A SG11201809861X A SG 11201809861XA SG 11201809861X A SG11201809861X A SG 11201809861XA SG 11201809861X A SG11201809861X A SG 11201809861XA SG 11201809861X A SG11201809861X A SG 11201809861XA
- Authority
- SG
- Singapore
- Prior art keywords
- layer
- substrate
- monocrystalline
- international
- strained
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76275—Vertical isolation by bonding techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Peptides Or Proteins (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1654369A FR3051596B1 (fr) | 2016-05-17 | 2016-05-17 | Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant |
| PCT/EP2017/061793 WO2017198687A1 (en) | 2016-05-17 | 2017-05-17 | Method for fabricating a strained semiconductor-on-insulator substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11201809861XA true SG11201809861XA (en) | 2018-12-28 |
Family
ID=56322203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201809861XA SG11201809861XA (en) | 2016-05-17 | 2017-05-17 | Method for fabricating a strained semiconductor-on-insulator substrate |
Country Status (8)
| Country | Link |
|---|---|
| US (3) | US10957577B2 (de) |
| EP (1) | EP3459107B1 (de) |
| JP (1) | JP6949879B2 (de) |
| CN (1) | CN109155278B (de) |
| FR (1) | FR3051596B1 (de) |
| SG (1) | SG11201809861XA (de) |
| TW (1) | TWI711118B (de) |
| WO (1) | WO2017198687A1 (de) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10833194B2 (en) | 2010-08-27 | 2020-11-10 | Acorn Semi, Llc | SOI wafers and devices with buried stressor |
| FR3051596B1 (fr) * | 2016-05-17 | 2022-11-18 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant |
| CN112567511B (zh) * | 2018-06-29 | 2023-08-25 | 长江存储科技有限责任公司 | 半导体结构及其形成方法 |
| US11610808B2 (en) * | 2019-08-23 | 2023-03-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor wafer with low defect count and method for manufacturing thereof |
| CN112447771B (zh) * | 2020-10-16 | 2023-12-01 | 广东省大湾区集成电路与系统应用研究院 | GeSiOI衬底及其制备方法、GeSiOI器件及其制备方法 |
| US11532642B2 (en) * | 2020-12-14 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-function substrate |
| US11955374B2 (en) * | 2021-08-29 | 2024-04-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming SOI substrate |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4521542B2 (ja) * | 1999-03-30 | 2010-08-11 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体基板 |
| FR2842350B1 (fr) * | 2002-07-09 | 2005-05-13 | Procede de transfert d'une couche de materiau semiconducteur contraint | |
| EP1443550A1 (de) * | 2003-01-29 | 2004-08-04 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Verfahren zur Herstellung einer kristallinen Spannungsschicht auf einem Isolator, halbleitende Struktur dafür und so hergestellte Halbleiterstruktur |
| US6911379B2 (en) * | 2003-03-05 | 2005-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming strained silicon on insulator substrate |
| US7329923B2 (en) * | 2003-06-17 | 2008-02-12 | International Business Machines Corporation | High-performance CMOS devices on hybrid crystal oriented substrates |
| US6830962B1 (en) * | 2003-08-05 | 2004-12-14 | International Business Machines Corporation | Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes |
| US6815278B1 (en) * | 2003-08-25 | 2004-11-09 | International Business Machines Corporation | Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations |
| US6992025B2 (en) * | 2004-01-12 | 2006-01-31 | Sharp Laboratories Of America, Inc. | Strained silicon on insulator from film transfer and relaxation by hydrogen implantation |
| US7087965B2 (en) * | 2004-04-22 | 2006-08-08 | International Business Machines Corporation | Strained silicon CMOS on hybrid crystal orientations |
| US7767541B2 (en) * | 2005-10-26 | 2010-08-03 | International Business Machines Corporation | Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods |
| EP2333824B1 (de) * | 2009-12-11 | 2014-04-16 | Soitec | Herstellung von dünnen SOI-Vorrichtungen |
| US9406798B2 (en) | 2010-08-27 | 2016-08-02 | Acorn Technologies, Inc. | Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer |
| KR102189611B1 (ko) * | 2014-01-23 | 2020-12-14 | 글로벌웨이퍼스 씨오., 엘티디. | 고 비저항 soi 웨이퍼 및 그 제조 방법 |
| FR3051596B1 (fr) * | 2016-05-17 | 2022-11-18 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant |
| FR3051595B1 (fr) * | 2016-05-17 | 2022-11-18 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant |
-
2016
- 2016-05-17 FR FR1654369A patent/FR3051596B1/fr active Active
-
2017
- 2017-05-17 TW TW106116265A patent/TWI711118B/zh active
- 2017-05-17 JP JP2018560481A patent/JP6949879B2/ja active Active
- 2017-05-17 WO PCT/EP2017/061793 patent/WO2017198687A1/en unknown
- 2017-05-17 CN CN201780030016.9A patent/CN109155278B/zh active Active
- 2017-05-17 US US16/301,276 patent/US10957577B2/en active Active
- 2017-05-17 EP EP17729386.7A patent/EP3459107B1/de active Active
- 2017-05-17 SG SG11201809861XA patent/SG11201809861XA/en unknown
-
2021
- 2021-03-19 US US17/207,202 patent/US11728207B2/en active Active
-
2023
- 2023-08-14 US US18/449,298 patent/US20230386896A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP3459107A1 (de) | 2019-03-27 |
| US20200321243A1 (en) | 2020-10-08 |
| WO2017198687A1 (en) | 2017-11-23 |
| US10957577B2 (en) | 2021-03-23 |
| US20230386896A1 (en) | 2023-11-30 |
| US11728207B2 (en) | 2023-08-15 |
| CN109155278A (zh) | 2019-01-04 |
| FR3051596B1 (fr) | 2022-11-18 |
| TW201806075A (zh) | 2018-02-16 |
| CN109155278B (zh) | 2023-06-27 |
| JP2019521510A (ja) | 2019-07-25 |
| US20210225695A1 (en) | 2021-07-22 |
| TWI711118B (zh) | 2020-11-21 |
| JP6949879B2 (ja) | 2021-10-13 |
| FR3051596A1 (fr) | 2017-11-24 |
| EP3459107B1 (de) | 2019-12-18 |
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