CN112567511B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
CN112567511B
CN112567511B CN201880096616.XA CN201880096616A CN112567511B CN 112567511 B CN112567511 B CN 112567511B CN 201880096616 A CN201880096616 A CN 201880096616A CN 112567511 B CN112567511 B CN 112567511B
Authority
CN
China
Prior art keywords
bonding
layer
bonding layer
substrate
semiconductor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201880096616.XA
Other languages
English (en)
Other versions
CN112567511A (zh
Inventor
王新胜
张莉
张高升
万先进
华子群
王家文
丁滔滔
朱宏斌
程卫华
杨士宁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN202311008252.4A priority Critical patent/CN117012754A/zh
Publication of CN112567511A publication Critical patent/CN112567511A/zh
Application granted granted Critical
Publication of CN112567511B publication Critical patent/CN112567511B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452Chemical vapour deposition [CVD], e.g. laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05023Disposition the whole internal layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05073Single internal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/05076Plural internal layers being mutually engaged together, e.g. through inserts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/05186Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/05576Plural external layers being mutually engaged together, e.g. through inserts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/05686Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/27444Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
    • H01L2224/27452Chemical vapour deposition [CVD], e.g. laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2902Disposition
    • H01L2224/29023Disposition the whole layer connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29186Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954Coating
    • H01L2224/29599Material
    • H01L2224/29686Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/335Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034Bonding interfaces of the bonding area
    • H01L2224/80357Bonding interfaces of the bonding area being flush with the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

本发明涉及一种半导体结构及其形成方法,所述半导体结构包括:第一基底;位于所述第一基底表面的第一键合层,所述第一键合层的材料为包含C元素的介质材料,所述第一键合层背向所述第一基底的表层的C原子浓度大于或等于35%。所述半导体结构在的第一键合层在键合时能够提高键合强度。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体技术领域,尤其涉及一种半导体结构及其形成方法。
背景技术
在3D的芯片技术平台中,通常会将两片以上形成有半导体器件的晶圆通过晶圆键合技术进行键合,以提高芯片的集成度。现有的晶圆键合技术,在晶圆键合面上形成键合薄膜以进行键合。
现有技术中,通常采用氧化硅和氮化硅薄膜作为键合薄膜,键合强度不够,导致工艺过程中容易出现缺陷,产品良率受到影响。
并且,键合薄膜内还形成有金属连接结构,在混合键合的过程中,所述金属连接结构容易在键合界面出现扩散现象,导致产品性能受到影响。
因此,如何提高晶圆键合的质量,是目前亟待解决的问题。
发明内容
本发明所要解决的技术问题是,提供一种半导体结构及其形成方法。
本发明提供一种半导体结构,所述半导体结构包括:第一基底;位于所述第一基底表面的第一键合层,所述第一键合层的材料为包含C元素的介质材料,所述第一键合层背向所述第一基底的表层的C原子浓度大于或等于35%。
可选的,所述第一键合层中,C的原子浓度均匀分布。
可选的,所述第一键合层中,C的原子浓度随第一键合层厚度增加而逐渐增大。
可选的,所述表层厚度为
可选的,还包括:第二基底,所述第二基底表面形成有第二键合层,所述第二键合层与所述第一键合层表面相对键合固定。
可选的,所述第二键合层的材料为包含C元素的介质材料,所述第二键合层背向所述第二基底的表层的C原子浓度大于或等于35%。
可选的,所述第二键合层的材料与所述第一键合层的材料相同。
可选的,还包括:贯穿所述第一键合层的第一键合垫;贯穿所述第二键合层的第二键合垫;所述第一键合垫与第二键合垫相对键合连接。
本发明的技术方案还提供一种半导体结构,包括:第一基底;位于所述第一基底表面的键合叠层,所述键合叠层包括键合的若干层键合层,所述键合叠层的材料为包含Si、N、C和O的介质材料。
可选的,所述键合叠层为两层具有CH3键的键合层分别经氧化后键合而成。
可选的,所述键合层靠近键合面的表层的C原子浓度大于或等于35%。
可选的,还包括:第二基底,位于所述键合叠层背向所述第一基底的一侧。
可选的,还包括:贯穿所述键合层的键合垫;两个所述键合层内的键合垫相对键合连接。
本发明的技术方案还提供一种半导体结构的形成方法,包括:提供第一基底;在所述第一基底表面形成第一键合层,所述第一键合层的材料为包含C元素的介质材料且含有CH3键;提供第二基底;在所述第二基底表面形成第二键合层,所述第二键合层的材料为包含C元素的介质材料且含有CH3键;使所述第一键合层、第二键合层的表层氧化,以使CH3键被氧化为OH键;将所述第一键合层和第二键合层相对键合连接。
可选的,所述第一键合层和第二键合层的表层内的C原子浓度大于或等于35%。
可选的,采用等离子体增强化学气相沉积工艺形成所述第一键合层。
可选的,所述第一键合层和第二键合层中,C的原子浓度均匀分布或者C的原子浓度随第一键合层、第二键合层厚度增加而逐渐增大。
可选的,所述表层厚度为
本发明的半导体结构的第一键合层在键合时能够具有较高的键合力,并且能够阻挡金属材料在键合界面的扩散,从而提高形成的半导体结构的性能。
附图说明
图1至图4为本发明一具体实施方式的半导体结构的形成过程的结构示意图;
图5为本发明一具体实施方式的半导体结构的示意图;
图6为本发明一具体实施方式的半导体结构的示意图。
具体实施方式
下面结合附图对本发明提供的半导体结构及其形成方法的具体实施方式做详细说明。
请参考图1至图4,为本发明一具体实施方式的半导体结构的形成过程的结构示意图。
请参考图1,提供第一基底100。
所述第一基底100包括第一半导体衬底101、形成于所述第一半导体衬底101表面的第一器件层102。
所述第一半导体衬底101可以为单晶硅衬底、Ge衬底、SiGe衬底、SOI或GOI等;根据器件的实际需求,可以选择合适的第一半导体衬底101,在此不作限定。该具体实施方式中,所述第一半导体衬底101为单晶硅晶圆。
所述第一器件层102包括形成于所述半导体衬底101上的半导体器件、连接所述半导体器件的金属互连结构、覆盖所述半导体器件以及金属互连结构的介质层等。所述第一器件层102可以为多层或单层结构。在一个具体实施方式中,所述第一器件层102包括介质层以及形成于介质层内的3D NAND结构。
请参考图2,在所述第一基底100表面形成第一键合层200,所述第一键合层的材料为包含C元素的介质材料,自所述第一键合层表面向所述第一键合层内部一定厚度的表层内的C的原子浓度大于或等于35%。
可以采用化学气相沉积工艺,形成所述第一键合层200。该具体实施方式中,采用等离子体化学气相沉积工艺形成所述第一键合层200。
所述第一键合层200的材料为包含C元素的介质材料。在一个具体实施方式中,所述第一键合层200主要包含Si、N和C。在其他具体实施方式中,基于化学气相沉积工艺中采用的反应气体,以及具体产品的需求,所述第一键合层200内还可以掺杂有Si、N、O、H、P、F等元素中的至少一种。所述第一键合层200的材料可以为掺碳氮化硅、掺碳氮氧化硅、掺氮碳氧化硅等。
在一个具体实施方式中,采用等离子体增强化学气相沉积工艺形成所述第一键合层200,采用的反应气体包括三甲基硅烷或四甲基硅烷中的一种以及括NH3,三甲基硅烷或四甲基硅烷与NH3的流量比为2:1,射频功率为800W。
通过控制所述第一键合层200的形成工艺参数,可以调整所述第一键合层200内各组分的浓度,对所述第一键合层200与第一器件层102之间的粘附力、第一键合层200的介电系数以及与其他键合层进行键合后的键合力进行调整。
所述第一键合层200中的C能够有效提高所述第一键合层201在键合过程中,与其他键合层之间的键合力。因此,C浓度越高,与其他键合层之间进行键合时产生的键合力越大。所述第一键合层200表面处的C浓度越高,与其他键合层进行键合时产生的键合力越大。由于C在所述第一键合层200内会以-CH3基团的形式存在,在经过键合之前的氧化以及等离子体活化等处理后,-CH3会被氧化成-OH,从而增加羟基数目,最终在键合时,提高键合界面Si-O键的数目,从而提高键合强度。因此,在形成所述第一键合层200的过程中,通过调整工艺参数,在所述第一键合层200背向所述第一基底的表层的C的原子浓度大于或等于35%,以使得所述第一键合层200表面具有较高的C浓度。在一个具体实施方式中,所述表层的厚度可以为在另一具体实施方式中,所述第一键合层200厚度为/>的表层内,C的原子浓度大于40%。
由于不同材料层之间的粘附力与界面两侧的材料组分相关,材料组分越接近,粘附力越强。为了增强所述第一键合层200与所述第一器件层102之间的粘附力,可以在形成所述第一键合层200的过程中,逐渐调整工艺参数,使得所述第一键合层200内的组分浓度逐渐发生变化,使得所述第一键合层200与所述第一器件层102界面两侧的材料组分接近。在一个具体实施方式中,在形成所述第一键合层200的过程中,随着第一键合层200厚度的增加,通过调整沉积工艺的参数,使得C的原子浓度随第一键合层200厚度增加而逐渐增大,使得所述第一键合层200表面的C的原子浓度最大。在其他具体实施方式中,在形成所述第一键合层200的过程中,保持沉积工艺参数不变,使得第一键合层200中各元素在不同厚度位置处的浓度均匀分布,例如第一键合层200中C的原子浓度在各厚度位置处保持一致。
在另一具体实施方式中,也可以通过调整行程工艺参数,使得形成的所述第一键合层200的密度随厚度增加而逐渐改变。例如自所述第一器件层102表面向上,所述第一键合层200的密度逐渐增大、逐渐减小或者先增大后减小。所述第一键合层200与第一器件层102界面处密度接近。
所述第一键合层200的厚度不能过小,以确保在将所述第一键合层200与其他键合层进行键合时,所述第一键合层200具有足够的键合厚度。在一个具体实施方式中,所述第一键合层200的厚度大于
所述第一键合层200还可以包括两层以上堆叠的子键合层,不同子键合层的元素组分不同,各个子键合层内的组分浓度可以不随厚度变化,也可以随厚度渐变。通过调整个子键合层内的组分浓度,可以对第一键合层200与第一器件层102之间的粘附力、各子键合层界面的粘附力以及第一键合层200的介电系数进行调整。
请参考图3,在另一具体实施方式中,还包括:提供第二基底300;在所述第二基底300表面形成第二键合层400。
所述第二基底300包括第二半导体衬底301以及位于所述第二半导体衬底201表面的第二器件层302。
采用化学气相沉积工艺在所述第二器件层302表面形成第二键合层400,所述第二键合层400的材料可以为氧化硅或氮化硅。
在该具体实施方式中,所述第二键合层400的材料也可以为包含C元素的介质材料,在一个具体实施方式中,所述第二键合层400主要包含Si、N和C。在其他具体实施方式中,基于化学气相沉积工艺中采用的反应气体,以及具体产品的需求,所述第二键合层400内还可以掺杂有Si、N、O、H、P、F等元素中的至少一种。可以采用与形成所述第一键合层200相同的方法形成所述第二键合层。请参考上述具体实施方式中的第一键合层200的描述,在此不再赘述。在一个具体实施方式中,所述第二键合层400的材料与上述第一键合层200的材料相同。
请参考图4,将所述第二键合层400和所述第一键合层200表面相对键合固定。
所述第一键合层200和第二键合层400内的C部分以CH3的形式存在,在进行键合之前,还包括对所述第二键合层400表面和所述第一键合层200表面均依次进行氧化处理和等离子体处理;所述氧化处理能够对第二键合层400和第一键合层200内的-CH3或其他含碳基团进行氧化,所述等离子体处理用于对所述第一键合层200和第二键合层400表面的化学键进行活化提高第一键合层200和第二键合层400的表面能,最终将所述-CH3或其他含碳基团氧化成-OH。在一个具体实施方式中,所述氧化处理采用氧气作为氧化气体,温度为25℃~80℃,时间为20min~200min;所述等离子体处理采用N2作为等离子体源气体,射频功率为75W~300W,时间为15s~45s。
由于所述第一键合层200和第二键合层400表面处的C浓度较高,氧化形成的羟基数目较多,而羟基在键合过程中与第一键合层200和第二键合层400内的Si形成硅氧键,从而提高键合界面的键合强度。在一个具体实施方式中,所述第二键合层400与第一键合层200之间的键合力大于1.7J/M2。而现有技术中采用不含C的键合层进行键合,通常键合力小于1.5J/M2
在一个具体实施方式中,所述第一基底100为形成有3D NAND存储结构的基底,而所述第二基底200为形成有外围电路的基底。
在其他具体实施方式中,还可以在基底的两侧表面均形成上述键合层,以实现多层键合。
请参考图5,在另一具体实施方式中,还包括:形成贯穿所述第一键合层200的第一键合垫501;形成贯穿所述第二键合层400的第二键合垫502;在将所述第二键合层400表面与所述第一键合层200表面相对键合固定的同时,将所述第一键合垫501与第二键合垫502相对键合连接。
所述第一键合垫501和第二键合垫502可以分别连接至所述第一器件层102和第二器件层302内的半导体器件以及金属互连层。
所述第一键合垫501的形成方法包括:对所述第一键合层200进行图形化,形成贯穿所述第一键合层200的开口;在所述开口内填充金属材料,并进行平坦化,形成填充满所述开口的第一键合垫501。采用相同的方法在所述第二键合层400内形成所述第二键合垫502。将所述第一键合垫501与第二键合垫502键合连接,可以实现所述第一器件层102和第二器件层302内的半导体器件之间的电连接。
所述第一键合垫501和第二键合垫502的材料可以是Cu、W等金属材料。所述第一键合层200和第二键合层400内均含有C,能够有效阻挡所述第一键合垫501和第二键合垫502的材料在键合界面发生扩散,从而提高所述半导体结构的性能。
上述具体实施方式,在第一基底表面形成第一键合层,所述第一键合层的材料为包含C元素的介质材料,在键合后能够在键合表面具有较强的键合力,并且能够阻挡金属材料在键合界面的扩散,从而提高形成的半导体结构的性能。
上述方法还用于多片基底键合。
请参考图6,在本发明一具体实施方式中,还包括提供第三基底600,在所述第三基底600的相对两侧表面分别形成第三键合层700和第四键合层800;将所述第三键合层700与第一键合层200表面相对键合固定,将所述第四键合层800与第二键合层400表面键合固定,形成三层键合结构。
所述第三键合层700和第四键合层800的材料与形成方法请参照上述具体实施方式中第一键合层200的材料与形成方法,在此不再赘述。
该具体实施方式中,还包括在第三键合层700内形成第三键合垫701,在第四键合层800内形成第四键合垫801,将所述第三键合垫701与第一键合垫501键合连接,将所述第四键合垫801与第二键合垫502键合连接。
在其他具体实施方式中,还可以采用上述方法形成四层以上的键合结构。
需说明的是,在本发明的技术方案中,半导体结构中各个基底内的半导体器件类型并不应局限于所给实施例,除了3D NAND之外,其可以为CMOS电路、CIS电路、TFT电路等等。
本发明的具体实施方式还提供一种半导体结构。
请参考图2,为本发明一具体实施方式的半导体结构的结构示意图。
所述半导体结构,包括:第一基底100;位于所述第一基底100表面的第一键合层200,所述第一键合层200材料为包含C元素的介质材料。
所述第一基底100包括第一半导体衬底101、形成于所述第一半导体衬底101表面的第一器件层102。
所述第一半导体衬底101可以为单晶硅衬底、Ge衬底、SiGe衬底、SOI或GOI等;根据器件的实际需求,可以选择合适的第一半导体衬底101,在此不作限定。该具体实施方式中,所述第一半导体衬底101为单晶硅晶圆。
所述第一器件层102包括形成于所述半导体衬底101上的半导体器件、连接所述半导体器件的金属互连结构、覆盖所述半导体器件以及金属互连结构的介质层等。所述第一器件层102可以为多层或单层结构。在一个具体实施方式中,所述第一器件层102包括介质层以及形成于介质层内的3D NAND结构。
所述第一键合层200的材料为包含C元素的介质材料。在一个具体实施方式中,所述第一键合层200主要包含Si、N和C。在其他具体实施方式中,基于所述第一键合层200的形成工艺以及具体产品的需求,所述第一键合层200内还可以掺杂有Si、N、O、H、P、F等元素中的至少一种。所述第一键合层200的材料可以为掺碳氮化硅、掺碳氮氧化硅、掺氮碳氧化硅等。
通过控制所述第一键合层200的形成工艺参数,可以调整所述第一键合层200内各组分的浓度,对所述第一键合层200与第一器件层102之间的粘附力、所述第一键合层200的介电系数以及与其他键合层进行键合后的键合力进行调整。
所述第一键合层200中的C能够有效提高所述第一键合层200在键合过程中,与其他键合层之间的键合力。C浓度越高,与其他键合层之间进行键合时产生的键合力越大。所述第一键合层200表面处的C浓度越高,与其他键合层进行键合时产生的键合力越大。由于C在所述第一键合层200内会以不稳定的-CH3基团的形式存在,在经过键合之前的自然氧化以及等离子体活化等处理后,-CH3会被氧化成-OH,从而增加羟数目,最终在键合时,提高键合界面Si-O键的数目,从而提高键合强度。
由于不同材料层之间的粘附力与界面两侧的材料组分相关,材料组分越接近,粘附力越强。为了进一步增强所述第一键合层200与所述第一器件层102之间的粘附力,所述第一键合层200内的组分浓度也可以随厚度逐渐变化,使得所述第一键合层200与所述第一器件层102界面两侧的材料组分接近。在一个具体实施方式中,随着第一键合层200厚度的增加,第一键合层200内的C原子浓度随第一键合层200厚度增加而逐渐增大,使得所述第一键合层200表面的C的原子浓度最大。在其他具体实施方式中,所述第一键合层200中各元素在不同厚度位置处的浓度均匀分布,例如第一键合层200中C的原子浓度在各厚度位置处保持一致。
在另一具体实施方式中,所述第一键合层200的密度随厚度增加而逐渐改变,例如自所述第一器件层102表面向上,所述第一键合层200的密度逐渐增大、逐渐减小或者先增大后减小。所述第一键合层200与第一器件层102界面处密度接近。
所述第一键合层200的厚度不能过小,以确保所述第一键合层200与其他键合层进行键合时,所述第一键合层200具有足够的键合厚度。在一个具体实施方式中,所述第一键合层200的厚度大于为了使得所述第一键合层200表面附近具有足够浓度的C元素,在一个具体实施方式中,自所述第一键合层200表面向所述第一键合层200内部一定厚度的表层内的C的原子浓度大于或等于35%。所述表层的厚度可以为/>在一个具体实施方式中,在所述第一键合层200表面向内/>的厚度内,C的原子浓度大于40%。
所述第一键合层200还可以包括两层以上堆叠的子键合层,不同子键合层的元素组分不同,各个子键合层内的组分浓度可以不随厚度变化,也可以随厚度渐变。通过调整个子键合层内的组分浓度,可以对第一键合层200与第一器件层102之间的粘附力、各子键合层界面的粘附力以及第一键合层200的介电系数进行调整。
请参考图4,为本发明另一具体实施方式的半导体结构的示意图。
该具体实施方式中,所述半导体结构还包括:第二基底300,所述第二基底300表面形成有第二键合层400,所述第二键合层400与所述第一键合层200表面相对键合固定。
所述第二基底300包括第二半导体衬底301以及位于所述第二半导体衬底201表面的第二器件层302。所述第二键合层400的材料可以为氧化硅或氮化硅。所述第二键合层400的材料也可以为包含C元素的介质材料,具体请参考上述具体实施方式中的第一键合层200的描述,在此不再赘述。在一个具体实施方式中,所述第二键合层400的材料与上述第一键合层200的材料相同。
所述第二键合层400与所述第一键合层200的表面相对键合固定。由于所述第一键合层200和第二键合层400表面处的C浓度较高,在键合过程中,氧化形成的羟基数目较多,使得在键合界面上具有较多的硅氧键,从而提高键合界面的键合强度。
在一个具体实施方式中,所述第一基底100为形成有3D NAND存储结构的基底,而所述第二基底200为形成有外围电路的基底。
在其他具体实施方式中,所述半导体结构可以包括三个以上的基底,相邻基底之间均通过本发明具体实施方式中的键合层进行键合。
请参考图5,为发明另一具体实施方式的半导体结构的结构示意图。
该具体实施方式中,所述半导体结构还包括:贯穿所述第一键合层200的第一键合垫501;贯穿所述第二键合层400的第二键合垫502;所述第二键合层400表面与所述第一键合层200表面相对键合固定且所述第一键合垫501与第二键合垫502相对键合连接。
所述第一键合垫501和第二键合垫502可以分别连接至所述第一器件层102和第二器件层302内的半导体器件以及金属互连层。
所述第一键合垫501和第二键合垫502的材料可以是Cu、W等金属材料。所述第一键合层200和第二键合层400内含有C,并且键合界面处C浓度较高,能够有效阻挡所述第一键合垫501和第二键合垫502的材料在键合界面发生扩散,从而提高所述半导体结构的性能。
在一个具体实施方式中,所述第一基底100为形成有3D NAND存储结构的基底,而所述第二基底200为形成有外围电路的基底。
请参考图6,为本发明另一具体实施方式的半导体结构示意图。
该具体实施方式中,所述半导体结构还包括第三基底600,位于所述第三基底600的一侧表面的第三键合层700,位于第三基底600的另一侧相对表面的第四键合层800;所述第三键合层700与第一键合层200表面相对键合固定,所述第四键合层80与第二键合层400表面键合固定,构成三层键合结构。
所述第三键合层700和第四键合层800的材料和结构,请参考上述具体实施方式中,第一键合层200的材料和结构,在此不再赘述。
该具体实施方式中,所述半导体结构还包括贯穿所述第三键合层700的第三键合垫701,贯穿所述第四键合层800的第四键合垫801,所述第三键合垫701与第一键合垫501键合连接,所述第四键合垫801与第二键合垫502键合连接。
在其他具体实施方式中,还可以采用上述方法形成四层以上的键合结构。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。

Claims (14)

1.一种半导体结构,其特征在于,包括:
第一基底;
位于所述第一基底表面的第一键合层,所述第一键合层的材料为包含Si、N和C元素的介质材料,所述第一键合层内各位置处均包含Si元素和N元素,所述第一键合层与所述第一基底界面两侧的材料组分基本相同,所述第一键合层中C的原子浓度随第一键合层厚度增加而逐渐增大,所述第一键合层背向所述第一基底的表层的C原子浓度大于或等于35%。
2.根据权利要求1所述的半导体结构,其特征在于,所述表层厚度为
3.根据权利要求1所述的半导体结构,其特征在于,还包括:第二基底,所述第二基底表面形成有第二键合层,所述第二键合层与所述第一键合层表面相对键合固定。
4.根据权利要求3所述的半导体结构,其特征在于,所述第二键合层的材料为包含C元素的介质材料,所述第二键合层背向所述第二基底的表层的C原子浓度大于或等于35%。
5.根据权利要求3所述的半导体结构,其特征在于,所述第二键合层的材料与所述第一键合层的材料相同。
6.根据权利要求3所述的半导体结构,其特征在于,还包括:贯穿所述第一键合层的第一键合垫;贯穿所述第二键合层的第二键合垫;所述第一键合垫与第二键合垫相对键合连接。
7.一种半导体结构,其特征在于,包括:
第一基底;
位于所述第一基底表面的键合叠层,所述键合叠层包括键合的两层键合层,所述键合叠层的材料为包含Si、N、C和O的介质材料,所述键合叠层内各位置处均包含Si元素和N元素,所述键合叠层与所述第一基底界面两侧的材料组分基本相同,所述键合叠层中C的原子浓度随厚度增加而逐渐增大,所述键合层靠近键合面的表层的C原子浓度大于或等于35%。
8.如权利要求7所述的半导体结构,其特征在于,所述键合叠层为两层具有CH3键的键合层分别经氧化后键合而成。
9.如权利要求7所述的半导体结构,其特征在于,还包括:第二基底,位于所述键合叠层背向所述第一基底的一侧。
10.如权利要求7所述的半导体结构,其特征在于,还包括:贯穿所述键合层的键合垫;两个所述键合层内的键合垫相对键合连接。
11.一种半导体结构的形成方法,其特征在于,包括:
提供第一基底;
在所述第一基底表面形成第一键合层,所述第一键合层的材料为包含Si、N和C元素的介质材料且含有CH3键,所述第一键合层内各位置处均包含Si元素和N元素,所述第一键合层与所述第一基底界面两侧的材料组分基本相同,所述第一键合层中C的原子浓度随第一键合层厚度增加而逐渐增大;
提供第二基底;
在所述第二基底表面形成第二键合层,所述第二键合层的材料与所述第一键合层的材料相同;
使所述第一键合层、第二键合层的表层氧化,以使CH3键被氧化为OH键;
将所述第一键合层和第二键合层相对键合连接。
12.根据权利要求11所述的半导体结构的形成方法,其特征在于,所述第一键合层和第二键合层的表层内的C原子浓度大于或等于35%。
13.根据权利要求11所述的半导体结构的形成方法,其特征在于,采用等离子体增强化学气相沉积工艺形成所述第一键合层。
14.根据权利要求11所述的半导体结构的形成方法,其特征在于,所述表层厚度为
CN201880096616.XA 2018-06-29 2018-06-29 半导体结构及其形成方法 Active CN112567511B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311008252.4A CN117012754A (zh) 2018-06-29 2018-06-29 半导体结构及其形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/093690 WO2020000376A1 (zh) 2018-06-29 2018-06-29 半导体结构及其形成方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202311008252.4A Division CN117012754A (zh) 2018-06-29 2018-06-29 半导体结构及其形成方法

Publications (2)

Publication Number Publication Date
CN112567511A CN112567511A (zh) 2021-03-26
CN112567511B true CN112567511B (zh) 2023-08-25

Family

ID=68984585

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201880096616.XA Active CN112567511B (zh) 2018-06-29 2018-06-29 半导体结构及其形成方法
CN202311008252.4A Pending CN117012754A (zh) 2018-06-29 2018-06-29 半导体结构及其形成方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202311008252.4A Pending CN117012754A (zh) 2018-06-29 2018-06-29 半导体结构及其形成方法

Country Status (4)

Country Link
US (3) US20200006285A1 (zh)
CN (2) CN112567511B (zh)
TW (1) TWI712146B (zh)
WO (1) WO2020000376A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112542378B (zh) * 2020-12-01 2024-03-26 武汉新芯集成电路制造有限公司 半导体器件的制作方法及半导体器件

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5526768A (en) * 1994-02-03 1996-06-18 Harris Corporation Method for providing a silicon and diamond substrate having a carbon to silicon transition layer and apparatus thereof
CN1767721A (zh) * 2004-10-29 2006-05-03 同和矿业株式会社 金属包覆基板及其制造方法
CN1819180A (zh) * 2005-01-21 2006-08-16 国际商业机器公司 介质材料及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350670B1 (en) * 1999-12-17 2002-02-26 Intel Corporation Method for making a semiconductor device having a carbon doped oxide insulating layer
US6953984B2 (en) * 2000-06-23 2005-10-11 International Business Machines Corporation Hydrogenated oxidized silicon carbon material
US6683002B1 (en) * 2000-08-10 2004-01-27 Chartered Semiconductor Manufacturing Ltd. Method to create a copper diffusion deterrent interface
US7125488B2 (en) * 2004-02-12 2006-10-24 Varian, Inc. Polar-modified bonded phase materials for chromatographic separations
WO2013066977A1 (en) * 2011-10-31 2013-05-10 Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University Methods for wafer bonding and for nucleating bonding nanophases using wet and steam pressurization
US9443796B2 (en) * 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
KR102402545B1 (ko) * 2014-02-19 2022-05-27 삼성전자주식회사 배선 구조 및 이를 적용한 전자소자
TWI721077B (zh) * 2015-12-28 2021-03-11 日商日立造船股份有限公司 奈米碳管複合材料及奈米碳管複合材料的製造方法
FR3051596B1 (fr) * 2016-05-17 2022-11-18 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant
US10692826B2 (en) * 2017-09-27 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method for forming the same
US10283493B1 (en) * 2018-01-17 2019-05-07 Sandisk Technologies Llc Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5526768A (en) * 1994-02-03 1996-06-18 Harris Corporation Method for providing a silicon and diamond substrate having a carbon to silicon transition layer and apparatus thereof
CN1767721A (zh) * 2004-10-29 2006-05-03 同和矿业株式会社 金属包覆基板及其制造方法
CN1819180A (zh) * 2005-01-21 2006-08-16 国际商业机器公司 介质材料及其制造方法

Also Published As

Publication number Publication date
CN112567511A (zh) 2021-03-26
TWI712146B (zh) 2020-12-01
US20220020725A1 (en) 2022-01-20
US20220216178A1 (en) 2022-07-07
TW202002223A (zh) 2020-01-01
WO2020000376A1 (zh) 2020-01-02
US20200006285A1 (en) 2020-01-02
CN117012754A (zh) 2023-11-07

Similar Documents

Publication Publication Date Title
CN112567495B (zh) 半导体结构及其形成方法
KR102609290B1 (ko) 상호연결부를 위한 확산 배리어 칼라
WO2010098151A1 (ja) 半導体装置およびその製造方法
TWI232539B (en) Method for forming intermetal dielectric
US20230005873A1 (en) Semiconductor structure and method of forming the same
CN112567506B (zh) 半导体结构及其形成方法
CN112567511B (zh) 半导体结构及其形成方法
CN112567512B (zh) 半导体结构及其形成方法
JP3948035B2 (ja) 張り合わせsoi基板の作成方法
TW440949B (en) Method for forming low-k material
JPH0499031A (ja) 半導体集積回路装置の製造方法
JPH07142578A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant