SG11201806851RA - Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof - Google Patents

Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof

Info

Publication number
SG11201806851RA
SG11201806851RA SG11201806851RA SG11201806851RA SG11201806851RA SG 11201806851R A SG11201806851R A SG 11201806851RA SG 11201806851R A SG11201806851R A SG 11201806851RA SG 11201806851R A SG11201806851R A SG 11201806851RA SG 11201806851R A SG11201806851R A SG 11201806851RA
Authority
SG
Singapore
Prior art keywords
international
semiconductor
pct
insulator structure
low temperature
Prior art date
Application number
SG11201806851RA
Other languages
English (en)
Inventor
Sasha Joseph Kweskin
Original Assignee
Globalwafers Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalwafers Co Ltd filed Critical Globalwafers Co Ltd
Publication of SG11201806851RA publication Critical patent/SG11201806851RA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/126—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates characterised by the composition of the bonding layer, e.g. dopant concentration or stoichiometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/68—Organic materials, e.g. photoresists
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Thin Film Transistor (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Laminated Bodies (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
SG11201806851RA 2016-03-07 2017-03-03 Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof SG11201806851RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662304376P 2016-03-07 2016-03-07
PCT/US2017/020619 WO2017155805A1 (en) 2016-03-07 2017-03-03 Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof

Publications (1)

Publication Number Publication Date
SG11201806851RA true SG11201806851RA (en) 2018-09-27

Family

ID=58387889

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201806851RA SG11201806851RA (en) 2016-03-07 2017-03-03 Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof

Country Status (5)

Country Link
US (1) US10593748B2 (https=)
EP (2) EP3758050A1 (https=)
JP (2) JP7002456B2 (https=)
SG (1) SG11201806851RA (https=)
WO (1) WO2017155805A1 (https=)

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US11114332B2 (en) * 2016-03-07 2021-09-07 Globalwafers Co., Ltd. Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof
US20180019169A1 (en) * 2016-07-12 2018-01-18 QMAT, Inc. Backing substrate stabilizing donor substrate for implant or reclamation
CN110085550A (zh) * 2018-01-26 2019-08-02 沈阳硅基科技有限公司 一种半导体产品用绝缘层结构及其制备方法
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Also Published As

Publication number Publication date
EP3427293A1 (en) 2019-01-16
JP2019513294A (ja) 2019-05-23
US20190035881A1 (en) 2019-01-31
JP7002456B2 (ja) 2022-01-20
JP2021061413A (ja) 2021-04-15
EP3758050A1 (en) 2020-12-30
US10593748B2 (en) 2020-03-17
WO2017155805A1 (en) 2017-09-14
EP3427293B1 (en) 2021-05-05
JP7071486B2 (ja) 2022-05-19

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