SG11201609300VA - Method for fabricating a semiconductor device including fin relaxation, and related structures - Google Patents

Method for fabricating a semiconductor device including fin relaxation, and related structures

Info

Publication number
SG11201609300VA
SG11201609300VA SG11201609300VA SG11201609300VA SG11201609300VA SG 11201609300V A SG11201609300V A SG 11201609300VA SG 11201609300V A SG11201609300V A SG 11201609300VA SG 11201609300V A SG11201609300V A SG 11201609300VA SG 11201609300V A SG11201609300V A SG 11201609300VA
Authority
SG
Singapore
Prior art keywords
fabricating
semiconductor device
device including
related structures
including fin
Prior art date
Application number
SG11201609300VA
Other languages
English (en)
Inventor
Frederic Allibert
Pierre Morin
Original Assignee
Soitec Silicon On Insulator
St Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, St Microelectronics Inc filed Critical Soitec Silicon On Insulator
Publication of SG11201609300VA publication Critical patent/SG11201609300VA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02614—Transformation of metal, e.g. oxidation, nitridation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
SG11201609300VA 2014-05-08 2015-04-28 Method for fabricating a semiconductor device including fin relaxation, and related structures SG11201609300VA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/272,660 US9620626B2 (en) 2014-05-08 2014-05-08 Method for fabricating a semiconductor device including fin relaxation, and related structures
PCT/US2015/027974 WO2015171362A1 (en) 2014-05-08 2015-04-28 Method for fabricating a semiconductor device including fin relaxation, and related structures

Publications (1)

Publication Number Publication Date
SG11201609300VA true SG11201609300VA (en) 2016-12-29

Family

ID=53053146

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201609300VA SG11201609300VA (en) 2014-05-08 2015-04-28 Method for fabricating a semiconductor device including fin relaxation, and related structures

Country Status (7)

Country Link
US (1) US9620626B2 (de)
EP (1) EP3140858B1 (de)
JP (1) JP6618528B2 (de)
KR (1) KR101929108B1 (de)
CN (1) CN106537554B (de)
SG (1) SG11201609300VA (de)
WO (1) WO2015171362A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10475886B2 (en) 2014-12-16 2019-11-12 International Business Machines Corporation Modified fin cut after epitaxial growth
US9564373B2 (en) * 2015-02-27 2017-02-07 International Business Machines Corporation Forming a CMOS with dual strained channels
US9607901B2 (en) * 2015-05-06 2017-03-28 Stmicroelectronics, Inc. Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FINFET technology
US9589811B2 (en) * 2015-06-24 2017-03-07 Varian Semiconductor Equipment Associates, Inc. FinFET spacer etch with no fin recess and no gate-spacer pull-down
US9728642B2 (en) * 2015-11-04 2017-08-08 International Business Machines Corporation Retaining strain in finFET devices
US9483592B1 (en) * 2015-12-07 2016-11-01 International Business Machines Corporation Maintaining stress in a layout design of an integrated circuit having fin-type field-effect transistor devices
US20180122908A1 (en) * 2016-10-31 2018-05-03 International Business Machines Corporation Silicon germanium alloy fin with multiple threshold voltages

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020089032A1 (en) 1999-08-23 2002-07-11 Feng-Yi Huang Processing method for forming dislocation-free silicon-on-insulator substrate prepared by implantation of oxygen
US7018909B2 (en) 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
JP3825768B2 (ja) * 2003-08-27 2006-09-27 株式会社東芝 電界効果トランジスタ
JP4239203B2 (ja) * 2005-05-31 2009-03-18 株式会社東芝 半導体装置とその製造方法
JP5394632B2 (ja) * 2007-11-19 2014-01-22 エア・ウォーター株式会社 単結晶ＳｉＣ基板の製造方法
US7524740B1 (en) 2008-04-24 2009-04-28 International Business Machines Corporation Localized strain relaxation for strained Si directly on insulator
EP2151852B1 (de) 2008-08-06 2020-01-15 Soitec Relaxation und Übertragung von Spannungsschichten
US7993999B2 (en) * 2009-11-09 2011-08-09 International Business Machines Corporation High-K/metal gate CMOS finFET with improved pFET threshold voltage
US8169025B2 (en) 2010-01-19 2012-05-01 International Business Machines Corporation Strained CMOS device, circuit and method of fabrication
US8723268B2 (en) 2012-06-13 2014-05-13 Synopsys, Inc. N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch
US8946063B2 (en) 2012-11-30 2015-02-03 International Business Machines Corporation Semiconductor device having SSOI substrate with relaxed tensile stress
US8853008B1 (en) * 2013-03-14 2014-10-07 Intermolecular, Inc. Counter-doped low-power FinFET

Also Published As

Publication number Publication date
JP6618528B2 (ja) 2019-12-11
US20150325686A1 (en) 2015-11-12
WO2015171362A1 (en) 2015-11-12
EP3140858A1 (de) 2017-03-15
CN106537554A (zh) 2017-03-22
EP3140858B1 (de) 2023-03-15
JP2017517901A (ja) 2017-06-29
US9620626B2 (en) 2017-04-11
KR101929108B1 (ko) 2018-12-13
KR20170015319A (ko) 2017-02-08
CN106537554B (zh) 2019-06-21

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