HK1232338A1 - 包括加厚的再分布層的半導體器件及其製造方法 - Google Patents

包括加厚的再分布層的半導體器件及其製造方法

Info

Publication number
HK1232338A1
HK1232338A1 HK17105684.1A HK17105684A HK1232338A1 HK 1232338 A1 HK1232338 A1 HK 1232338A1 HK 17105684 A HK17105684 A HK 17105684A HK 1232338 A1 HK1232338 A1 HK 1232338A1
Authority
HK
Hong Kong
Prior art keywords
thickened
semiconductor device
redistribution layers
redistribution
layers
Prior art date
Application number
HK17105684.1A
Other languages
English (en)
Inventor
Christopher M Scanlan
Craig Bishop
Original Assignee
Deca Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/US2015/019538 external-priority patent/WO2015138359A1/en
Application filed by Deca Technologies Inc filed Critical Deca Technologies Inc
Publication of HK1232338A1 publication Critical patent/HK1232338A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
HK17105684.1A 2014-03-10 2017-06-08 包括加厚的再分布層的半導體器件及其製造方法 HK1232338A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201461950743P 2014-03-10 2014-03-10
PCT/US2015/019538 WO2015138359A1 (en) 2014-03-10 2015-03-09 Semiconductor device and method comprising thickened redistribution layers

Publications (1)

Publication Number Publication Date
HK1232338A1 true HK1232338A1 (zh) 2018-01-05

Family

ID=57528766

Family Applications (1)

Application Number Title Priority Date Filing Date
HK17105684.1A HK1232338A1 (zh) 2014-03-10 2017-06-08 包括加厚的再分布層的半導體器件及其製造方法

Country Status (2)

Country Link
CN (1) CN106233460A (zh)
HK (1) HK1232338A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275240A (zh) * 2017-07-03 2017-10-20 京东方科技集团股份有限公司 一种芯片封装方法及芯片封装结构
CN107564822A (zh) * 2017-08-28 2018-01-09 华进半导体封装先导技术研发中心有限公司 一种集成芯片的封装方法及系统级封装的集成芯片
US10910287B2 (en) 2018-02-28 2021-02-02 Stmicroelectronics Pte Ltd Semiconductor package with protected sidewall and method of forming the same
TWI657545B (zh) * 2018-03-12 2019-04-21 頎邦科技股份有限公司 半導體封裝結構及其線路基板
CN111490004A (zh) * 2019-01-28 2020-08-04 中芯长电半导体（江阴）有限公司 重新布线层的制备方法及半导体结构
CN110120355A (zh) * 2019-05-27 2019-08-13 广东工业大学 一种降低扇出型封装翘曲的方法
CN110739287B (zh) * 2019-12-06 2021-06-15 江苏感测通电子科技有限公司 一种集成芯片封装结构
CN111696879B (zh) * 2020-06-15 2021-08-31 西安微电子技术研究所 一种基于转接基板的裸芯片kgd筛选方法
WO2022022419A1 (zh) * 2020-07-31 2022-02-03 华为技术有限公司 电路板组件及其加工方法、电子设备
CN112134007B (zh) * 2020-08-12 2022-07-19 光臻精密制造(苏州)有限公司 选择性增厚、差分蚀刻制备5g天线振子导电图形的方法
KR20220033177A (ko) * 2020-09-09 2022-03-16 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
CN113223974A (zh) * 2021-05-07 2021-08-06 成都奕斯伟系统技术有限公司 一种半导体封装结构制作方法及半导体封装结构

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6790759B1 (en) * 2003-07-31 2004-09-14 Freescale Semiconductor, Inc. Semiconductor device with strain relieving bump design
CN101425492A (zh) * 2007-10-30 2009-05-06 育霈科技股份有限公司 具积层的晶圆级封装结构
TWI528514B (zh) * 2009-08-20 2016-04-01 精材科技股份有限公司 晶片封裝體及其製造方法
US8922021B2 (en) * 2011-12-30 2014-12-30 Deca Technologies Inc. Die up fully molded fan-out wafer level packaging
US8653674B1 (en) * 2011-09-15 2014-02-18 Amkor Technology, Inc. Electronic component package fabrication method and structure

Also Published As

Publication number Publication date
CN106233460A (zh) 2016-12-14

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