SG10202003846SA - Three-Dimensional Semiconductor Devices - Google Patents
Three-Dimensional Semiconductor DevicesInfo
- Publication number
- SG10202003846SA SG10202003846SA SG10202003846SA SG10202003846SA SG10202003846SA SG 10202003846S A SG10202003846S A SG 10202003846SA SG 10202003846S A SG10202003846S A SG 10202003846SA SG 10202003846S A SG10202003846S A SG 10202003846SA SG 10202003846S A SG10202003846S A SG 10202003846SA
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor devices
- dimensional semiconductor
- dimensional
- devices
- semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1022—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including bipolar transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020190111467A KR20210030533A (ko) | 2019-09-09 | 2019-09-09 | 3차원 반도체 장치 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10202003846SA true SG10202003846SA (en) | 2021-04-29 |
Family
ID=74833669
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10202003846SA SG10202003846SA (en) | 2019-09-09 | 2020-04-27 | Three-Dimensional Semiconductor Devices |
Country Status (4)
Country | Link |
---|---|
US (1) | US11367735B2 (ko) |
KR (1) | KR20210030533A (ko) |
CN (1) | CN112466876A (ko) |
SG (1) | SG10202003846SA (ko) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210061166A (ko) * | 2019-11-19 | 2021-05-27 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
JP2022131445A (ja) * | 2021-02-26 | 2022-09-07 | キオクシア株式会社 | 半導体装置及びその製造方法 |
CN115803882A (zh) | 2021-06-30 | 2023-03-14 | 长江存储科技有限责任公司 | 三维存储器装置及其形成方法 |
WO2023272592A1 (en) | 2021-06-30 | 2023-01-05 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and methods for forming the same |
WO2023272638A1 (en) * | 2021-06-30 | 2023-01-05 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and methods for forming the same |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6333208B1 (en) | 1999-07-13 | 2001-12-25 | Li Chiung-Tung | Robust manufacturing method for making a III-V compound semiconductor device by misaligned wafer bonding |
US7312485B2 (en) * | 2000-11-29 | 2007-12-25 | Intel Corporation | CMOS fabrication process utilizing special transistor orientation |
US8058137B1 (en) | 2009-04-14 | 2011-11-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
KR102150969B1 (ko) | 2013-12-05 | 2020-10-26 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
KR20150139223A (ko) | 2014-06-03 | 2015-12-11 | 삼성전자주식회사 | 반도체 소자 |
JP6203152B2 (ja) | 2014-09-12 | 2017-09-27 | 東芝メモリ株式会社 | 半導体記憶装置の製造方法 |
KR102609516B1 (ko) | 2016-05-04 | 2023-12-05 | 삼성전자주식회사 | 반도체 장치 |
JP6677076B2 (ja) | 2016-05-24 | 2020-04-08 | Tdk株式会社 | 積層膜、電子デバイス基板、電子デバイス及び積層膜の製造方法 |
CN110121779B (zh) | 2017-08-21 | 2020-09-25 | 长江存储科技有限责任公司 | 三维存储器器件及用于形成其的方法 |
US10665580B1 (en) * | 2019-01-08 | 2020-05-26 | Sandisk Technologies Llc | Bonded structure including a performance-optimized support chip and a stress-optimized three-dimensional memory chip and method for making the same |
-
2019
- 2019-09-09 KR KR1020190111467A patent/KR20210030533A/ko not_active Application Discontinuation
-
2020
- 2020-03-31 US US16/835,484 patent/US11367735B2/en active Active
- 2020-04-27 SG SG10202003846SA patent/SG10202003846SA/en unknown
- 2020-05-14 CN CN202010406631.9A patent/CN112466876A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
US20210074717A1 (en) | 2021-03-11 |
US11367735B2 (en) | 2022-06-21 |
KR20210030533A (ko) | 2021-03-18 |
CN112466876A (zh) | 2021-03-09 |
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