SE9703344D0 - Flerlagerskretskort - Google Patents

Flerlagerskretskort

Info

Publication number
SE9703344D0
SE9703344D0 SE9703344A SE9703344A SE9703344D0 SE 9703344 D0 SE9703344 D0 SE 9703344D0 SE 9703344 A SE9703344 A SE 9703344A SE 9703344 A SE9703344 A SE 9703344A SE 9703344 D0 SE9703344 D0 SE 9703344D0
Authority
SE
Sweden
Prior art keywords
supporting layer
supporting
melting point
layers
new
Prior art date
Application number
SE9703344A
Other languages
English (en)
Other versions
SE510487C2 (sv
SE9703344L (sv
Inventor
Leif Bergstedt
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9703344A priority Critical patent/SE510487C2/sv
Publication of SE9703344D0 publication Critical patent/SE9703344D0/sv
Priority to DE69833495T priority patent/DE69833495T2/de
Priority to AU91944/98A priority patent/AU9194498A/en
Priority to PCT/SE1998/001633 priority patent/WO1999014994A1/en
Priority to EP98944395A priority patent/EP1025749B1/en
Priority to US09/154,503 priority patent/US6249962B1/en
Publication of SE9703344L publication Critical patent/SE9703344L/sv
Publication of SE510487C2 publication Critical patent/SE510487C2/sv
Priority to US09/793,188 priority patent/US6717063B2/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H05K3/4655—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676—Single layer compositions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49163—Manufacturing circuit on or in base with sintering of base
SE9703344A 1997-09-17 1997-09-17 Flerlagerskretskort SE510487C2 (sv)

Priority Applications (7)

Application Number Priority Date Filing Date Title
SE9703344A SE510487C2 (sv) 1997-09-17 1997-09-17 Flerlagerskretskort
DE69833495T DE69833495T2 (de) 1997-09-17 1998-09-15 Herstellungsvefahren für eine mehrschichtige leiterplatte
AU91944/98A AU9194498A (en) 1997-09-17 1998-09-15 Multi-layer circuit board
PCT/SE1998/001633 WO1999014994A1 (en) 1997-09-17 1998-09-15 Multi-layer circuit board
EP98944395A EP1025749B1 (en) 1997-09-17 1998-09-15 Process for manufacturing a multi-layer circuit board
US09/154,503 US6249962B1 (en) 1997-09-17 1998-09-17 Process for manufacturing a multi-layer circuit board with supporting layers of different materials
US09/793,188 US6717063B2 (en) 1997-09-17 2001-02-26 Multi-layer circuit board with supporting layers of different materials

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9703344A SE510487C2 (sv) 1997-09-17 1997-09-17 Flerlagerskretskort

Publications (3)

Publication Number Publication Date
SE9703344D0 true SE9703344D0 (sv) 1997-09-17
SE9703344L SE9703344L (sv) 1999-03-18
SE510487C2 SE510487C2 (sv) 1999-05-31

Family

ID=20408269

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9703344A SE510487C2 (sv) 1997-09-17 1997-09-17 Flerlagerskretskort

Country Status (6)

Country Link
US (2) US6249962B1 (sv)
EP (1) EP1025749B1 (sv)
AU (1) AU9194498A (sv)
DE (1) DE69833495T2 (sv)
SE (1) SE510487C2 (sv)
WO (1) WO1999014994A1 (sv)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345549A (ja) * 2000-06-01 2001-12-14 Fujitsu Ltd 実装用基板の製造方法及び部品実装方法並びに実装用基板製造装置
US7506438B1 (en) * 2000-11-14 2009-03-24 Freescale Semiconductor, Inc. Low profile integrated module interconnects and method of fabrication
AT412681B (de) * 2002-04-22 2005-05-25 Hueck Folien Gmbh Substrate mit unsichtbaren elektrisch leitfähigen schichten
US6900708B2 (en) * 2002-06-26 2005-05-31 Georgia Tech Research Corporation Integrated passive devices fabricated utilizing multi-layer, organic laminates
US6987307B2 (en) * 2002-06-26 2006-01-17 Georgia Tech Research Corporation Stand-alone organic-based passive devices
US7260890B2 (en) 2002-06-26 2007-08-28 Georgia Tech Research Corporation Methods for fabricating three-dimensional all organic interconnect structures
US7489914B2 (en) * 2003-03-28 2009-02-10 Georgia Tech Research Corporation Multi-band RF transceiver with passive reuse in organic substrates
US8345433B2 (en) * 2004-07-08 2013-01-01 Avx Corporation Heterogeneous organic laminate stack ups for high frequency applications
US7439840B2 (en) 2006-06-27 2008-10-21 Jacket Micro Devices, Inc. Methods and apparatuses for high-performing multi-layer inductors
US7808434B2 (en) * 2006-08-09 2010-10-05 Avx Corporation Systems and methods for integrated antennae structures in multilayer organic-based printed circuit devices
US7989895B2 (en) 2006-11-15 2011-08-02 Avx Corporation Integration using package stacking with multi-layer organic substrates

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4180608A (en) * 1977-01-07 1979-12-25 Del Joseph A Process for making multi-layer printed circuit boards, and the article resulting therefrom
JPH074822B2 (ja) 1986-08-15 1995-01-25 松下電工株式会社 多層プリント配線板の製法
JP2517726B2 (ja) 1987-07-22 1996-07-24 ソニー株式会社 多層配線基板の製造方法
US4806188A (en) * 1988-03-04 1989-02-21 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits
JPH02237197A (ja) * 1989-03-10 1990-09-19 Hitachi Ltd 多層回路基板及びその製造方法並びにその用途
JPH0632670A (ja) 1992-07-16 1994-02-08 Nippon Cement Co Ltd セラミックスと金属の接合用ロウ材及びその接合方法
US5384690A (en) * 1993-07-27 1995-01-24 International Business Machines Corporation Flex laminate package for a parallel processor
JPH07249869A (ja) 1994-03-08 1995-09-26 Sumitomo Metal Mining Co Ltd ガラスセラミックス多層回路板及びその製造方法
US5434751A (en) * 1994-04-11 1995-07-18 Martin Marietta Corporation Reworkable high density interconnect structure incorporating a release layer
US5449427A (en) * 1994-05-23 1995-09-12 General Electric Company Processing low dielectric constant materials for high speed electronics
US5719354A (en) * 1994-09-16 1998-02-17 Hoechst Celanese Corp. Monolithic LCP polymer microelectronic wiring modules
EP0768334B1 (en) * 1995-10-16 2004-02-18 Sumitomo Chemical Company Limited Prepreg, process for producing the same and printed circuit substrate using the same
US5993945A (en) * 1996-05-30 1999-11-30 International Business Machines Corporation Process for high resolution photoimageable dielectric
US5679444A (en) * 1996-07-15 1997-10-21 International Business Machines Corporation Method for producing multi-layer circuit board and resulting article of manufacture

Also Published As

Publication number Publication date
DE69833495D1 (de) 2006-04-20
US20010016980A1 (en) 2001-08-30
SE510487C2 (sv) 1999-05-31
AU9194498A (en) 1999-04-05
WO1999014994A1 (en) 1999-03-25
DE69833495T2 (de) 2006-09-28
SE9703344L (sv) 1999-03-18
US6249962B1 (en) 2001-06-26
US6717063B2 (en) 2004-04-06
EP1025749A1 (en) 2000-08-09
EP1025749B1 (en) 2006-02-15

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NUG Patent has lapsed