SE9101325L - Foerfarande foer att oeka databehandlingshastigheten i datasystem - Google Patents

Foerfarande foer att oeka databehandlingshastigheten i datasystem

Info

Publication number
SE9101325L
SE9101325L SE9101325A SE9101325A SE9101325L SE 9101325 L SE9101325 L SE 9101325L SE 9101325 A SE9101325 A SE 9101325A SE 9101325 A SE9101325 A SE 9101325A SE 9101325 L SE9101325 L SE 9101325L
Authority
SE
Sweden
Prior art keywords
cache
processor
addresses
stream
pct
Prior art date
Application number
SE9101325A
Other languages
English (en)
Other versions
SE469402B (sv
SE9101325D0 (sv
Inventor
E Hagersten
Original Assignee
Swedish Inst Of Computer Scien
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Swedish Inst Of Computer Scien filed Critical Swedish Inst Of Computer Scien
Priority to SE9101325A priority Critical patent/SE469402B/sv
Publication of SE9101325D0 publication Critical patent/SE9101325D0/sv
Priority to JP4509557A priority patent/JPH06510611A/ja
Priority to US08/140,097 priority patent/US5802566A/en
Priority to AT92910069T priority patent/ATE176534T1/de
Priority to KR1019930703312A priority patent/KR100277818B1/ko
Priority to EP92910069A priority patent/EP0582635B1/en
Priority to PCT/SE1992/000282 priority patent/WO1992020027A1/en
Priority to DE69228380T priority patent/DE69228380T2/de
Publication of SE9101325L publication Critical patent/SE9101325L/sv
Publication of SE469402B publication Critical patent/SE469402B/sv
Priority to US09/144,677 priority patent/US6078996A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
  • Communication Control (AREA)
SE9101325A 1991-05-02 1991-05-02 Foerfarande foer att haemta data till ett cache-minne SE469402B (sv)

Priority Applications (9)

Application Number Priority Date Filing Date Title
SE9101325A SE469402B (sv) 1991-05-02 1991-05-02 Foerfarande foer att haemta data till ett cache-minne
DE69228380T DE69228380T2 (de) 1991-05-02 1992-04-29 Verfahren zur erhöhung der datenverarbeitungsgeschwindigkeit in einem rechnersystem
KR1019930703312A KR100277818B1 (ko) 1991-05-02 1992-04-29 컴퓨터 시스템의 데이터 처리 속도를 증가시키는 방법
US08/140,097 US5802566A (en) 1991-05-02 1992-04-29 Method and system for predicting addresses and prefetching data into a cache memory
AT92910069T ATE176534T1 (de) 1991-05-02 1992-04-29 Verfahren zur erhöhung der datenverarbeitungsgeschwindigkeit in einem rechnersystem
JP4509557A JPH06510611A (ja) 1991-05-02 1992-04-29 コンピュータシステムにおいてデータ処理速度を向上させる方法
EP92910069A EP0582635B1 (en) 1991-05-02 1992-04-29 Method for increasing the speed of data processing in a computer system
PCT/SE1992/000282 WO1992020027A1 (en) 1991-05-02 1992-04-29 Method for increasing the speed of data processing in a computer system
US09/144,677 US6078996A (en) 1991-05-02 1998-08-31 Method for increasing the speed of data processing in a computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9101325A SE469402B (sv) 1991-05-02 1991-05-02 Foerfarande foer att haemta data till ett cache-minne

Publications (3)

Publication Number Publication Date
SE9101325D0 SE9101325D0 (sv) 1991-05-02
SE9101325L true SE9101325L (sv) 1992-11-03
SE469402B SE469402B (sv) 1993-06-28

Family

ID=20382624

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9101325A SE469402B (sv) 1991-05-02 1991-05-02 Foerfarande foer att haemta data till ett cache-minne

Country Status (8)

Country Link
US (2) US5802566A (sv)
EP (1) EP0582635B1 (sv)
JP (1) JPH06510611A (sv)
KR (1) KR100277818B1 (sv)
AT (1) ATE176534T1 (sv)
DE (1) DE69228380T2 (sv)
SE (1) SE469402B (sv)
WO (1) WO1992020027A1 (sv)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5588131A (en) * 1994-03-09 1996-12-24 Sun Microsystems, Inc. System and method for a snooping and snarfing cache in a multiprocessor computer system
US5809529A (en) * 1995-08-23 1998-09-15 International Business Machines Corporation Prefetching of committed instructions from a memory to an instruction cache
US5664147A (en) * 1995-08-24 1997-09-02 International Business Machines Corp. System and method that progressively prefetches additional lines to a distributed stream buffer as the sequentiality of the memory accessing is demonstrated
US5737565A (en) * 1995-08-24 1998-04-07 International Business Machines Corporation System and method for diallocating stream from a stream buffer
US6029226A (en) * 1996-09-30 2000-02-22 Lsi Logic Corporation Method and apparatus having automated write data transfer with optional skip by processing two write commands as a single write command
DE19747275A1 (de) * 1997-10-25 1999-04-29 Philips Patentverwaltung Mobilfunkgerät mit einem Steuersignalgenerator
JP3071752B2 (ja) 1998-03-24 2000-07-31 三菱電機株式会社 ブリッジ方法、バスブリッジ及びマルチプロセッサシステム
US6430680B1 (en) * 1998-03-31 2002-08-06 International Business Machines Corporation Processor and method of prefetching data based upon a detected stride
TW501011B (en) * 1998-05-08 2002-09-01 Koninkl Philips Electronics Nv Data processing circuit with cache memory
JP3439350B2 (ja) * 1998-10-02 2003-08-25 Ｎｅｃエレクトロニクス株式会社 キャッシュ・メモリ制御方法及びキャッシュ・メモリ制御装置
US6370614B1 (en) 1999-01-26 2002-04-09 Motive Power, Inc. I/O cache with user configurable preload
US6463509B1 (en) * 1999-01-26 2002-10-08 Motive Power, Inc. Preloading data in a cache memory according to user-specified preload criteria
US6449697B1 (en) 1999-04-23 2002-09-10 International Business Machines Corporation Prestaging data into cache in preparation for data transfer operations
US6622212B1 (en) * 1999-05-24 2003-09-16 Intel Corp. Adaptive prefetch of I/O data blocks
US6470427B1 (en) 1999-11-09 2002-10-22 International Business Machines Corporation Programmable agent and method for managing prefetch queues
US6567894B1 (en) 1999-12-08 2003-05-20 International Business Machines Corporation Method and apparatus to prefetch sequential pages in a multi-stream environment
US6628294B1 (en) 1999-12-31 2003-09-30 Intel Corporation Prefetching of virtual-to-physical address translation for display data
JP4341186B2 (ja) 2001-01-22 2009-10-07 株式会社日立製作所 メモリシステム
US6571318B1 (en) * 2001-03-02 2003-05-27 Advanced Micro Devices, Inc. Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism
JP3969009B2 (ja) * 2001-03-29 2007-08-29 株式会社日立製作所 ハードウェアプリフェッチシステム
WO2003025755A2 (en) * 2001-09-14 2003-03-27 Seagate Technology Llc sETHOD AND SYSTEM FOR CACHE MANAGEMENT ALGORITHM SELECTION
US6760818B2 (en) 2002-05-01 2004-07-06 Koninklijke Philips Electronics N.V. Memory region based data pre-fetching
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
JP4532931B2 (ja) * 2004-02-25 2010-08-25 株式会社日立製作所 プロセッサ、および、プリフェッチ制御方法
EP1610323A1 (en) * 2004-06-22 2005-12-28 Koninklijke Philips Electronics N.V. Defect management on file level
US7418531B2 (en) * 2005-05-04 2008-08-26 Pillar Data Systems, Inc. Quality of service for data storage volumes
US7457923B1 (en) * 2005-05-11 2008-11-25 Sun Microsystems, Inc. Method and structure for correlation-based prefetching
US20060294315A1 (en) * 2005-06-27 2006-12-28 Seagate Technology Llc Object-based pre-fetching Mechanism for disc drives
US8612956B2 (en) * 2007-12-05 2013-12-17 International Business Machines Corporation Efficient object profiling for optimizing object locality
US8918588B2 (en) * 2009-04-07 2014-12-23 International Business Machines Corporation Maintaining a cache of blocks from a plurality of data streams
US8566496B2 (en) * 2010-12-03 2013-10-22 Lsi Corporation Data prefetch in SAS expanders
US10642502B2 (en) 2018-06-29 2020-05-05 Western Digital Technologies, Inc. System and method for prediction of read commands to non-sequential data
US10649776B2 (en) 2018-06-29 2020-05-12 Western Digital Technologies, Inc. System and method for prediction of multiple read commands directed to non-sequential data
US10642742B2 (en) 2018-08-14 2020-05-05 Texas Instruments Incorporated Prefetch management in a hierarchical cache system
US10846226B2 (en) 2019-01-28 2020-11-24 Western Digital Technologies, Inc. System and method for prediction of random read commands in virtualized multi-queue memory systems
US10896131B2 (en) 2019-01-28 2021-01-19 Western Digital Technologies, Inc. System and method for configuring a storage device based on prediction of host source
US10719445B1 (en) 2019-02-28 2020-07-21 Western Digital Technologies, Inc. System and method for scaling a historical pattern matching data structure in a memory device
US10725781B1 (en) 2019-02-28 2020-07-28 Western Digital Technologies, Inc. System and method for chain prediction of multiple read commands
US11055022B2 (en) 2019-03-25 2021-07-06 Western Digital Technologies, Inc. Storage system and method for early host command fetching in a low queue depth environment
US11010299B2 (en) 2019-05-20 2021-05-18 Western Digital Technologies, Inc. System and method for performing discriminative predictive read
US11416263B1 (en) 2021-02-12 2022-08-16 Western Digital Technologies, Inc. Boosted boot procedure by background re-arrangement of read patterns

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4262332A (en) * 1978-12-28 1981-04-14 International Business Machines Corporation Command pair to improve performance and device independence
US4468730A (en) * 1981-11-27 1984-08-28 Storage Technology Corporation Detection of sequential data stream for improvements in cache data storage
US5093777A (en) * 1989-06-12 1992-03-03 Bull Hn Information Systems Inc. Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack
US5233702A (en) * 1989-08-07 1993-08-03 International Business Machines Corporation Cache miss facility with stored sequences for data fetching
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5357618A (en) * 1991-04-15 1994-10-18 International Business Machines Corporation Cache prefetch and bypass using stride registers
US5305389A (en) * 1991-08-30 1994-04-19 Digital Equipment Corporation Predictive cache system
US5367656A (en) * 1992-03-13 1994-11-22 Bull Hn Information Systems Inc. Controlling cache predictive prefetching based on cache hit ratio trend
US5586294A (en) * 1993-03-26 1996-12-17 Digital Equipment Corporation Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer
US5426764A (en) * 1993-08-24 1995-06-20 Ryan; Charles P. Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor

Also Published As

Publication number Publication date
SE469402B (sv) 1993-06-28
DE69228380D1 (de) 1999-03-18
EP0582635B1 (en) 1999-02-03
US6078996A (en) 2000-06-20
ATE176534T1 (de) 1999-02-15
JPH06510611A (ja) 1994-11-24
KR100277818B1 (ko) 2001-01-15
SE9101325D0 (sv) 1991-05-02
DE69228380T2 (de) 1999-08-26
US5802566A (en) 1998-09-01
WO1992020027A1 (en) 1992-11-12
EP0582635A1 (en) 1994-02-16

Similar Documents

Publication Publication Date Title
SE9101325D0 (sv) Foerfarande foer att oeka databehandlingshastigheten i datasystem
EP0343567A3 (en) Multi-processing system and cache apparatus for use in the same
KR840001368A (ko) 데이타 처리 시스템에서의 선택적 캐쉬 클리어링 방법과 장치
KR970029103A (ko) 데이터 처리 시스템 및 데이터 처리 방법
EP0496506A3 (en) A processing unit for a computer and a computer system incorporating such a processing unit
ATE542179T1 (de) Mehrstufiges cachespeichersystem
EP0321793A3 (en) Apparatus for forcing a reload from main memory upon cache memory error
KR970029141A (ko) 인스트럭션 프리페치 방법 및 데이터 처리 시스템
KR930700907A (ko) 스톨캐쉬를 제공하기 위한 장치 및 방법
EP0374370A3 (en) Method for storing into non-exclusive cache lines in multiprocessor systems
ES2144488T3 (es) Sistema de tratamiento de datos que emplea coherencia de antememoria empleando un protocolo de escrutinio.
KR970705086A (ko) 같은 클락 사이클 동안에 캐쉬 메모리와 외부 메모리 제어기로 메모리 요청을 하는 파이프라인 마이크로프로세서(A Pipelined Microprocessor that Makes Memory Requests to a Cache Memory and an external Memory Controller During the Same Clock Cycle)
KR940018763A (ko) 데이타 처리 장치에서 메모리로부터 다중 프로세서의 데이타전송 효율을 향상시키기 위한 방법 및 장치.
US5960456A (en) Method and apparatus for providing a readable and writable cache tag memory
KR960018958A (ko) 다중 프로세서 시스템에서 아토믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치
KR930702726A (ko) 분리된 구조적 의존도를 가진 알 아이 에스 씨(risc) 마이크로프로세서 구조
JPS6476343A (en) Cache memory control system
JPS57200985A (en) Buffer memory device
JPH03116345A (ja) データ処理装置
KR970049517A (ko) 고속 중형컴퓨터에 있어서 isdn보드의 데이타 전달방법
KR940022269A (ko) 캐쉬제어방식 및 장치
JPS56124954A (en) Advance control type information processing equipment
KR880011679A (ko) Dma 억세스 중재 장치
JPS6428736A (en) Data error processing system for processing unit of common bus system
KR910001566A (ko) 공통 메모리 억쎄스방식

Legal Events

Date Code Title Description
NAL Patent in force

Ref document number: 9101325-0

Format of ref document f/p: F

NUG Patent has lapsed