SE8107832L - Dator med forbettrat fickminne - Google Patents

Dator med forbettrat fickminne

Info

Publication number
SE8107832L
SE8107832L SE8107832A SE8107832A SE8107832L SE 8107832 L SE8107832 L SE 8107832L SE 8107832 A SE8107832 A SE 8107832A SE 8107832 A SE8107832 A SE 8107832A SE 8107832 L SE8107832 L SE 8107832L
Authority
SE
Sweden
Prior art keywords
cache
central processor
dedicated
cycle
processor
Prior art date
Application number
SE8107832A
Other languages
Unknown language ( )
English (en)
Other versions
SE445270B (sv
Inventor
H H Tsiang
Original Assignee
Wang Laboratories
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wang Laboratories filed Critical Wang Laboratories
Publication of SE8107832L publication Critical patent/SE8107832L/sv
Publication of SE445270B publication Critical patent/SE445270B/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0857—Overlapped cache accessing, e.g. pipeline by multiple requestors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
SE8107832A 1981-01-07 1981-12-29 Dator med ett fickminne, vars arbetscykel er uppdelad i tva delcykler SE445270B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22315481A 1981-01-07 1981-01-07

Publications (2)

Publication Number Publication Date
SE8107832L true SE8107832L (sv) 1982-07-08
SE445270B SE445270B (sv) 1986-06-09

Family

ID=22835271

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8107832A SE445270B (sv) 1981-01-07 1981-12-29 Dator med ett fickminne, vars arbetscykel er uppdelad i tva delcykler

Country Status (10)

Country Link
JP (1) JPS57169990A (sv)
BE (1) BE891723A (sv)
CA (1) CA1175581A (sv)
CH (1) CH656470A5 (sv)
DE (1) DE3200042A1 (sv)
FR (1) FR2497596B1 (sv)
GB (1) GB2090681B (sv)
IT (1) IT1154407B (sv)
NL (1) NL8200043A (sv)
SE (1) SE445270B (sv)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS617967A (ja) * 1984-06-15 1986-01-14 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Ｉ／ｏコントロ−ラ
AU5634086A (en) * 1985-05-06 1986-11-13 Wang Laboratories, Inc. Information processing system with enhanced instruction execution and support control
US4814981A (en) * 1986-09-18 1989-03-21 Digital Equipment Corporation Cache invalidate protocol for digital data processing system
DE3920883A1 (de) * 1989-06-26 1991-01-03 Siemens Ag Verfahren und anordnung zur erhoehung der verarbeitungsgeschwindigkeit der zentraleinheit einer datenverarbeitungsanlage
JPH03189845A (ja) * 1989-12-13 1991-08-19 Internatl Business Mach Corp <Ibm> 階層メモリ・システムおよびキヤツシユ・メモリ・サブシステム
JPH0756815A (ja) * 1993-07-28 1995-03-03 Internatl Business Mach Corp <Ibm> キャッシュ動作方法及びキャッシュ
JP5494643B2 (ja) 2009-02-20 2014-05-21 旭硝子株式会社 エレクトレットの製造方法及び静電誘導型変換素子

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
JPS51148334A (en) * 1975-06-16 1976-12-20 Hitachi Ltd Buffer memory control method
JPS5441291A (en) * 1977-09-09 1979-04-02 Sagami Chem Res Center Cluster fixed substance, production thereof and catalyst
US4169284A (en) * 1978-03-07 1979-09-25 International Business Machines Corporation Cache control for concurrent access
US4208716A (en) * 1978-12-11 1980-06-17 Honeywell Information Systems Inc. Cache arrangement for performing simultaneous read/write operations
GB2037039B (en) * 1978-12-11 1983-08-17 Honeywell Inf Systems Cache memory system

Also Published As

Publication number Publication date
FR2497596A1 (fr) 1982-07-09
BE891723A (fr) 1982-04-30
JPH0353657B2 (sv) 1991-08-15
FR2497596B1 (fr) 1989-03-03
IT1154407B (it) 1987-01-21
DE3200042C2 (sv) 1991-03-07
GB2090681B (en) 1985-11-20
SE445270B (sv) 1986-06-09
JPS57169990A (en) 1982-10-19
GB2090681A (en) 1982-07-14
CA1175581A (en) 1984-10-02
NL8200043A (nl) 1982-08-02
CH656470A5 (de) 1986-06-30
DE3200042A1 (de) 1982-08-19
IT8267010A0 (it) 1982-01-06

Similar Documents

Publication Publication Date Title
US9928180B2 (en) Synchronizing a translation lookaside buffer with page tables
US4504902A (en) Cache arrangement for direct memory access block transfer
KR100204741B1 (ko) 제1및 제2캐시 메모리 사용방법
Yan et al. Hardware translation coherence for virtualized systems
US6594734B1 (en) Method and apparatus for self modifying code detection using a translation lookaside buffer
KR890017609A (ko) 멀티프로세서 데이타 처리시스템 및 그것에 사용되는 캐시장치
US5155828A (en) Computing system with a cache memory and an additional look-aside cache memory
KR20210021464A (ko) 예약된 태그 필드 비트를 사용하는 캐시 기반 트레이스 리플레이 중단점
US5590310A (en) Method and structure for data integrity in a multiple level cache system
KR880011674A (ko) 캐쉬 메모리 장치
SE8107832L (sv) Dator med forbettrat fickminne
JP4047281B2 (ja) キャッシュメモリをメインメモリに同期させる方法
EP0173909A2 (en) Look-aside buffer least recently used marker controller
JPH055137B2 (sv)
US11314657B1 (en) Tablewalk takeover
KR920005296B1 (ko) 정보처리장치
KR100201671B1 (ko) 컴퓨팅 시스템 및 컴퓨팅 시스템의 캐시 메모리 이용방법
JP3293872B2 (ja) キャッシュ一致化方式
EP0229253A2 (en) Data processor with virtual memory management
JPS63240651A (ja) キヤツシユメモリ
Cox et al. Hardware Translation Coherence for Virtualized Systems
JPS55117780A (en) Buffer memory unit
EP0362366A4 (en) Instruction cache flush-on-rei control
JPS6135583B2 (sv)
JPH03228150A (ja) キャッシュメモリコントローラ

Legal Events

Date Code Title Description
NUG Patent has lapsed

Ref document number: 8107832-1

Effective date: 19940710

Format of ref document f/p: F