SE437581B - Databuffertminne - Google Patents

Databuffertminne

Info

Publication number
SE437581B
SE437581B SE7812716A SE7812716A SE437581B SE 437581 B SE437581 B SE 437581B SE 7812716 A SE7812716 A SE 7812716A SE 7812716 A SE7812716 A SE 7812716A SE 437581 B SE437581 B SE 437581B
Authority
SE
Sweden
Prior art keywords
memory
register
signal
data
input
Prior art date
Application number
SE7812716A
Other languages
English (en)
Swedish (sv)
Inventor
P G Jansen
J L W Kessels
B L A Waumans
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of SE437581B publication Critical patent/SE437581B/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
SE7812716A 1977-12-12 1978-12-11 Databuffertminne SE437581B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7713707A NL7713707A (nl) 1977-12-12 1977-12-12 Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met variabele ingang en vaste uitgang.

Publications (1)

Publication Number Publication Date
SE437581B true SE437581B (sv) 1985-03-04

Family

ID=19829732

Family Applications (2)

Application Number Title Priority Date Filing Date
SE7812716A SE437581B (sv) 1977-12-12 1978-12-11 Databuffertminne
SE7812716D SE7812716L (sv) 1977-12-12 1978-12-11 Databuffertminne

Family Applications After (1)

Application Number Title Priority Date Filing Date
SE7812716D SE7812716L (sv) 1977-12-12 1978-12-11 Databuffertminne

Country Status (9)

Country Link
US (1) US4236225A (nl)
JP (1) JPS5920139B2 (nl)
CA (1) CA1122329A (nl)
DE (1) DE2853239A1 (nl)
FR (1) FR2411467A1 (nl)
GB (1) GB2009984B (nl)
IT (1) IT1101479B (nl)
NL (1) NL7713707A (nl)
SE (2) SE437581B (nl)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57164331A (en) * 1981-04-02 1982-10-08 Nec Corp Buffer controller
JPS57185492A (en) * 1981-05-11 1982-11-15 Matsushita Electric Ind Co Ltd Data latch circuit
JPS58220293A (ja) * 1982-06-15 1983-12-21 Nec Corp 記憶装置
US4510581A (en) * 1983-02-14 1985-04-09 Prime Computer, Inc. High speed buffer allocation apparatus
US4930102A (en) * 1983-04-29 1990-05-29 The Regents Of The University Of California Dynamic activity-creating data-driven computer architecture
JPS59226923A (ja) * 1983-05-27 1984-12-20 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン バスインタ−フエ−ス装置
US4598363A (en) * 1983-07-07 1986-07-01 At&T Bell Laboratories Adaptive delayed polling of sensors
US4592019A (en) * 1983-08-31 1986-05-27 At&T Bell Laboratories Bus oriented LIFO/FIFO memory
FR2552916B1 (fr) * 1983-09-29 1988-06-10 Thomas Alain File d'attente asynchrone a empilement de registres
US5038277A (en) * 1983-11-07 1991-08-06 Digital Equipment Corporation Adjustable buffer for data communications in a data processing system
AU575351B2 (en) * 1983-11-07 1988-07-28 Digital Equipment Corporation Data processing system
US4764894A (en) * 1985-01-16 1988-08-16 Varian Associates, Inc. Multiple FIFO NMR acquisition system
US4833655A (en) * 1985-06-28 1989-05-23 Wang Laboratories, Inc. FIFO memory with decreased fall-through delay
NL8502023A (nl) * 1985-07-15 1987-02-02 Philips Nv Werkwijze voor het schakelen van tijdsloten in een tdm-signaal en inrichting voor het uitvoeren van de werkwijze.
US4672646A (en) * 1986-09-16 1987-06-09 Hewlett-Packard Company Direct-injection FIFO shift register
US4995005A (en) * 1986-09-18 1991-02-19 Advanced Micro Devices, Inc. Memory device which can function as two separate memories or a single memory
US4847812A (en) * 1986-09-18 1989-07-11 Advanced Micro Devices FIFO memory device including circuit for generating flag signals
JPS648732A (en) * 1987-06-30 1989-01-12 Sharp Kk Digital serial/parallel converter
US5115496A (en) * 1988-01-26 1992-05-19 Nec Corporation Queue device capable of quickly transferring a digital signal unit of a word length different from a single word length
JP2764908B2 (ja) * 1988-02-04 1998-06-11 日本電気株式会社 カスケード・バッファ回路
JP2576616B2 (ja) * 1988-12-29 1997-01-29 カシオ計算機株式会社 処理装置
JPH0391188A (ja) * 1989-09-04 1991-04-16 Matsushita Electric Ind Co Ltd Ｆｉｆｏメモリ
US5095462A (en) * 1990-05-25 1992-03-10 Advanced Micro Devices, Inc. Fifo information storage apparatus including status and logic modules for each cell
US5412611A (en) * 1992-03-17 1995-05-02 Fujitsu, Limited FIFO memory device capable of writing contiguous data into rows
US5513224A (en) * 1993-09-16 1996-04-30 Codex, Corp. Fill level indicator for self-timed fifo
WO1997003444A1 (en) * 1995-07-10 1997-01-30 Xilinx, Inc. System comprising field programmable gate array and intelligent memory
EP0932862A2 (en) 1997-08-20 1999-08-04 Koninklijke Philips Electronics N.V. A transient datastream-processing buffer memory organization with software management adapted for multilevel housekeeping
JP4841314B2 (ja) * 2006-05-29 2011-12-21 川崎マイクロエレクトロニクス株式会社 データ転送回路
JP6568560B2 (ja) 2017-09-15 2019-08-28 株式会社Ｓｕｂａｒｕ 車両の走行制御装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6600550A (nl) * 1966-01-15 1967-07-17
US3646526A (en) * 1970-03-17 1972-02-29 Us Army Fifo shift register memory with marker and data bit storage
NL7014737A (nl) * 1970-10-08 1972-04-11
GB1289249A (nl) * 1971-05-05 1972-09-13
US3781821A (en) * 1972-06-02 1973-12-25 Ibm Selective shift register
US3942163A (en) * 1974-06-21 1976-03-02 Burroughs Corporation CCD stack memory organization
US3953838A (en) * 1974-12-30 1976-04-27 Burroughs Corporation FIFO Buffer register memory utilizing a one-shot data transfer system
JPS5247638A (en) * 1975-10-15 1977-04-15 Toshiba Corp Information processing device
US4095283A (en) * 1976-07-02 1978-06-13 International Business Machines Corporation First in-first out memory array containing special bits for replacement addressing

Also Published As

Publication number Publication date
DE2853239C2 (nl) 1989-02-02
IT1101479B (it) 1985-09-28
JPS5920139B2 (ja) 1984-05-11
DE2853239A1 (de) 1979-06-13
FR2411467A1 (fr) 1979-07-06
SE7812716L (sv) 1979-06-13
US4236225A (en) 1980-11-25
JPS5489439A (en) 1979-07-16
CA1122329A (en) 1982-04-20
FR2411467B1 (nl) 1985-01-18
IT7830681A0 (it) 1978-12-07
GB2009984B (en) 1982-01-27
NL7713707A (nl) 1979-06-14
GB2009984A (en) 1979-06-20

Similar Documents

Publication Publication Date Title
SE437581B (sv) Databuffertminne
US5345419A (en) Fifo with word line match circuits for flag generation
US5898893A (en) Fifo memory system and method for controlling
EP0183875A2 (en) Clocked logic device
JP4036270B2 (ja) メモリ構造
US4785204A (en) Coincidence element and a data transmission path
KR100317203B1 (ko) 스루율을제어할수있는출력버퍼회로
SE503914C2 (sv) Dataöverföringssystem
US6240031B1 (en) Memory architecture
US6285229B1 (en) Digital delay line with low insertion delay
SE449672B (sv) Minnesanordning, innefattande tva par atkomstledningar
US5206834A (en) Semiconductor memory device performing last in-first out operation and the method for controlling the same
US3300724A (en) Data register with particular intrastage feedback and transfer means between stages to automatically advance data
US6400642B1 (en) Memory architecture
KR100209975B1 (ko) 표시 장치
JP3765273B2 (ja) シフトレジスタ
KR100249498B1 (ko) 분산 표본 혼화 장치의 병렬 처리기
JPH06311127A (ja) ディジタルデータ調停装置
SE515563C2 (sv) Dataöverföringssystem
KR100217270B1 (ko) 반도체 메모리 장치
US6240044B1 (en) High speed address sequencer
KR960008323B1 (ko) 병렬 데이타 포트 선택 장치
US6055276A (en) Signal transmitting circuit and method with selection among differential pairs
US5394364A (en) High-speed memory readout circuit using a single set of data buffers
US20040027909A1 (en) Self-synchronous FIFO memory device

Legal Events

Date Code Title Description
NUG Patent has lapsed

Ref document number: 7812716-4

Effective date: 19920704