SE384756B - Lagringsmatris innefattande ett flertal minnesceller av laddningskopplad typ samt metod for framstellning av en sadan minnescell - Google Patents

Lagringsmatris innefattande ett flertal minnesceller av laddningskopplad typ samt metod for framstellning av en sadan minnescell

Info

Publication number
SE384756B
SE384756B SE7208905A SE890572A SE384756B SE 384756 B SE384756 B SE 384756B SE 7208905 A SE7208905 A SE 7208905A SE 890572 A SE890572 A SE 890572A SE 384756 B SE384756 B SE 384756B
Authority
SE
Sweden
Prior art keywords
matrium
manufacture
storage
charge coupled
including several
Prior art date
Application number
SE7208905A
Other languages
English (en)
Swedish (sv)
Inventor
N G Anantha
T-L Chiu
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SE384756B publication Critical patent/SE384756B/xx

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Non-Volatile Memory (AREA)
SE7208905A 1971-08-09 1972-07-06 Lagringsmatris innefattande ett flertal minnesceller av laddningskopplad typ samt metod for framstellning av en sadan minnescell SE384756B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16996171A 1971-08-09 1971-08-09

Publications (1)

Publication Number Publication Date
SE384756B true SE384756B (sv) 1976-05-17

Family

ID=22617925

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7208905A SE384756B (sv) 1971-08-09 1972-07-06 Lagringsmatris innefattande ett flertal minnesceller av laddningskopplad typ samt metod for framstellning av en sadan minnescell

Country Status (10)

Country Link
JP (1) JPS5314351B2 (de)
AR (1) AR200242A1 (de)
BR (2) BR7205394D0 (de)
CH (1) CH534939A (de)
DE (1) DE2236510C3 (de)
FR (1) FR2148581B1 (de)
GB (1) GB1374009A (de)
IT (1) IT963412B (de)
NL (1) NL7209890A (de)
SE (1) SE384756B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES404184A1 (es) * 1971-07-06 1975-06-01 Ibm Una disposicion de celula de memoria de acceso casual para calculadoras digitales.
DE2441385C3 (de) * 1974-08-29 1981-05-07 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Vergrößern des Lesesignals bei einem Ein- Transistor-Speicherelement
JPS51147226A (en) * 1975-06-13 1976-12-17 Nec Corp Semiconductor memory device
JPS5811103B2 (ja) * 1975-11-07 1983-03-01 株式会社日立製作所 ハンドウタイメモリ
JPS5853512B2 (ja) * 1976-02-13 1983-11-29 株式会社東芝 半導体記憶装置の製造方法
GB1562650A (en) * 1976-11-18 1980-03-12 Fairchild Camera Instr Co Memory cell for storing charge
EP0003413A3 (de) * 1978-01-19 1979-08-22 Sperry Corporation Massnahmen zur Verbesserung eines Halbleiterspeichers
DE2912858A1 (de) * 1979-03-30 1980-10-09 Siemens Ag Niederohmige leitung
JPH0782753B2 (ja) * 1984-08-31 1995-09-06 三菱電機株式会社 ダイナミックメモリ装置

Also Published As

Publication number Publication date
JPS4826437A (de) 1973-04-07
BR7205394D0 (pt) 1973-06-07
BR7205403D0 (pt) 1973-06-07
FR2148581A1 (de) 1973-03-23
AR200242A1 (es) 1974-10-31
GB1374009A (en) 1974-11-13
DE2236510C3 (de) 1975-01-23
FR2148581B1 (de) 1980-03-21
DE2236510A1 (de) 1973-03-08
IT963412B (it) 1974-01-10
NL7209890A (de) 1973-02-13
DE2236510B2 (de) 1974-05-22
CH534939A (de) 1973-03-15
JPS5314351B2 (de) 1978-05-17

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