SE384756B - Lagringsmatris innefattande ett flertal minnesceller av laddningskopplad typ samt metod for framstellning av en sadan minnescell - Google Patents
Lagringsmatris innefattande ett flertal minnesceller av laddningskopplad typ samt metod for framstellning av en sadan minnescellInfo
- Publication number
- SE384756B SE384756B SE7208905A SE890572A SE384756B SE 384756 B SE384756 B SE 384756B SE 7208905 A SE7208905 A SE 7208905A SE 890572 A SE890572 A SE 890572A SE 384756 B SE384756 B SE 384756B
- Authority
- SE
- Sweden
- Prior art keywords
- matrium
- manufacture
- storage
- charge coupled
- including several
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16996171A | 1971-08-09 | 1971-08-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SE384756B true SE384756B (sv) | 1976-05-17 |
Family
ID=22617925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SE7208905A SE384756B (sv) | 1971-08-09 | 1972-07-06 | Lagringsmatris innefattande ett flertal minnesceller av laddningskopplad typ samt metod for framstellning av en sadan minnescell |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JPS5314351B2 (xx) |
| AR (1) | AR200242A1 (xx) |
| BR (2) | BR7205394D0 (xx) |
| CH (1) | CH534939A (xx) |
| DE (1) | DE2236510C3 (xx) |
| FR (1) | FR2148581B1 (xx) |
| GB (1) | GB1374009A (xx) |
| IT (1) | IT963412B (xx) |
| NL (1) | NL7209890A (xx) |
| SE (1) | SE384756B (xx) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ES404184A1 (es) * | 1971-07-06 | 1975-06-01 | Ibm | Una disposicion de celula de memoria de acceso casual para calculadoras digitales. |
| DE2441385C3 (de) * | 1974-08-29 | 1981-05-07 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum Vergrößern des Lesesignals bei einem Ein- Transistor-Speicherelement |
| JPS51147226A (en) * | 1975-06-13 | 1976-12-17 | Nec Corp | Semiconductor memory device |
| JPS5811103B2 (ja) * | 1975-11-07 | 1983-03-01 | 株式会社日立製作所 | ハンドウタイメモリ |
| JPS5853512B2 (ja) * | 1976-02-13 | 1983-11-29 | 株式会社東芝 | 半導体記憶装置の製造方法 |
| GB1562650A (en) * | 1976-11-18 | 1980-03-12 | Fairchild Camera Instr Co | Memory cell for storing charge |
| IT1110947B (it) * | 1978-01-19 | 1986-01-13 | Sperry Rand Corp | Elemento di memoria ad accesso comandato |
| DE2912858A1 (de) * | 1979-03-30 | 1980-10-09 | Siemens Ag | Niederohmige leitung |
| JPH0782753B2 (ja) * | 1984-08-31 | 1995-09-06 | 三菱電機株式会社 | ダイナミックメモリ装置 |
-
1972
- 1972-06-23 GB GB2941972A patent/GB1374009A/en not_active Expired
- 1972-07-06 SE SE7208905A patent/SE384756B/xx unknown
- 1972-07-14 JP JP7008672A patent/JPS5314351B2/ja not_active Expired
- 1972-07-18 NL NL7209890A patent/NL7209890A/xx unknown
- 1972-07-26 DE DE2236510A patent/DE2236510C3/de not_active Expired
- 1972-07-26 FR FR7228829A patent/FR2148581B1/fr not_active Expired
- 1972-07-27 IT IT27478/72A patent/IT963412B/it active
- 1972-07-28 CH CH1133272A patent/CH534939A/de not_active IP Right Cessation
- 1972-08-09 BR BR5394/72A patent/BR7205394D0/pt unknown
- 1972-08-09 BR BR5403/72A patent/BR7205403D0/pt unknown
- 1972-08-21 AR AR243646A patent/AR200242A1/es active
Also Published As
| Publication number | Publication date |
|---|---|
| IT963412B (it) | 1974-01-10 |
| DE2236510C3 (de) | 1975-01-23 |
| DE2236510B2 (de) | 1974-05-22 |
| BR7205394D0 (pt) | 1973-06-07 |
| FR2148581B1 (xx) | 1980-03-21 |
| JPS5314351B2 (xx) | 1978-05-17 |
| AR200242A1 (es) | 1974-10-31 |
| CH534939A (de) | 1973-03-15 |
| GB1374009A (en) | 1974-11-13 |
| BR7205403D0 (pt) | 1973-06-07 |
| NL7209890A (xx) | 1973-02-13 |
| JPS4826437A (xx) | 1973-04-07 |
| DE2236510A1 (de) | 1973-03-08 |
| FR2148581A1 (xx) | 1973-03-23 |
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