GB1562650A - Memory cell for storing charge - Google Patents

Description

(54) MEMORY CELL FOR STORING CHARGE (71) We, FAIRCHILD CAMERA AND INSTRUMENT CORPORATION of 464 Ellis Street, Mountain View, California 94042, United States of America, a corporation organised and existing under the laws of the State of Delaware, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a memory cell for storing charge and to a semiconductor structure comprising such memory cells.

The invention will be readily understood from the following description and accompanying drawings in which: Figures la and l b illustrate, respectively a typical prior-art structure and the resulting schematic diagram; Figures 2a and 2c illustrate a process by which a semiconductor structure embodying this invention may be formed; Figure 2d depicts a semiconductor structure embodying this invention; Figure 3 is a schematic diagram of a four-cell array incorporating singletransistor cells embodying this invention; and Figures 4a and 4c illustrate another process by which a semiconductor structure embodying this invention may be formed.

Figure 4d depicts another structure of this invention.

Single-transistor memory cells which utilize a passive storage region are well known in the art and have been the subject of numerous patents and other literature. See e.g., Gerald Kuecke, et al.. "Semiconductor Memory Design and Application", p.123 (1973) and Bruce Threewit, "Memories Come of Age" in Fairchld Journal of Semiconductor Progress, Vol. 4, No.1. September, October 1976, p. 12. One such structure is depicted in Figure la with an accompanying schematic diagram depicted in Figure lb.

Such prior-art devices typically stored a bit of information in the form of the potential difference between regions a and b as shown in Figure la. The magnitude of the charge in this capacitor would determine the sense of the bit of information, e.g., a "1" or a "0". The overall region in which information is stored is commonly referred to as the "storage region" and is so designated in Figure la. In operation, application of a suitable signal to the word line as shown schematically in Figure 1b activates the transistor and allows the bit line to sense the condition of the storage region, that is, to sense the potential difference between a and b. Typically, the bit line is connected to an amplifier in some other location of the circuit, which amplifies any signal perceived by the bit line, so that the amplified signal may perform other functions in other parts of the device within which the memory cell is situated.

Unfortunately, prior-art memory cells as depicted in Figure la, and shown schematically in Figure lb, require a junction region and a gate (word line) to electrically connect the bit line with the storage region when a selected potential is applied to the word line. Such a junction region occupies a significant amount of die surface area and increases the amount of die surface area required for the formation of each memory cell in an array of such cells. Elimination of the junction region would be desirable as elimination would facilitate manufacture of smaller memory cells than those heretofore existing, amd therefore would reduce the area required for formation of an array of memory cells.

The invention accordingly provides a memory cell comprising: a single region of semiconductor material of one conductivity type formed in a subs trate of opposite conductivity type; a first electrode disposed on a first insulating layer on the substrate, overlying a region of the substrate spaced apart from the single region, said first electrode being provided to control the storage of charge in said spaced apart region; a second electrode disposed on the insulating layer and overlying part of the first electrode, the second electrode being separated from the first electrode by a second insulating layer and overlying a continuous region of the substrate extending from said spaced apart region to said single region to control the transfer of charge from said spaced apart region to said single region.

Although the invention is discussed below primarily in terms of a single memory cell, it will be evident as from Figure 3 that groups of such cells can be interconnected to form a semiconductor structure comprising an array of such memory cells.

In the formation of memory cells according to this invention, no junction region is necessary to connect the passive storage region with the bit line. The junction region is eliminated by utilizing a suitably thin layer of insulating material as the second insulating layer between the partially overlapping, but electrically isolated layers of conductive material disposed upon the wafer surface to act as the first and second electrodes. By suitable control of manufacturing processes.

the layer of insulating material separating the two layers of conductive material can be made sufficiently thin so that the semiconductor structure functions like a chargecoupled device. Charge stored in a potential well in the substrate underneath the overlap between the partially-overlapping, but electrically isolated, layers of conductive material may be transferred to the bit line in accordance with changes in potential on the layer of electrically conductive material which serves as a word line. In a similar manner, charge may be written into the potential well.

Although the semiconductor structure of this invention may be fabricated without regard to any particular technique of forming electrically insulating regions around each memory cell, the structure of the memory cell herein is discussed for illustrative purposes in conjunction with a typical oxide-isolation process, for example, as set forth in U.S. Patent No. 3,648.125, issued to Douglas L. Peltzer. and entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure." The single-transistor memory cell of this invention may be fabricated utilizing the process depicted in Figures 2a to 2d. The structure shown in Figure 2a may be achieved utilizing the following steps: 1) Oxidize p-type silicon wafer 21 to create oxide region 22.

2) Deposit silicon nitride layer 23 on oxide layer 22, and selectively remove those portions of silicon nitride layer 23 which overlie field oxide isolation regions to be formed.

Any one of several well-known techniques may be utilized to obtain the structure depicted in Figure 2b from that depicted in Figure 2a. According to one such technique, p type semiconductor material is used to dope those surfaces of substrate 21 upon which field oxide isolation will be formed.

p+ regions 20a and 20b function to prevent the well-known phenomenon of channel inversion from occurring at the interface between substrate 21 and field oxide isolation regions 24a and 24b. Silicon wafer 21 is then oxidized further to create field oxide isolation regions 24a and 24b. This annularshaped field oxide region functions to isolate the memory cell from neighboring memory cells in the same array. Silicon nitride layer 23 and underlying oxide layer 22 are then removed from the surface of substrate 21. A suitably thin layer of oxide 25, referred to herein as gate oxide 25, is then grown on the surface of substrate 21. In one embodiment of this invention gate oxide 25 has a thickness of 1000 Angstroms.

An electrically conductive layer 26, typically polycrystalline silicon, is then deposited and selectively removed by conventional techniques to cover selected areas of the wafer surface. A layer of insulating material 27, typically silicon dioxide, is formed over layer 26. Insulating material 27 will later separate layer 26 from subsequently-formed electrically-conducting regions deposited on the surface of the wafer. In some embodiments of this invention insulating material 27 is 2000 Angstroms.

The structure depicted in Figure 2c is obtained from that depicted in Figure 2b by depositing and selectively removing a second layer of electrically conducting matrerial 28, typically polycrystalline silicon. Conducting material 28 will partially overlap insulating material 27, and will also be formed on gate oxide 25. A "window" (not shown) is opened in gate oxide 25 and source-drain region 29 is diffused or otherwise introduced into substrate 21. Finally, another layer of oxide 30 may be formed above and around electrically conducting material 28 to protect conducting material 28 and to electrically isolate it from any additional material formed on the upper surface of the structure depicted in Figure 2d.

By utilizing the process heretofore described, an array of i rows and j columns of one-transistor memory cells of the type illustrated in Figure 2d may be fabricated.

Electrical contact to desired locations in the array may be achieved by conventional well-known means. For example, a layer of oxide may be formed across the upper surface of the structure shown in Figure 2d and openings made in the oxide above conducting material 28. A conducting metal "word" line along one of the i rows may be then formed by conventional well-known processes to contact layer 28 in any desired number of individual memory cells. A "bit" line along one of the j columns may be framed by a modification whereby region 29 is configured as a continuous diffused region which forms a part of each cell in the particular column.

A companion process to the one depicted in Figure 2a to 2c is set out in Figure 4a to 4c. The process is identical except for one variation and results in another structure of the present invention as shown in Figure 4d.

First, the silicon nitride layer 42 of Figures 4a to 4d (corresponding to silicon nitride layer 23 in Figure 2a) is not removed during the initial processing. Thus, the insulation underlying the first layer of electrically conductive material 45 (corresponding to electrically conductive material 26 of Figure 2b) now consists of a composite layer of silicon nitride 42 overlying a layer of silicon dioxide 41. The retention of this silicon nitride layer saves several processing steps without affecting device performance. The composite layer is subsequently removed only over the diffused bit region 48 to permit formation of the region. Contact to the diffused bit region 48 is shown to be made through sinker metal contact 50 as an alternative to the diffused bit line contact described above for Figure 2d.

It will be understood by those skilled in the art of semiconductor manufacture that although this invention has been described in terms of given materials and conductivity types, other materials and conductivity types may be substituted which will function equally well. For example, in an alternative embodiment of the structure of the present invention, access to the diffused bit line may be made by opening gate oxide 25 and forming a sinker contact. shown as contact 50 in Figure 4d, with a continuous metal bit line which runs over the surface of gate oxide 25. In this alternative embodiment.

the word line is formed by fabricating layer 28 with a continuous polycrystalline silicon line. This embodiment provides a reduced bit line capacitance and allows a denser layer. Similarly. as previously discussed, this invention has been described in conjunction with oxide-isolation techniques. although other techniques suitable for isolating indi vidual memory cells in a large array of such cells may be utilized also. Further. although the invention has been described with reference to p-type silicon substrate and an n-type bit line, opposite conductivity-type materials may be utilized in fabricating the structure of this invention.

The schematic diagram of a four-cell array incorporating the single-transistor cell of this invention is depicted in Figure 3. This array is representative of cell interconnection and can be expanded to any desired size of i rows of word lines and j columns of bit lines. With reference to Figure 3, it is apparent that selection of any one word line, for example, i2, and any one bit line, for example, jl, will detect the information stored in only one memory cell, in the example, Ss j Although application of the appropriate signal to word line i2 allows any number of bit lines to be sensed to ascertain the information stored in any number of memory cells, selective sensing of the various bit lines may be utilized to uniquely ascertain the information stored in any single memory cell. The same procedure may be reversed in a well-known fashion to store information in any single memory cell.

The structure of this invention provides a substantial advantage over prior-art structures by significantly reducing the wafer surface area necessary for fabrication of one memory cell. This reduction in area is made possible by the elimination of the heretofore necessary junction region which has been utilized to connect the passive storage region with the bit line. The utilization of the electrically isolated, but partially overlapping, layers of conductive material and the principle of operation of charge-coupled devices allows electrical signals to pass from the storage region to the bit line, or vice versa, without the necessity of a junction region.

The elimination of a junction region allows fabrication of smaller one-transistor memory cells, thereby increasing the amount of memory which can be fabricated within a given amount of wafer surface area.

Such reductions in cell area facilitate the fabrication of larger and faster computer memories.

WHAT WE CLAIM IS: 1. A memory cell for storing charge, the memory cell comprising: a single region of semiconductor material of one conductivity type formed in a substrate of opposite conductivity type; a first electrode disposed on a first insulating layer on the substrate, overlying a region of the substrate spaced apart from the single region, said first electrode being provided to control the storage of charge in said spaced apart region; a second electrode disposed on the insulating layer and overlying part of the first electrode, the second electrode being separated from the first electrode by a second

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (11)

**WARNING** start of CLMS field may overlap end of DESC **. Electrical contact to desired locations in the array may be achieved by conventional well-known means. For example, a layer of oxide may be formed across the upper surface of the structure shown in Figure 2d and openings made in the oxide above conducting material 28. A conducting metal "word" line along one of the i rows may be then formed by conventional well-known processes to contact layer 28 in any desired number of individual memory cells. A "bit" line along one of the j columns may be framed by a modification whereby region 29 is configured as a continuous diffused region which forms a part of each cell in the particular column. A companion process to the one depicted in Figure 2a to 2c is set out in Figure 4a to 4c. The process is identical except for one variation and results in another structure of the present invention as shown in Figure 4d. First, the silicon nitride layer 42 of Figures 4a to 4d (corresponding to silicon nitride layer 23 in Figure 2a) is not removed during the initial processing. Thus, the insulation underlying the first layer of electrically conductive material 45 (corresponding to electrically conductive material 26 of Figure 2b) now consists of a composite layer of silicon nitride 42 overlying a layer of silicon dioxide 41. The retention of this silicon nitride layer saves several processing steps without affecting device performance. The composite layer is subsequently removed only over the diffused bit region 48 to permit formation of the region. Contact to the diffused bit region 48 is shown to be made through sinker metal contact 50 as an alternative to the diffused bit line contact described above for Figure 2d. It will be understood by those skilled in the art of semiconductor manufacture that although this invention has been described in terms of given materials and conductivity types, other materials and conductivity types may be substituted which will function equally well. For example, in an alternative embodiment of the structure of the present invention, access to the diffused bit line may be made by opening gate oxide 25 and forming a sinker contact. shown as contact 50 in Figure 4d, with a continuous metal bit line which runs over the surface of gate oxide 25. In this alternative embodiment. the word line is formed by fabricating layer 28 with a continuous polycrystalline silicon line. This embodiment provides a reduced bit line capacitance and allows a denser layer. Similarly. as previously discussed, this invention has been described in conjunction with oxide-isolation techniques. although other techniques suitable for isolating indi vidual memory cells in a large array of such cells may be utilized also. Further. although the invention has been described with reference to p-type silicon substrate and an n-type bit line, opposite conductivity-type materials may be utilized in fabricating the structure of this invention. The schematic diagram of a four-cell array incorporating the single-transistor cell of this invention is depicted in Figure 3. This array is representative of cell interconnection and can be expanded to any desired size of i rows of word lines and j columns of bit lines. With reference to Figure 3, it is apparent that selection of any one word line, for example, i2, and any one bit line, for example, jl, will detect the information stored in only one memory cell, in the example, Ss j Although application of the appropriate signal to word line i2 allows any number of bit lines to be sensed to ascertain the information stored in any number of memory cells, selective sensing of the various bit lines may be utilized to uniquely ascertain the information stored in any single memory cell. The same procedure may be reversed in a well-known fashion to store information in any single memory cell. The structure of this invention provides a substantial advantage over prior-art structures by significantly reducing the wafer surface area necessary for fabrication of one memory cell. This reduction in area is made possible by the elimination of the heretofore necessary junction region which has been utilized to connect the passive storage region with the bit line. The utilization of the electrically isolated, but partially overlapping, layers of conductive material and the principle of operation of charge-coupled devices allows electrical signals to pass from the storage region to the bit line, or vice versa, without the necessity of a junction region. The elimination of a junction region allows fabrication of smaller one-transistor memory cells, thereby increasing the amount of memory which can be fabricated within a given amount of wafer surface area. Such reductions in cell area facilitate the fabrication of larger and faster computer memories. WHAT WE CLAIM IS:

1. A memory cell for storing charge, the memory cell comprising: a single region of semiconductor material of one conductivity type formed in a substrate of opposite conductivity type; a first electrode disposed on a first insulating layer on the substrate, overlying a region of the substrate spaced apart from the single region, said first electrode being provided to control the storage of charge in said spaced apart region; a second electrode disposed on the insulating layer and overlying part of the first electrode, the second electrode being separated from the first electrode by a second

insulating layer and overlying a continuous region of the substrate extending from said spaced apart region to said single region to control the transfer of charge from said spaced apart region to said single region.

2. A memory cell as claimed in claim 1 wherein the substrate is substantially planar.

3. A memory cell as claimed in claim 1 or 2 wherein the first insulating layer comprises a layer of silicon nitride overlying a layer of silicon dioxide.

4. A memory cell as claimed in claim 1, 2 or 3 wherein said first electrode and said second electrode comprise polycrystalline silicon.

5. A memory cell as claimed in any preceding claim wherein the substrate is P conductivity type.

6. A memory cell as claimed in any one of claims 1 to 4 wherein the substrate is N conductivity type.

7. A memory cell substantially as herein described with reference to Figures 2a to 2d or Figures 4a to 4d of the accompanying drawings.

8. A semiconductor structure comprising an array of memory cells as claimed in any preceding claim arranged in I rows and J columns and fabricated in a single substrate, all of the second electrodes in each row of said I rows being electrically connected by first connecting means to form thereby a word line; and all of the single regions of semiconductor material in each column of said J columns being electrically connected by second connecting means to form thereby a bit line.

9. A structure as claimed in claim 8 wherein the first connecting means is a metal line, and the second connecting means is provided by extending each single region in each structure to contact the corresponding region in each of the adjacent structures in the column.

10. A structure as claimed in claim 8 wherein the first connecting means is a continuous layer of polycrystalline silicon, and the second connecting means is a metal line.

11. A semiconductor structure substantially as herein described with reference to Figure 3 of the accompanying drawings.