RU2292127C1 - Digital stereo television system - Google Patents

Abstract

FIELD: radio communications, possible use for television broadcasting, starting from decimeter range, in ground-based television networks and via satellite communication lines.

SUBSTANCE: in known system introduced additionally at transmitting side to frequency synthesizer is tenth output, and at receiving side second frequency divider, three-dimensional goggles with infrared receiver, infrared transmitter, position on lusterless screen are added. Code accumulator is introduced to each channel of video signal, while radiation modulation block is composed of 400 channels, while there are 800 active rows in frame with 1200 counts in a row, frame frequency is 50Hz, frequency of stereo pairs is 25Hz.

EFFECT: introduction of electronic control over separate observation of stereo-pair frames and 40000 times increased averaged brightness of image on screen.

20 dwg, 2 tbl

Description

The invention relates to radio communications technology, can be used for television broadcasting, starting with the decimeter range, in terrestrial TV networks and via satellite communication lines.

The digital stereo-television system [1] was adopted as a prototype, it contains a photoelectric converter on the transmitting side that generates six analog color signals of a stereo pair / right and left frames /, six ADCs, two ADCs of a sound signal, a sinusoidal oscillation generator and a frequency synthesizer, 1-3 code generators , the first and second self-propelled pulse distributors, pulse counter, trigger, two keys and a transmitter of radio signals from three channels, on the receiving side containing an antenna, control unit, 1-3 reception and processing paths video signal codes, a control signal generation channel and two sound channels, six pulse amplifier units, a radiation modulation unit, a first frequency divider, a horizontal scanning unit, a first amplifier and a first piezoelectric deflector with an end reflector, a frame scan unit, a second amplifier and a second piezoelectric deflector with a reflector at the end, four sources of reference voltages, a projection optical system and an opaque screen, a second frequency divider, an emitter and a unit for separate observation of frames. The stereo pair includes the following two frames sequentially, the repetition rate of stereo pairs is 25 Hz. Information of the codes of the video signals of the right and left frames is transmitted over three radio channels by two upper and one lower side frequencies of two carrier frequencies. On the first radio channel, the upper side frequency of the first carrier transmits codes E _RP and E _RL , on the second radio channel, the upper frequency of the second carrier transmits codes E _GP and E _GL , on the third radio channel, the lower side frequency of the first carrier transmits codes E _VP and E _VL . On the receiving side, three radio signals are received in parallel, amplified, detected, the symbols of the code units are converted from half-sine waves to pulses, the codes of the video signals are distributed over their channels, where the samples are doubled in the line and the lines are doubled in the frame, after which the code signals are amplified in pulse amplifiers and received to the radiation modulation unit. Reflectors of two piezoelectric deflectors scan the frame in the focal plane of the projection lens, which projects a 20x magnified image of the frame on a matte screen. The left and right frames are separately observed by the left and right eye of the viewer. Alternating overlapping of the field of view of the eye is performed by a separate observation unit by mechanical rotation of neutral filters of the corresponding density by mechanical meshes. The filters are mounted on an axis that rotates with a resolution of 90 ° and rotates at a frequency of 3.125 r / s according to the control signals from the pulsed LED above the matte screen. To watch stereo broadcasts, glasses are worn over the eyes, against the eye windows of which are left and right cylindrical frames with neutral light filters. The disadvantages of the prototype: the observation of the frames of a stereo pair through mechanically rotating light filters limits the repetition rate of stereo pairs of 12.5 Hz and is dangerous for the viewer’s eyes, viewing a frame with one eye requires increasing the brightness and contrast of the image on the screen.

The purpose of the invention is inertialess control of separate observation of frames of stereo pairs and increasing the brightness of the image on the screen.

, длительность строки на экране приемной стороны 200 мкс, частота повторов 400 строк на приемной стороне 100 раз: 50 повторов 400 нечетных и 50 повторов 400 четных строк.The technical result is the introduction of electronic / inertia-free / separate monitoring of stereo frames and increasing the average brightness of the image on the screen by 40,000 times. The result is achieved by changing the perception of the volumetric image of ZD glasses with an IR receiver on their frame and an IR transmitter on a matte screen and scanning the frame at the same time with 400 odd and 400 even lines with repeating each group of lines for the frame period by 50 times, which allows to increase the average brightness images in 40,000 times / 400 × 100 /. Stereopair frame code information is transmitted over three channels by the side frequencies of the two carrier frequencies. On the transmitting side, 400 lines are encoded in a frame, 600 samples in a line are encoded with 8-bit codes. The clock frequency in the system is 48 MHz. The scan of lines on the transmitting side is line-by-line without reverse moves, line frequency is 20 kHz, frame scan without reverse moves, frame rate is 50 Hz, stereo pair frequency is 25 Hz. The frame duration on the transmitting side and on the receiving side is 20 ms, the line duration on the transmitting side is 50 μs

, the length of the line on the screen of the receiving side is 200 μs, the repetition frequency of 400 lines on the receiving side is 100 times: 50 repeats of 400 odd and 50 repeats of 400 even lines.

Receive line frequency 5 kHz

Between the eyes and the screen are placed electronically controlled ZD glasses [2, p. 588-565], in which the field of view of that eye, the frame of which is absent, is synchronously and in phase with the change of frames.

The essence of the invention is that in a digital stereo television system containing on the transmitting side a photoelectric converter, 1-6 ADCs of a video signal, 1-2 ADCs of a sound signal, a sinusoidal oscillation generator and a frequency synthesizer, three code shapers, two self-propelled pulse distributors, a pulse counter, trigger, two keys and a transmitter of radio signals from three channels, on the receiving side containing an antenna, a control unit, 1-3 paths for receiving and processing codes of video signals, a channel for generating control signals and two channels sound launcher, three pulsed amplifier units, a radiation modulation unit, a first frequency divider, a horizontal scanning unit, a first amplifier and a first piezoelectric deflector with an end reflector, a second amplifier and a second piezoelectric deflector with an end reflector, four reference voltage sources, a projection lens and a matte screen , a second frequency divider, ZD glasses with an IR receiver on the rim of the glasses and an IR transmitter located above the matte screen are introduced, a code storage device is inserted into each channel of the video signal, the radiation modulation unit is made of 400 Anal.

The block diagram of the transmitting side in figure 1, the scan of the raster on the transmitting side in figure 2, the form of the control voltage of the scan in figure 3, the structure of the digital streams from the transmitting side in figure 4, the ADC of the video signal in figure 5, the design of the piezoelectric reflector in figure 2 .6, the encoder of the video signals E _R and E _G in Fig. 7, the encoder of the codes E _B in Fig. 8, the receiving side in Fig. 9, a circuit diagram of a bipolar amplitude detector in Fig. 10, the code processing unit in Fig. 11, the radiation modulation unit in Fig.12, the scan raster on the receiving side on Fig.13, block allocation of horizontal sync pulses in Fig.14, block allocation of sync pulses of stereopairs in Fig.15, the first delay block in Fig.16, the code store in Fig.17, the odd / even / frame code store in Fig.18, block registers on. Fig.19 and 20.

The transmitting side includes / Fig. 1 / photoelectric converter 1, which is a sensor of two images of one object: the right / E _RP , E _GP , E _VP / and left / E _RL , E _GL , E _VL /. The photoelectric converter 1 is part of the transmitting television camera, which includes the first ADC 2 / video signal E _RP /, the second ADC 3 / video signal E _GP /, the third ADC 4 / video signal E _VP /, the fourth ADC 5 / video signal E _RL /, fifth ADC 6 / video signal E _GL /, sixth ADC 7 / video signal E _VL /. The transmitting side includes the first ADC 8 and the second ADC 9 of the sound signal, the inputs of which are _{supplied with} sound signals U sound ₁ and U _{sound 2} , the oscillator 10 of the sinusoidal oscillations, the synthesizer 11 frequencies, the first 12, second 13, third 14 code _generators respectively E _RP and E _RL , E _GP and E _GL , E _VP and E _VL , first 15 and second 16 self-propelled pulse distributors, counter 17 pulses, trigger 18, first 19 and second 20 keys, transmitter 21 radio signals, including three channels. The first channel includes a series-connected amplifier 22 of the first carrier frequency, an amplitude modulator 23 into an output amplifier 24, the second channel includes an amplitude modulator 25 and an output amplifier 26, the third channel includes an amplifier of a second carrier frequency, an amplitude modulator 28 and an output amplifier 29. Each amplitude modulator 23, 25, 28 consists of a series-connected ring modulator and a voice filter [3, p.234], filtering out one of the side frequencies in the spectrum of the amplitude-modulated carrier. ADCs 2-7 / Fig. 5/ are identical, each includes a video amplifier 30 and a piezoelectric deflector 31 with a reflector at the end, a source 32 of a positive reference voltage, a source 33 of a negative reference voltage, an emitter from a pulsed LED 34, a slit diaphragm 35 and a micro lens 36, line 37 multi-element photodetector and encoder 38. All piezoelectric deflectors used in the system are end bimorph piezoelectric elements with a light reflector at the end / Fig.6/, are identical in design [4, p.118] from the first 39 and second 40 piezoelectric plates, int friction electrode 41, the first 42 and second 43 external electrodes. One end of the piezoelectric plates is fixed in the holder 44, the light reflector 45 is located on the free end, the ADCs 2-7 have one conversion principle, which consists in scanning the beam (Fig. 5/) from the LED 34 of the piezoelectric reflector 31 to the plane of the entrance pupils of the photodetector line 37 of the multi-element photodetector, the light pulse is converted into an electrical signal that excites one of the input buses of the encoder 38, which generates a code for the instantaneous value of the input video signal. The conversion is performed with a sampling rate of 12 MHz. The radiation source is a pulsed LED AL402A with a response time of 25 ns, with a margin satisfying a sampling rate of 12 MHz / 83 ns /. Line 37 contains 255 photodetectors for encoding video signals with an 8-bit code. The encoder is represented by K155IV1 microcircuits with a response time of 20 ns [5, p.231], generates codes from 00000001 to 11111111.

The first 12 and second 13 code generators are executed identically / Fig. 7/, each containing a serially connected trigger 46 and a switching unit 47 and three channels. The first and second are identical. The first channel includes a series-connected block of 48 elements And, the first 49, the second 50 elements. OR and an output switch 51, and a self-propelled pulse distributor 52. The second channel includes a second block 53 of AND elements, a third 54 and a fourth 55 elements OR, and an output switch 56, and a self-propelled pulse distributor 57. The third channel includes two blocks 58, 59 of AND elements, the fifth 60 and sixth 61 elements of OR, and two self-propelled distributors 62, 63 pulses, includes the first 64, second 65 keys, serially connected counter 66 pulses and decoder 67. In the first shaper 12 codes the decoder 67 has first and second outputs connected to the corresponding inputs of the keys 64, 65. In the second code generator 13, the decoder 67 has a third output, which is the second output of the code generator 13, connected to the input of the self-propelled distributor 15 pulses / signal U _П / and at go counter 17 pulses. The first and second information inputs are the inputs of the switching unit 47 and the inputs of the blocks 58, 59 of AND elements, the third and fourth information inputs are the third inputs of the second and fourth elements OR 50, 55. The control inputs are: the first is the trigger input 46/12 MHz /, the second - the combined inputs of the counter 66 pulses and keys 64, 65/6 MHz /, the third - the signal inputs of the output keys 51, 56/48 MHz /, the fourth - the control input of the counter 66 pulses / 20 kHz /. The output is the combined outputs of the output keys 51, 56. In the second code generator 13, the second output is the third output of the decoder 67. The third code generator 14 comprises a trigger 68, a switching unit 69, and two channels. The channels are identical. The first includes an AND element block 70, a first 71 and a second 72 OR element, and an output switch 73, and a self-propelled pulse distributor 74. The second channel includes a block of 75 AND elements, a third 76 and a fourth 77 OR elements, and an output switch 78, and a self-propelled pulse distributor 79. The first information input is the inputs of the switching unit 69, the second and third information inputs are the second inputs of the second 72 and fourth 77 OR elements. The first control input is the trigger input 68/12 MHz /, the second is the combined inputs of the self-propelled valves 74. 79 pulses / 6 MHz /, the third is the signal inputs of the output keys 73, 78/48 MHz /, the output is the combined outputs of the output keys 73, 78 .

First, the 12 MHz clock pulses from the output of the first key 19 are supplied to the ADC 2-4, codes of the right frame of the image are issued, in the next frame, the 12 MHz clock pulses from the second key are fed to the clock inputs of the ADC 5-7, codes of the left frame are issued. The units in the codes are represented by the presence of an impulse; zeros by their absence. The first shaper of 12 codes issues from the 1st to 592 codes of video signals E _RП and Е _РЛ , three sound codes, the SSI code / 599th line code /, in the last 400th line of each even frame the SIS code / 600th line count /, Fig. 4. Units in codes of odd samples of a line are represented by positive half-sine waves of mono frequency 48 MHz with stability of 10 ^-7 , units in codes of even samples of a line are represented by negative half-sines of monofrequency 48 MHz. The second shaper 13 codes gives from 1 to 592 codes of video signals E _GP and E _GL , three sound codes, the SSI code and the SIS code. The third forming 14 codes gives out from 1 with 592 codes of video signals E _VP and E _VL , the SSI code and the SIS code.

The operation of the shapers 12, 13 codes / 7, 8 /.

Codes with the ADC 3, 6/2, 5 / arrive in parallel form with a frequency of 12 MHz to the inputs of the block. 47 switching branching stream of codes in 12 MHz into two of 6 MHz: the first stream is the codes of odd samples, the second is the codes of even samples of the line. Block 47 of K176KT1 microcircuits with a response time of 25 ns [7, p. 222]. Alternate connection of the channels to the outputs of block 47 is performed by a trigger 46, at the input of which 12 MHz pulses are received. At the second inputs of the elements AND blocks 48, 53, eight pulses are received from the self-propelled distributor 52 and 57. From the outputs of the elements AND blocks 48, 53, the pulses of the codes are opened sequentially through the OR elements 49, 50 and 54, 55 for the duration of their duration / 20.8 ns / output keys 51 and 56. The signal inputs of the keys 51, 56 receive 48 MHz sine waves. The output key 51 in the open state passes one positive sine wave, the key 56 in the open state passes one negative sine wave. At the output of the code generator, the units in the codes of odd samples are represented by positive half-sine waves, in the codes of even samples by a line, they are represented by negative half-sines. Zeros appear to be the absence of both. The output signal at the output of the code generator is either a full 48 MHz sine wave or an incomplete sine wave of the same frequency. These signals modulate the carrier frequencies: from the shaper 12, the first carrier frequency in block 23, from the shaper 13, the second carrier frequency in block 28 of the transmitter, and from the shaper 14, the first carrier frequency in block 25. The sound code consists of two 8-bit packets. The first package of 1-8 bits is fed to the first inputs of the AND elements of block 58 and through the OR elements 60, 50 to the input of the output key 51, the second package of 9-16 bits goes to the first inputs of the AND elements of block 59 and through the OR elements 61, 55 to the input output key 56. The keys 64, 65 are designed to separate the sound codes from the video signal codes. At the moment of the 300th pulse of line sampling / 599 line count /, the SSI code / 11111111 / from block 15 is supplied to the third input of the OR element 50, which is triggered by the signal U _P from the third output of the decoder 67, issued at the moment 299 of the line sampling pulse of Fig. 4 . With the last 400th line in an even frame, the second self-propelled distributor of 16 pulses gives the SIS code / 11111111 / for 600 line counts to the third input of the OR element 55 at the time of the 300th pulse of line sampling. The start signal for block 16 gives the counter 17 pulses / fig .1 / s counting cycle, two pulses. The counter 17 is reset to zero by a signal of U _O 25 Hz from the 6th output, of a synthesizer of 11 frequencies. The counter 17 pulses receives two pulses from the second shaper 13 codes, the second pulse corresponds to the end of an even frame / 299 sampling pulse of the last line of an even frame /. The second pulse starts the self-propelled distributor of 16 pulses. The SIS code is the 600th count of the last line only in an even frame. The process of the third shaper 14 codes is similar to the work of the shaper 12 codes, it does not generate sound codes.

The receiving side (Fig. 9/) contains an antenna, a control unit 80, first, second, third paths for receiving and processing video signal codes, a channel for generating control signals and two sound reproduction channels. The first path for receiving and processing codes of video signals receives and processes codes E _RП and Е _РЛ and includes serially connected radio signal receiving unit 81, radio frequency amplifier 82 and bipolar amplitude detector 83, first 84 and second 85 pulse shapers, and a video signal channel including first 86 and a second 87 registers, a code processing unit 88, a first delay unit 89, an adder 90, a second delay unit 91, and a code accumulator 92. The second path for receiving and processing codes of video signals receives and processes codes E _VP and E _VL and includes serially connected unit 93 for receiving a radio signal, an amplifier 94 for radio frequency and a bipolar amplitude detector 95, a first 96 and a second 97 pulse shapers, and a channel for a video signal including the first 98 and a second 99 registers, a code processing unit 100, a first delay unit 101, an adder 102, a second delay unit 103 and a code accumulator 104. The third path for receiving and processing codes receives and processes codes E _GP and E _GL , includes serially connected radio signal receiving unit 105, radio frequency amplifier 106 and bipolar amplitude detector 107, first 108 and second 109 pulse shapers, and a video signal channel including the first 110 and second 111 registers, code processing unit 112, first delay unit 113, adder 114, second delay unit 115 and code storage 116. The receiving side includes the first 117, the second 118, the third 119 blocks of pulse amplifiers, the radiation modulation unit 120, the first frequency divider 121/8: 1 /, the horizontal scanning unit 122 from the master oscillator 123 and the output stage 124, the first amplifier 125 and the first a piezoelectric deflector 126 with a reflector at the end, a first source of positive reference voltage 127, a second source of negative negative voltage 128, a second frequency divider 129/8: 1 /, a second amplifier 130 and a second piezoelectric deflector 131 with a reflector at the end, the third source to 132 positive reference voltage, a fourth source of negative reference voltage 133, a projection lens 134 and a matte screen 135, above which an IR transmitter 136, an IR receiver 137 on the rim of the ZD glasses 138 are located. The receiving side is controlled by a channel for generating control signals, including a sequentially connected block 139 selection of horizontal sync pulses / SSI /, a frequency synthesizer 140, serially connected key 141, a counter 142 pulses and a decoder 143, and a block 144 allocation of sync pulses of stereo pairs / SIS /. The receiving side includes first 145 and second 146 identical sound reproduction channels.

Blocks 88, 100, 112 of the code processing are identical / 11 /, each includes a trigger 147, the first 148, the second 149, the third 150, the fourth 151 registers, the first 152, the second 153 and the third 154 delay blocks, the fifth 155 and sixth 156 registers , adder 157 and 16 diodes. The first block 152 delays the codes by 10 ns, the second block 153 delays the codes by 93 ns / 83 + 10 / to restore the even codes of the line to be odd / before that they went in parallel /, the third block 154 delays the codes by 17.6 ns / 41.6-24 /. Registers 155, 156 operate storing codes 83 ns and outputting them in the form of parallel U _vyd corresponding output signal from the flip-flop 147. The first and second data inputs are inputs of blocks 152, 153 delay. The output is the combined bitwise outputs of the fifth 155, sixth 156 registers and the outputs of the block 154 delays. The control input is the input of the trigger 147, combined with the control input of the adder 157.

The cure modulation unit 120 (Fig. 12/) is made up of 400 channels, each of which includes a sequentially arranged emitter 158 of three primary colors, a micro lens 159 and a focusing cone of the optical fiber 160 — a focon [6 p.77]. The inputs of block 120 are the inputs of emitters 158 _1-400 connected to the outputs of the blocks of pulse amplifiers 117, 118, 119, the outputs are the radiation 400 of the output windows of the focons 160 _1-400 . Micro lenses 159 introduce the radiation of emitters 158 into the input windows of the focons 160. The output ends of the 400 focons form a vertical ruler, and their output windows are projected onto the piezoelectric reflector reflector 131 / 12/400 color circles, each 0.02 mm in diameter. The output windows of the focons are arranged vertically in increments of 0.02 mm, and the projections of the circles on the reflector are arranged in increments of 0.02 mm. When scanning 400 lines from left to right, the circles of radiation of the odd lines of the raster are projected by focons on the reflector of the piezoelectric deflector 131, while scanning the lines 400 from right to left, the reflector of the piezoelectric deflector 131 is shifted vertically by a step of 0.02 mm with an inclination by the control signal from amplifier 130 (Fig. 9/) down so that the circles of radiation of even lines are projected by focons 160 in the spaces between the circles from odd lines / 12 /.

The length of the piezoelectric reflector 131 reflector is 16 mm / 800 _lines × 0.02 mm /. The radiating plane of the emitter 158 is located in the rear focal plane of the micro-lens 159, in the front focal plane of which the input window of the focal plane 160 is located. The radiating sides of the emitters 158 _1-400 through the lenses 159 _1-400 , focons 160 _1-400 , the reflector of the piezoelectric reflector 131 are optically connected to the reflector piezoelectric deflector 126. Each emitter 158 is a matrix of 24 LEDs, consisting of 8 LEDs of red radiation, 8 - green and 8 blue radiation. The free end face with the reflector of the piezoelectric deflector 131 performs oscillatory movements with an amplitude of 0.02 mm along the control pulse from the amplifier 130, which generates control signals by amplitude and duration, the frequency of the control signals is 2.5 kHz. Block 129 produces a frequency division of 20 kHz 8: 1, 2.5 kHz pulses and a duration equal to a line duration of 200 μs / meander waveform / are received at the input of amplifier 130. The piezoelectric deflector 126 performs a horizontal scan of 400 lines from left to right and 400 lines from right to left. A frequency divider 121 performs a division of the frequency of 20 kHz 8: 1. The input of the master oscillator 123 in the block 122 horizontal scanning receives pulses of 2.5 kHz. Block 123 generates control rectangular pulses with a period of two lines, 400 μs / 200 μs × 2 /, which enter the output stage 124, which generates a triangular-shaped control voltage / FIG. 13/ with a period of 400 μs, which is input to an amplifier 125 amplifying control voltage to the required value, which is supplied to the internal electrode 41 / FIG. 6/ of the piezoelectric deflector 126. Corresponding reference voltages are supplied to the external electrodes 42, 43 from the first 127 and second 128 reference voltage sources. The end face of the piezoelectric deflector 126 with a reflector comes into vibrational motion [4, p.122] with a frequency of 2.5 kHz and scans 400 lines simultaneously odd from left to right and 400 even lines when the reflector moves from right to left. For a frame period of 20 ms, the piezo-deflector 126 performs 100 repeats of sweeps of 400 lines each: 50 sweeps from left to right of odd lines and 50 sweeps of a sturava of null-even lines. The piezoelectric reflector is located in the rear focal plane of the projection lens 134, which is wide-angle. The matte screen 135 is located in the outer focal plane of the projection lens 134 projecting onto the image screen 135 successively the right and left frames of the stereo pair. The image from the screen is perceived by the viewer as voluminous through ZD-glasses 138 [2, p. 588-565]. When playing the right and left frames, the glasses of the ZD glasses alternately lose transparency, each eye sees only its own frame, which gives a stereo effect. The glasses of the ZD glasses are made using the technology of LCD cells of the translucent type, used as electronically controlled filters / shutters /. With the arrival of the stereo pulse clock / SIS / 25 Hz and the IR transmitter 136, it emits an IR pulse of 20 ms duration, the frame duration received by the IR receiver 137 (Fig. 9/), located on the frame of the ZD glasses. The IR receiver provides a control signal to the LCD cell of the left glass, dimming it for 20 ms, then it outputs a second control signal to the LCD cell of the right glass, dimming its transparency for 20 ms. Each eye sees its frame. The transparency of the LCD cells in the open state is much less than 100%, hence the need to increase the brightness of the image on the screen 135. For this purpose, a frame scan on the screen is applied at the same time with 400 lines, repeating them 100 times per frame. The average image brightness for the viewer increases by 40,000 times / 400 × 100 /. Block 139 selection of horizontal sync pulses / FIG. 14/ includes the first 161, second 162, third 163 pulse counters, the first 164, second 165 elements AND, the first 166, second 167, the third l68 elements NOT and a diode. The information inputs of the block are the counting inputs of the pulse counters. The output is the output of the second element And 165. With the arrival of three codes from the same units 11111111 at the output of the information block 139, a horizontal sync pulse / SSI / appears, the frequency is 20 kHz. Block 144 allocation of clock pulses of stereopairs SIS / Fig.15/ includes the first 169, second 170, third 171 pulse counters, the first 172, second 173, third 174 And elements, the first 175, second 176, third 177 elements NOT and a diode. With the arrival of three codes 11111111 and a horizontal sync pulse from block 139 to the counting inputs, a stereo pair clock appears at the output of block 144, this is a 600 count in the last line in each even frame on the transmitting side, their frequency is 25 Hz. The first delay blocks 89, 101, 113 are identical, each includes / FIG. 16/ element and 178, the first 179 and second 180 keys, the first 181 and second 182 pulse distributors, eight registers 183 _1-8 , each of which contains 1200 bits to place signals in them on one bit of an 8-bit code of 1200 line samples. Blocks 89, 101, 113 delay the codes of each line by a line duration of 50 μs.

Drives 92, 104, 116 codes are identical (Fig.17/, each includes a key 184, trigger 185, drive 186 codes of an odd frame / right /, drive 187 codes of an even frame / left /. The first and second information inputs of blocks 92, 104, 116 are the bitwise combined first 1-8 and second 1-8 inputs of the drive 186 and 187 connected to the outputs of blocks 90 and 91/102, 103 and 114, 115 /, respectively. The control inputs are: the first is the signal input of the key 184, the second is the control input of the key 184, the third is the combined second control inputs of the drives 186, 187, the fourth is the combined third control inputs of the drive 186 codes and 187. The first control input of the drive 186 of the odd-frame code is connected to the first output of the trigger 185, the first control input of the drive 187 codes of an even frame is connected to the second output of the trigger 185. The outputs of the blocks 186, 187 are bitwise combined and are 1-3200 outputs of the drive of codes 92/104, 116 /, connected to the input Ladies unit 117/118, 119 / pulse amplifiers. The accumulator 186 of the codes of the odd frame and the accumulator of 187 codes of the even frame are identical / Fig. 18/. Each includes the number of lines blocks 188 _1-400 registers. The first and second information inputs of block 186/187 / are the first 1-8 and second 1-8 inputs connected to the outputs of blocks 91 and 90. Block 186 accumulates codes of odd frames, block 187 accumulates codes of even frames.

Blocks 188 _1-400 registers are identical / 19, 20 /, each includes the first 189, second 190, third 191, fourth 192 keys, first 193, second 194, third 195, fourth 196 pulse distributors, the first eight registers 197 _{1- 8} , the first pulse counter 198 and the first decoder 199, the second eight registers 200 _1-8 , the second pulse counter 201 and the second decoder 202, and the trigger 203. The first and second information inputs of block 188 are the bit / first / bit information inputs of the first eight registers 197 _1-8 and the combined bitwise first / information data / inputs of bits of the second eight registers 200 _1-8 . The outputs of the bits in each register are combined and are 1-8 outputs of the block 188 registers. There are four control inputs: the first is the combined first control inputs of the first 189 and third 191 keys connected to the first output of trigger 185 in block 92, the second is the combined signal inputs of the second 190 and fourth 192 keys connected to output 1 of the 140/6 MHz block, the third is the combined signal inputs of the keys 189, 191 connected to the output 7 of the block 140/24 MHz /, the fourth is the combined first control input of the key 190, the second control input of the key 192 and the second output of the trigger 203 connected through the diode to the first control output of the block 188 ₄₀₀ re histres.

The clock frequency in the system is:

where 400 is the number of lines encoded on the transmitting side,

50 Hz - frame rate, 400 × 50 = 20 kHz line frequency,

- число пар отсчетов в строке при двухполярной передачи кодов /фиг.4/,

- the number of pairs of samples in a row during bipolar transmission of codes / 4 /,

8 _bits - the number of bits in the code.

The photoelectric converter 1 generates six analog video signals of two images following each other. The photoelectric converter 1 and six ADCs are structurally placed in a transmitting chamber, the output of which are six binary codes of video signals: the right image E _RP , E _GP , E _VP and the left image E _RL , E _GL , E _VL . ADCs convert analog video signals to 8-bit codes. Alternate issuance of codes with ADCs 2, 3, 4 and ADCs 5, 6, 7 is performed by trigger 18 and keys 19 and 20. Pulses of 50 Hz from the tenth output of synthesizer 11 frequencies are input to trigger 18, the signal from the first output of which opens the first key 19 transmitting 12 MHz pulses for 0.02 s / 20 ms / of the first frame to the clock inputs of the ADC 2, 3, 4, the codes of which are transmitted to the drivers 12, 13, 14 of the code during the frame. The ADCs 5, 6, 7 do not issue codes; 12 MHz pulses are not passed to their clock inputs. With the arrival of the second pulse of 50 Hz to the trigger 18, the key 19 is closed, the second key 20 is opened, which during the period of the second frame 20 ms passes 12 MHz pulses to the ADC clock inputs 5, 6, 7, the codes from which are supplied to the drivers 12, 13, 14. Code generators convert parallel codes into serial ones and replace the representation of units from pulses with positive and negative half-sinusoids of the 48 MHz monofrequency from a synthesizer of 11 frequencies. The master oscillator 10 generates sine waves with a stability of 10 ^-7 . A frequency synthesizer 11 generates and issues: from the first output, 12 MHz pulses to the ADC 2-7 clock inputs and to the first control inputs of code generators 12, 13, 14, from the second output 6 MHz pulses to the second control inputs of blocks 12, 13, 14 and to the first control inputs of the ADC 8, 9, from the third - 60 kHz pulses to the second control inputs of the ADC 8, 9, from the fourth output sinusoidal oscillations of 48 MHz to the third control inputs of blocks 12, 13, 14, from the fifth output pulses of 20 kHz to the fourth control inputs of blocks 12, 13, to the first input of the photoelectric converter 1 and to the third control inputs of the ADC 8, 9, from the sixth - 25 Hz pulses to the second input of the photoelectric converter 1, to the control input of the counter 17 pulses / U _O /, from the seventh - 10 kHz pulses to the third input of the photoelectric converter 1, from the eighth - sinusoidal oscillations of 480 MHz of the first carrier frequency to the amplifier 22, from the ninth output, sinusoidal oscillations of 576 MHz of the second carrier to the amplifier 27 of the second carrier, from the tenth output, 50 Hz pulses to trigger 18. The ADCs 8, 9 convert the sound signals into 16-bit codes, which go to the second and formational inputs formers 12 and 13 codes. A self-propelled distributor of 15 pulses with the arrival of a U _P start signal from the second output of block 13 gives a code of eight units 11111111, which is the SSI code / 599th count of each line / to the third information inputs of blocks 12, 13 and to the second information input of block 14. Self-propelled distributor 16 with the arrival of the signal pulses _P U starting from the second output of the pulse counter 17 outputs a code of eight units being sync stereopair SIS / 600th count of the last row of each even frame / to the fourth information inputs of blocks 12, 13 and the third and formational input unit 14. The two-bit counter 17, outputs the output from the second discharge signal U _n to the block 16 with the arrival of the second pulse it from the second output driver 13 codes, then reset pulse 25 Hz.

The spectrum of the amplitude-modulated signal consists of a carrier and two side frequencies. One of the side frequencies and the carrier frequency itself in the information sense are redundant, therefore, in each amplitude modulator, the carrier frequency is suppressed and one of the side frequencies is filtered out. The amplitude modulator 23 outputs to the output amplifier 24 an upper side frequency of 528 MHz from the first carrier of 480 MHz. The amplitude modulator 25 outputs to the input of the output amplifier 26 a lower side frequency of 432 MHz from the first carrier. Amplitude modulator 28 outputs to the input of amplifier 29 an upper side frequency of 624 MHz from a second carrier frequency of 576 MHz. The receiving side receives three radio signals, amplifies them, detects half-sine waves based on the polarity sign, separates the codes by video signal channels, selects horizontal sync pulses and stereo pair clock pulses, generates two carrier frequencies, separates audio signal codes, doubles the number of samples per line from 600 to 1200, doubles the number of lines in the frame from 400 to 800, performs luminance modulation of the radiation of 400 emitters / simultaneously 400 lines / and reproduces the right and left image frames on the matte screen.

Three radio signals are received by blocks 81, 93, 105 (Fig. 9/) of receiving a radio signal, which are selectors of decimeter band channels / ACS / with electronic tuning, and receive radio signals in the range 430-790 MHz. Each unit includes an input circuit, a radio frequency amplifier, and a mixer [8, p.132, Fig. 4.2] An amplified radio frequency signal through a communication loop [8, p.132] is fed to the mixer emitter, and a frequency equal to the carrier is supplied here from the frequency synthesizer 140 on the transmitting side, necessary for detecting a single-band signal [9, p.146]. The output signal from block 81/93, 105 / is fed to the input of the amplifier 82/94, 106 / of the radio frequency, where it is amplified to the required value and fed to the input of a bipolar amplitude detector 83/95, 107 /. The second inputs of the frequency synthesizer 140 are connected to the second group of outputs of the control unit 80.

After the transmission channel is turned on in block 80, the voltage from the corresponding output of the control unit 80 determines the output of two frequencies from the frequency synthesizer 140 to the third inputs of blocks 81, 93 and block 105 / the first carrier frequency is output 5, the second is output 6 in block 140 /. Bipolar amplitude detectors 83, 95, 107 are made according to the scheme in figure 10. Diode D1 selects the positive envelope of the modulating signal, diode D2 already selects the envelope of the positive half-sine wave / unit symbols in the codes of odd samples / diode D3 from the modulating selects the envelope of the negative half-sinusoid / unit symbols in codes of even samples /. From the first output, the detected positive half-sine waves with a frequency of 48 MHz are fed to the input of the first driver 84/96, 108 / pulses, from the second output, the detected negative half-sine waves are fed to the input of the second driver 85/97, 109 / pulses. The pulse shapers are made according to the scheme of an asymmetric trigger with emitter coupling [10, p.209], which forms rectangular pulses from harmonically changing signals. The pulses from the formers have one polarity and a duration equal to the pulse duration in the codes on the transmitting side. Units in codes are represented by the presence of an impulse, zeros by their absence. After turning on the power in the receiving side, the keys are all closed, the operating procedure is determined by control signals from the channel for generating control signals from blocks 139, 140, 143 and 144. The deciding role belongs to block 139 for selecting horizontal sync pulses. The condition for the appearance of the SSI from block 139 is the simultaneous arrival of eight codes from eight units into it from three shapers 84, 96, 108. In all codes, except for 599 counts, one or more zeros will be present, especially in three codes at the same time. For each zero in the code, the NOT elements (Fig. 14/) will reset the counters in block 139. With the arrival of three codes 11111111, block 139 generates an output pulse, which is an SSI whose frequency is 20 kHz / line frequency on the transmitting side /. The SSI opens the key 141, is fed to the input of the sterepair clock allocation section 144 and to the first input of the frequency synthesizer 140. At the SSI pulse, the frequency is synchronized in the synthesizer 140 frequencies, whose own frequency stability is 10 ^-6 . The frequency and phase of the master oscillator 10 of the transmitting side are tuned along the leading edge of the SSI from block 139. Frequency synthesizer 140 produces: 6 MHz pulses from the first output, 48 MHz clock pulses from the second output, and 60 kHz pulses from the third output to output sound codes to sound reproduction channels, from the fourth - 12 MHz pulses to the control inputs of the code processing blocks 88, 112, 100, from the fifth and sixth - sinusoidal oscillations of the two required carrier frequencies respectively of the received transmission channel to the third inputs of the blocks 81, 93, 105, s of the first output, 24 MHz pulses to the first delay blocks 89, 113, 101, to the control inputs of adders 90, 114, 102 and to the third control inputs of drives 92, 116, 104 codes, from the eighth - 50 Hz pulses to blocks 89, 113, 101 delays and the fourth control inputs of drives 92, 116, 104 codes. The code of the odd count of the video signal E _R from the output of the pulse shaper 84 is supplied in sequential form to the first register 86, filling its bits, the code becomes parallel. The code of the even count of the video signal E _R from the output of the pulse shaper 85 is received in serial form in the register 87 and also takes a parallel form. Codes also go through the same process with the shapers 96, 97, 108, 109. The codes are sent from the registers to the blocks 88, 112, 100 and the code is processed by 6 MHz pulses from block 140; they also reset the registers before receiving the next code. Blocks 88, 100, 112 of the code processing double the samples in the thirst line by obtaining intermediate samples / average value / between each passing code and the next one. In blocks, the previous and subsequent codes are added and the sum code is divided in half / by 2 /. Each code is used twice: the first time as the next, the second time as the previous one, therefore the block 88/112, 100 / contains four registers 148, 149, 150, 151/11 /. The odd first code from register 86 enters through the first delay block 152 to register 148, 149. The even code from register 87 enters through the second delay block 153 to registers 150, 151. Block 152 delays the code by 10 ns so that it does not overlap the incoming into the registers 148, 149 code and issued from them. Block 153 delays the codes by 93 ns: 83 ns are required to restore the sequence of the even code following the odd / the second should follow the second / and 10 ns as well as block 152. With the arrival of the first 12 MHz pulse to the input of the trigger 147, the pulse U _vy1 with its the first output gives the code "code 0" from the second register 149 to the first inputs of the adder 157 and "code 0" from the register 150 to the sixth register 156 / for delaying the code by 83 ns / and through diodes to the second inputs of the adder 157. Registers 148, 149 filled in with the first incoming code "code 1". The adder 157 tracks the codes code 0 + code 0, is made of K555IM6 microcircuits [5, p. 258] with an addition time of 24 ns. At the end of the addition, the adder 157 is reset to zero by the pulse U _О ; it also issues a sum code to the output of the adder. The division of the sum code by two is performed by shifting the sum code by one bit so that the least significant bit of the sum code is discarded / as dividing the decimal code by ten /. The shift is performed instantly by the corresponding connection of the outputs of the adder to the inputs of the third block 154 delays:

Bit 0 means transfer to the high bit when the sum of codes. After doubling the samples in the line from 600 to 1200, the period of the codes is 41.6 ns / 11 /. The addition process takes 24 ns; therefore, block 154 should delay the code by 17.5 ns / 41.6-24 /. After the codes arrive at the adder, the code exits block 154 after 41.6 ns, which is required.

.After 41.6 ns, a code goes from block 154

.

следует на выход.With the arrival of the second pulse to the input of the trigger 147, from the second output of the trigger, the signal U _vy2 generates from code six sixth register 156 code No. 2 "code 0", which was stored in it 83 ns, but the first half of the storage is 41.5 ns during the addition and delay in block 154, therefore, code No. 2 "code 0" from register 156 follows code No. 1 after 41.5 ns. The signal U _vyd2 issues from the register 151 to the adder 157 "code 0", from the register 148 gives the "code 1" through diodes to the adder 157 and directly to the register 155 for storage. The freed-up registers 150 and 151 are filled with the following code "code 2", in addition there is addition in the adder code 0 + code 1, division by 2, and code No. 3

should exit.

идет на выход. С приходом четвертого импульса в триггер, с его выхода сигнал U_выд2 /он же U_выд4/ выдает с регистра 156 код №6 "код 2", с регистра 148 "код 3" в сумматор и в блок 155, и "код 2" с регистра 151 в сумматор. Освободившиеся регистры 150, 151 заполняются кодом "код 4". Идет сложение код 2 + код 3, деление пополам, и код №7

идет на выход. С приходом 5-го импульса в триггер 147, сигнал U_выд1 /он же U_выд5/ выдает с регистра 155 код №8 "код 3", выдает "код 3" с регистра 149 в сумматор 157 и "код 4" с регистра 150 в регистр 156 и через диоды в сумматор 157. Следует заполнение регистров 148, 149 следующим кодом "код 5". Идет сложение код 3 + код 4, деление на 2, код №9

идет на выход. С приходом шестого и следующих импульсов в триггер 147 процессы аналогично повторяются. Выходы регистров 155, 156 и третьего блока 154 задержек поразрядно объединены и являются выходом блока 88 /100, 112/. С выходов блоков 88, 100, 112 коды поступают параллельно на входы блоков соответственно 86 и 91, 101 и 103, 113 и 115. Первый блок 89 /101, 113/ задержек выполняют задержку кодов строки на длительность строки 50 мкс и участвует в формировании отсчетов промежуточных строк. Так как развертка нечетных и четных строк в растре идет встречно /фиг.16/, то для получения нечетных промежуточных строк нужно выдавать коды в сумматор 90 в последовательности с последнего кода /1200/ в строке к первому, а при получении четных промежуточных строк выдавать коды с блока 89, начиная с 1-го кода строки к последнему. При развертке первой строки растра в блоке 89 открывается первый ключ 179, импульсы двойной частоты 24 МГц дискретизации поступают в первый распределитель 181 импульсов, выдающие тактовые импульсы с первого по 1200 на первые управляющие входы, начиная с первых разрядов регистров 183_1-8 к 1200-му, регистры 183 заполняются кодами первой строки: первые разряды кодов поступают в регистр 183₁, вторые разряды кодов поступают в регистр 183₂, третьи в регистр 183₃ и т.д. восьмые разряды поступают в регистр 183₈. Импульс с последнего 1200 выхода распределителя 181 закрывает ключ 179, открывает ключ 180.With the arrival of the third pulse in the trigger 147, the signal U _vyd1 / aka U _vyd3 / gives code No. 4 "code 1" from register 155, issues "code 1" from register 149 to the adder and "code 2" from register 150 to the adder 157 and in register 156 deposited. The freed registers 148, 149 are filled with the code "code 3". Addition follows in the adder code 1 + code 2, then division by 2, and code No. 5

goes to the exit. With the arrival of the fourth pulse in the trigger, from its output the signal U _out2 / also U _out4 / gives code No. 6 "code 2" from register 156, from code 148 "code 3" to the adder and to block 155, and "code 2" from register 151 to the adder. The freed registers 150, 151 are filled with the code "code 4". There is addition code 2 + code 3, halving, and code number 7

goes to the exit. With the arrival of the 5th pulse in trigger 147, the signal U _vyd1 / aka U _vyd5 / gives code No. 8 "code 3" from register 155, issues "code 3" from register 149 to adder 157 and "code 4" from register 150 to the register 156 and through diodes to the adder 157. The registers 148, 149 should be filled with the following code "code 5". Adding code 3 + code 4, dividing by 2, code number 9

goes to the exit. With the arrival of the sixth and subsequent pulses in the trigger 147, the processes are similarly repeated. The outputs of the registers 155, 156 and the third delay block 154 are bitwise combined and are the output of the block 88/100, 112 /. From the outputs of blocks 88, 100, 112, the codes are sent in parallel to the inputs of the blocks 86 and 91, 101 and 103, 113 and 115, respectively. The first block of 89/101, 113 / delays delays the line codes by a line duration of 50 μs and participates in the formation of samples intermediate lines. Since the scanning of odd and even lines in the raster is counter-running / Fig.16/, to obtain odd intermediate lines you need to issue codes to the adder 90 in the sequence from the last code / 1200 / in the line to the first, and if you get even intermediate lines, give the codes from block 89, starting from the 1st code of the line to the last. When scanning the first line of the raster in block 89, the first key 179 opens, pulses of a double frequency of 24 MHz sampling arrive at the first distributor 181 pulses, issuing clock pulses from the first to 1200 to the first control inputs, starting from the first bits of registers 183 _1-8 to 1200- mu, registers 183 are filled with the codes of the first line: the first bits of codes go to register 183 ₁ , the second bits of codes go to register 183 ₂ , the third to register 183 ₃ , etc. eighth digits are entered in the register 183 ₈ . The pulse from the last 1200 output of the distributor 181 closes the key 179, opens the key 180.

The input of the second distributor 182 pulses received pulses of 24 MHz. The outputs from the distributor 182 pulses are connected to the first control inputs of the bits of the registers 183 _1-8 in the reverse order, the first output is connected to the last 1200th bits, the last output is connected to the first bits of the registers. When scanning the second line, pulses from the outputs of the distributor 182 pulses give the second inputs of the adder 90 codes delayed by 50 μs of the first line in the sequence from 1200 to the first code, respectively, following the samples when the second current line of the frame is scanned. An adder 90 forms a first intermediate line. The freed bits of the registers 183 are filled with the codes of the second / current / line in the order from 1200 to the first. The pulse from the last output of / 1200 / distributor 182 closes the key 180 and opens the key 179. There follows a scan of the third current line, in which the codes of the second line are issued from registers 183 to the adder 90, starting from the first code to the 1200th. The adder 90 forms a second intermediate line. Next, the processes are repeated. The codes from the outputs of the adders 90, 114, 102 are codes 400 intermediate lines. The second delay blocks 91, 115, 103 perform the delay of the codes of the current lines 400 for a time of 24 ns, this is the response time of the adders so that the codes of the current and intermediate lines arrive at the inputs of the drives 92, 116, 104 codes synchronously. As adders, K555IM6 microcircuits are used.

The operation of the drives 92, 116, 104 codes / Fig.17, 18 /. To scan the first frame, a 25 Hz SIS clock from an SIS extraction block 144 opens a key 184 in the drive 92 for the receiver side to work, and a 50 Hz frame pulse belonging to the right frame of the stereo pair enters the trigger input 185, from the first output of which it starts the drive 186 odd frame codes. With the arrival of the second pulse of 50 Hz in the trigger 185, the signal from the second output of the trigger starts the drive 187 codes of an even frame. In block 186, the codes of each odd frame are concentrated; in block 187, the codes of each even frame are concentrated. Blocks 186, 187 each / FIG. 18/ includes 400 blocks 188 _1-400 registers, which, in turn, each includes eight first registers 197 _1-8 and eight second registers 200 _{1-8 /} FIG. 19/. In the first period of the frame, block 186 accumulates codes of 800 lines of the first frame, in the second period of the frame, codes of 400 odd lines and then 400 even lines follow from all blocks of registers 188, and their output is repeated up to 50 times each. At the same time, in the period of the second frame, block 187 accumulates 800 line codes of the second frame. In the third period of the frame, the codes from block 187 are issued, and codes of 800 lines of the third frame are accumulated by block 186. Thus, the processes are repeated.

Blocks 188 registers works as follows / Fig.19/.

In the initial state, all keys in the block 188 registers are closed. With the arrival of the first frame pulse of 50 Hz at the input of trigger 185 from the first output of trigger 185, the pulse opens the first key 189 / Fig. 19/ and the third key 191, which pass the frequency of 24 MHz to the pulse distributors 193, 195. From the outputs of these blocks, 24 MHz clock signals are sequentially fed to the first control inputs of the bits of registers 197 _1-8 and 200 _1-8 , the first / information / inputs of which are fed with the signals of line codes from blocks 91 and 90. The registers 197 are filled with codes of current lines with block 91, and the registers 200 are filled with codes of intermediate lines from the adder 90. At the end of the period of the line registers 197 and 200 are filled with 1200 codes of the first line. The pulse from the 1200th output of block 193 closes the key 189 and is the first control output to the next block 188 ₂ , the signal of which opens the same keys 189, 191 in the second block 188 _{2 /} Fig. 20/, and it follows the identical process of filling with codes the second line of registers 197, 200. Likewise, codes 3 ... 800 are filled with lines of registers 197 and 200 in blocks 188 _3-400 . As a result, block 186 focuses codes 800 lines of the first frame. When the second frame pulse / 50 Hz / pulse from the second output of the trigger 185 arrives at the input of trigger 185 / Fig.17/, the keys 189, 191 in block 188 ₁ in the drive 187 of the codes of an even frame open and the identical processes of accumulating 800 line codes go there second frame.

, где 20000 мкс - длительность кадра, 100 - число повторов развертки 400-ми строками. Делитель 121 частоты выполняет деление 8:1 частоты 20 кГц. На вход задающего генератора 123 /фиг.9/ поступает частота 2,5 кГц. Развертка, всех строк за кадр выполняется 100 раз: 50 раз слева направо и 50 раз справа налево. Повторы по 50 раз задаются счетчиками 198, 201 /фиг.19/ и дешифраторами 199, 202. В конце каждой строки сигнал с 1200 выхода блока 194 /196/ в качестве счетного импульса поступает в счетчик 198 /201/. После 50 разверток счетчик формирует код 110010, дешифрируемый дешифратором 199 /202/, выходной сигнал с которого обнуляет разряды регистров 197, 200, подготавливая их к заполнению кодами следующего кадра. Смену последовательности выдачи кодов от строки к строке задает триггер 203. Вход его через диоды подключен к 1200-м выходам блоков 194, 196. Первый выход триггера 203 подключен к второму управляющему входу ключа 190 и первому управляющему входу ключа 192, второй выход триггера подключен к первому управляющему входу ключа 190 и к второму управляющему входу ключа 192. Каждый накопитель 92, 116, 104 кодов выдает в параллельном виде одновременно по 400 строк с 1-3200 выходов /400 × 8/ на входы блоков 117, 118, 119 импульсных усилителей. Блоки 117, 118, 119 включают по 3200 импульсных усилителей каждый с временем срабатывания 18 нс, микросхемы 533АП6 [5 c.128]. Выходы импульсных усилителей подключены к своим излучателям 158_1-400 в блоке 120 модуляции излучения. Для излучения каждый светодиод запитывается импульсным сигналом со своего импульсного усилителя. 400 излучателей содержат 9600 светодиодов /400×24/. Блок 120 выполняет яркостную модуляцию излучений, преобразуя коды трех цветовых сигналов в соответствующие по яркости мгновенные излучения излучателей /фиг.12/. В излучателях используются светодиоды типа HL МР компании "Хьюлетт-паккард" [11 с.71]. Для красного излучения применяются светодиоды HL MP-AL 00 с силой света 0,4 кд, длиной волны 0,59 мкм при токе 0,02 A, [11 c.71], для зеленого - светодиоды HL MP-AM 00 с силой света 0,8 кд длиной волны 0,526 мкм при токе 0,02 А, для синего излучения светодиоды HLMP-AB00 с силой света 0,3 кд длиной волны 0,475 мкм при токе 0,02 А. Яркостная модуляция излучений выполняется включением на излечение числа светодиодов в излучателе соответственно весам разрядов по таблице 1.At the same time, the signal from the control output 1 of block 188 _{400 of the} drive 186 of the odd-frame code 186 arrives in parallel to the fourth control inputs of all blocks 188 _1-400, opens the keys 190 and 192, which transmit signals U _output 6 MHz to the inputs of the pulse distributors 194, 196 block 140. The outputs of block 194 are connected to the second control inputs of the bits of the registers 197 in the sequence from 1 to 1200. Sweep 400 odd lines from left to right, codes are issued simultaneously from the registers 197 of all blocks 188 of _1-400 registers. When the piezoelectric reflector reflector 126 is rotated backward / from right to left / 400 even lines are scanned, codes are issued from all blocks 188 _1-400 from registers 200 _1-8 . Codes are issued starting from the last 1200 bits of the registers to the first bits. The outputs of the distributor 196 pulses are connected to the second control inputs of the bits in the registers 200 in the reverse order: the first output is connected to the last 1200th bits in the registers, and the last output / 1200 / is connected to the first bits / Fig. 19, 20 /. Line Duration 200 μs

, where 20,000 μs is the frame duration, 100 is the number of scan repeats with 400 lines. A frequency divider 121 performs an 8: 1 division of a frequency of 20 kHz. At the input of the master oscillator 123/9 / receives a frequency of 2.5 kHz. Scanning, all lines per frame is performed 100 times: 50 times from left to right and 50 times from right to left. Repetitions 50 times are set by counters 198, 201 (Fig. 19/) and decoders 199, 202. At the end of each line, the signal from 1200 output of block 194/196 / enters counter 198/201 / as a counting pulse. After 50 sweeps, the counter generates code 110010, which is decoded by the decoder 199/202 /, the output signal from which resets the bits of the registers 197, 200, preparing them to be filled with codes for the next frame. The trigger 203 sets the sequence of issuing codes from row to row. Its input through diodes is connected to the 1200th outputs of blocks 194, 196. The first output of trigger 203 is connected to the second control input of the key 190 and the first control input of the key 192, the second trigger output is connected to the first control input of the key 190 and the second control input of the key 192. Each drive 92, 116, 104 codes in parallel at the same time 400 lines from 1-3200 outputs / 400 × 8 / to the inputs of blocks 117, 118, 119 pulse amplifiers. Blocks 117, 118, 119 include 3200 pulse amplifiers each with a response time of 18 ns, microcircuits 533AP6 [5 p.128]. The outputs of the pulse amplifiers are connected to their emitters 158 _1-400 in the block 120 radiation modulation. For radiation, each LED is fed by a pulse signal from its pulse amplifier. 400 emitters contain 9600 LEDs / 400 × 24 /. Block 120 performs luminance modulation of the radiation, converting the codes of the three color signals into the corresponding instantaneous emission emitters of brightness (Fig. 12/). The emitters use HL MP type LEDs from the Hewlett-Packard company [11 p. 71]. For red radiation, LEDs HL MP-AL 00 with a light intensity of 0.4 cd, a wavelength of 0.59 μm at a current of 0.02 A, [11 p. 71] are used, for green light-emitting diodes HL MP-AM 00 with a light intensity 0.8 cd wavelength 0.526 μm at a current of 0.02 A, for blue radiation, HLMP-AB00 LEDs with a light intensity of 0.3 cd wavelength 0.475 μm at a current of 0.02 A. Luminance modulation of radiation is performed by switching on the number of LEDs to cure emitter according to the discharge weights according to table 1.

Table 1 Discharge number in code 1 senior rank 2nd category 3 four 5 6 7 8 younger discharge LEDs per discharge one one one one one one one one Multiplicity of the filter - 2 ^x 4 ^x 8 ^x 16 ^x 32 ^x 64 ^x 128 ^x The weight of the discharge in the code, in% fifty% 25% 12.5 6.25 3,1 1,57 0.78 0.39%

The radiation of the LEDs in three colors R, G. In the emitter 158 when focusing with a micro lens 159 and entering into the input window of the focon 160 is mixed. The focon outputs radiation in the form of a circle with a diameter of 0.02 mm to the reflector of the piezoelectric deflector 131. 400 emitters give 131,400 circles on the reflector. The brightness, saturation and hue of the resulting color of the circle on the reflector are determined by the total energy of light and the mutual ratio of the three colors. The total luminous intensity of one emitter, taking into account that the LEDs of all colors have a light intensity of 0.3 cd / blue LED /, is:

0.3 cd × 3/1 + 0.5 + 0.25 + 0.125 + 0.0625 + 0.03125 +

+ 0.0156 + 0.0078 / = 0.9 cd × 1.98 = 1.782 cd,

where: 3 - the number of colors in the emitter,

1-0,0078 - coefficients of 1-8 binary bits in the code.

Total luminous intensity from 400 emitters:

1,782 cd × 400 = 712.8 cd

With 100 horizontal line repeats per frame:

712.8 cd × 100 = 71280 cd.

Taking into account losses during projection from the emitter to the screen, the averaged maximum radiation strength is 20 times the following:

71280: 20 = 3564 cd.

Accepting the magnification of the image magnification by the projection lens by 10 times, the screen will be:

horizontal 10 × / 0.04 mm × 1200 _count / = 480 mm,

vertical 10 × / 0.04 mm × 800 _lines / = 320 mm,

diagonally 576 mm or 22.6 inches.

0.04 mm resolution element on the piezoelectric reflector 126, the length of the piezoelectric reflector at least 32 mm / 0.04 mm × 800 /. The perception of the volumetric image on the screen 22.5 "with a radiation power of 3564 cd will give the viewer full satisfaction with the volumetric image. Technical characteristics of the claimed system in table 2.

The operation of a digital stereo television system.

Six analog video signals of the right and left frames of a stereo pair are converted by six 2-7 ADCs into 8-bit codes with 12 MHz sampling. Code generators 12, 13, 14 form sequential codes from parallel codes and replace the representation of units from pulses in them with positive / odd samples of a line / half-sine wave and negative / even samples / half-sine waves of a mono frequency of 48 MHz. The clock frequency in the system is 48 MHz. On the transmitting side are encoded / Fig. 1/400 lines per frame with 600 samples per line. Line scan line-by-line without reverse moves of figure 2, line frequency of 20 kHz, frame rate of 50 Hz, frame scan without reverse moves, the frequency of stereo pairs 25 Hz. The video signals of the right and left frames of one object follow in 0.02 s. The information of the codes is transmitted by the three channels of the transmitter 21. The first channel transmits the information of the codes E _RP and E _{RL by the} upper side frequency of the first carrier, the second channel transmits the information of codes E _VP and E _{VL by the} lower side frequency of the first carrier, the third channel transmits information of the codes E _GP and E _GL upper lateral frequency of the second carrier. The total occupied band on the air is 316 Hz. Broadcast speed 36 Mb / s / 288 Mb / s. The receiving side simultaneously receives three radio signals by three paths of receiving and processing codes of video signals, amplifies them, detects, extracts horizontal sync pulses / SSI / and stereo sync pulses / SIS /, frequency synthesizer 140 / Fig. 9 / reproduces two carrier frequencies, video signal codes are separated by its video signal channels, where the number of samples in a line doubles from 600 to 1200 and the number of lines in a frame doubles from 400 to 800.

The codes of the even frame are accumulated in the drive 186 of the codes of the even frame, the codes of the odd frame are accumulated in the drive of 187 codes of the odd frame / FIG. 17/. Both drives 186, 187 are combined in block 92/116, 104 / drive code / Fig.9/. Codes from the drives 92, 116, 104 codes are fed to the inputs of 400 emitters of the block 120 radiation modulation. Block 120 performs luminance modulation of the radiation according to the code values in parallel with 400 lines. Radiation from 400 emitters is projected by 400 focusing cones of optical fibers / focons / 160 onto the reflector of the piezoelectric deflector 131 with a vertical pitch of 0.02 mm. Reflecting from it, the radiation arrives at the reflector of the piezoelectric deflector 126, which simultaneously performs horizontal scanning of 400 odd lines when the reflector is turned from left to right and 400 even lines when turned from right to left. The projection of even lines on the reflector of the piezoelectric deflector 126 is carried out in the intervals between the odd lines / 12 /. For this, the reflector of the piezoelectric deflector 131 is rotated down 0.02 mm according to the control signals from the amplifier 130. For a frame, the line scan is performed 100 times: 50 times of odd lines and 50 times of even lines. The end face of the piezoelectric deflector 126 with a reflector oscillates with a frequency of 2.5 kHz and scans 800 lines with a frequency of 5 kHz in the rear focal plane of the projection lens 134, which projects the image of the stereo pair onto a matte screen 135 with a magnification of 10 times. The viewer perceives a three-dimensional image through ZD glasses 138 with an IR receiver 137 on a frame that receives control signals from an IR transmitter 136 located above the screen. The control signals for the IR transmitter are 25 Hz stereo pulses, coming to its inputs from the stereo pair sync pulses allocation unit 144.

Used sources

1. Patent No. 2246801, cl. H 04 N 15/00, bull. No. 5 of 02.20.05, prototype.

2. Kolesnichenko O.V., Shishigin I.V. PC hardware. 5th ed., St. Petersburg. 2004, p. 588-565.

3. Radio transmitting devices, MS Shumilin et al. M, 1981, p. 234, 235.

4. Fridland I.V., Soshnikov V.G. Automatic control systems in video recording devices. M, 1988, c.118 fig.5.5, c.122 fig.5.10.

5. Digital integrated circuits. Handbook, Minsk, 1991, p. 128, 231, 258.

6. L.M. Kuchekyan. Light guides. M, 1973, p.77.

7. Shilo V.A. Popular digital circuits. Chelyabinsk, 1989, p. 222.

8. Brodsky M.A. TVs color image. Minsk, 1988, p. 86 fig. 2.55, p. 132 fig. 4.2.

9. Radio communications, broadcasting and television. Ed. Fortushenko. M, 1981, p. 146.

10. Barkan V.F., Zhdanov V.K. Amplification and impulse technology. M, 1981, p. 209.

11. "Radio" No. 7, 1998, p.7l.

table 2 Specifications Values Transmission side Ranges Used 430-790 MHz, 21-60 can Carrier frequencies / option / 480 MHz, 576 MHz System Clock 48 MHz Video Code Transmission E _RP , E _RL 528 MHz upper side. f ₁ - "- E _VP , E _VL 432 MHz lower side. f ₁ - "- E _GP , E _GL 624 MHz top side. f ₂ Occupied band on air 316.8 Hz The number of encoded lines / samples per line 400/600/300 × 2 /; Video Sampling 12 MHz Line frequency / frame rate 20 kHz / 50 Hz Line Duration / Frame Duration 50 μs / 20 ms Video coding 255 levels, 8 digits Audio sampling 60 kHz Sound coding 16 bits Receiving side Number of lines / line frequency 800/5 kHz Counts per line 1200/600 × 2 / Video Signal Code Frequency 24 MHz Frame resolution 960000 ale. / 1200 × 800 / Raster scan 400 lines at a time Line Length / Frame Duration 200 μs / 20 ms Screen imaging 400 line electronic scan and lens projection 3D image perception through ZD glasses

Claims (1)

Digital stereo television system,  comprising a photovoltaic converter on the transmitting side,  first to sixth analog-to-digital converters (ADC),  the inputs of which are connected to the corresponding outputs of the photoelectric converter,  the first and second ADCs of the sound signal,  to the information inputs of which sound signals are given,  serially connected sine oscillation generator and frequency synthesizer,  first to third code generators,  first and second self-propelled pulse distributors,  pulse counter  first and second keys,  trigger and transmitter of radio signals,  the first output of the frequency synthesizer is connected to the first control inputs of the first to third code generators and to the signal inputs of the first and second keys,  the output of the first key is connected to the clock inputs of the first to third ADCs,  the output of the second key is connected to the clock inputs of the fourth to sixth ADCs,  the first control input of the first key and the second control input of the second key are connected to the first output of the trigger,  the second control input of the first key and the first control input of the second key are connected to the second output of the trigger,  the second output of the frequency synthesizer is connected to the second control inputs of the first to third code generator and the first control inputs of the first and second ADC sound signals,  to the second control inputs of which the third output of the frequency synthesizer is connected,  the fourth output of which is connected to the third control inputs of the first to third code generators,  the fifth output of the frequency synthesizer is connected to the fourth control inputs of the first,  second code formers,  to the first control input of the photoelectric converter and to the third control inputs of the first and second ADCs of the sound signal,  the sixth output of the frequency synthesizer is connected to the second control input of the photoelectric converter and to the control input of the pulse counter,  the output of which is connected to the control input of the second self-propelled pulse distributor,  the seventh output of the frequency synthesizer is connected to the third control input of the photoelectric converter,  the eighth output of the frequency synthesizer is connected to the first input of the radio signal transmitter,  the second input of which is connected to the ninth output of the frequency synthesizer,  the first information input of the first code generator is connected in parallel to the outputs of the first and fourth ADCs,  the first information input of the second code generator is connected in parallel to the outputs of the second and fifth ADCs,  the first information input of the third code generator is connected in parallel to the outputs of the third and sixth ADCs,  the outputs of the first and second ADCs of the sound signal are connected to the second information inputs of the first and second code generators, respectively,  the output of the first self-propelled pulse distributor is connected to the third information inputs of the first and second code generators and to the second information input of the third code generator,  and the input of the first self-propelled pulse distributor is connected to the second output of the second code generator,  the counting input of the pulse counter is also connected to it,  the output of the second self-propelled pulse distributor is connected in parallel to the fourth information inputs of the first,  the second shaper codes and to the third information input of the third shaper codes,  three-channel radio transmitter,  the first channel includes a series-connected amplifier of the first carrier frequency,  the input of which is the first input of the radio signal transmitter,  amplitude modulator  the second input of which is connected to the output of the first code generator,  and an output amplifier,  the second channel includes a series-connected amplitude modulator and output amplifier,  the first input of the amplitude modulator is connected to the output of the amplifier of the first carrier frequency,  its second input is connected to the output of the third code generator,  the third channel includes a series-connected amplifier of the second carrier frequency,  the input of which is the second input of the radio transmitter,  amplitude modulator  the second input of which is connected to the output of the second code generator,  and an output amplifier,  the first to sixth ADCs are identical,  each contains a series-connected video amplifier and a piezoelectric deflector with a reflector at the end,  source of positive reference voltage  the output of which is connected to the second inputs of the video amplifier and piezoelectric deflector,  negative reference voltage source  the output of which is connected to the third inputs of the video amplifier and piezoelectric deflector,  emitter from a pulsed LED,  slit diaphragm and micro lens,  line of multi-element photodetector and encoder,  the outputs of which are the outputs of the ADC,  the control input is the pulse LED input,  the first and second code generators are identical,  each contains a serially connected trigger and a switching unit,  whose inputs are the first information input,  and three channels  the first and second channels are identical,  their inputs are connected to the corresponding outputs of the switching unit,  and the outputs of the three channels are combined,  the first channel includes a series-connected block of elements AND,  the first and second elements OR and the output key,  and a self-propelled pulse distributor,  the second channel includes a series-connected block of elements AND,  the third and fourth elements OR and the output key,  and a self-propelled pulse distributor,  the first inputs of AND elements are connected to the corresponding outputs of the switching unit,  their second inputs are connected to the outputs of the self-propelled pulse distributor of their channel,  the outputs of the output keys are combined and are the output of the code generator,  the third channel includes two blocks of AND elements,  the inputs of which are the second information input,  fifth and sixth elements OR,  the output of the fifth OR element is connected to the second input of the second OR element in the first channel,  the output of the sixth OR element is connected to the second input of the fourth OR element in the second channel,  and two self-propelled pulse distributors,  the outputs of which are connected to the second inputs of the corresponding blocks of elements of the third channel,  and includes the first and second keys,  and series-connected pulse counter and decoder,  the first and second outputs of which are connected respectively to the first and second control inputs of the first and second keys,  in the second code generator, the decoder has a third output,  being the second output of the second code generator,  connected to the input of the first self-propelled pulse distributor and to the counting input of the transmitting side pulse counter,  the output of the first key is connected to the inputs of the self-propelled pulse distributors of the first and second channels,  the output of the second key is connected to the inputs of the self-propelled pulse distributors in the third channel,  the first control input of the code generator is the trigger input,  the second - associations key input and counting input of the pulse counter,  the third is the combined input of the signal inputs of the output keys,  the fourth control input of the pulse counter,  the third code generator contains a serially connected trigger and a switching unit,  and two identical channels,  the inputs of which are connected to the outputs of the switching unit,  and their outputs are combined and are the output of the third code generator,  the first channel includes sequentially composed block of elements AND,  the first and second elements OR and the output key,  and a self-propelled pulse distributor,  the second channel includes a series-connected block of elements AND,  the third and fourth elements OR and the output key,  and a self-propelled pulse distributor,  the first inputs of the blocks of elements AND are connected to the corresponding outputs of the switching unit,  the second inputs of the elements And are connected to the outputs of the self-propelled pulse distributor of its channel,  the first information input is the inputs of the switching unit,  the second and third information inputs are the second inputs of the second and fourth elements OR,  the first control input is the trigger input,  the second is the combined inputs of self-propelled pulse distributors,  the third is the combined signal inputs of the output keys,  the combined output of which is the output of the third code generator,  and comprising an antenna on the receiving side,  Control block,  first to third paths for the reception and processing of video signal codes,  the inputs of which are connected to the antenna,  three blocks of pulse amplifiers,  channel for generating control signals,  two channels of sound reproduction,  radiation modulation unit,  the corresponding inputs of which are connected to the corresponding outputs of the three blocks of pulse amplifiers,  serially connected first frequency divider,  line scan unit from the master oscillator and the output stage,  first amplifier  the input of which is connected to the output of the horizontal scanning unit,  and the first piezoelectric deflector with a reflector at the end,  the first source of positive reference voltage  the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector,  a second source of negative reference voltage,  the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector,  connected in series to a second amplifier and a second piezoelectric deflector with a reflector at the end,  a third source of positive reference voltage,  the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector,  a fourth source of negative reference voltage,  the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector,  projection lens  in the rear focal plane of which the reflector of the first piezoelectric deflector is located,  optically connected through the reflector of the second piezoelectric deflector to the radiating side of the block,  radiation modulation  in the external focal plane of the projection lens is a matte screen,  the first to third paths of the reception and processing of video signal codes are identical,  each includes a series-connected reception unit,  radio signal  whose first input is connected to the antenna,  the second inputs are connected to the first group of outputs of the control unit,  radio frequency amplifier and bipolar amplitude detector,  first and second pulse shapers,  connected respectively to the first and second outputs of the bipolar amplitude detector,  and the video channel,  including the first register,  the input of which is connected to the output of the first pulse shaper,  second register  the input of which is connected to the output of the second pulse shaper,  code processing unit,  the inputs of which are connected to the outputs of the first and second registers,  first block of delays  the inputs of which are connected to the outputs of the code processing unit,  second delay unit and adder,  the first inputs of which and the inputs of the second delay unit are bitwise combined and connected to the outputs of the code processing unit,  the second inputs of the adder are connected to the outputs of the first block of delays,  the channel for generating control signals includes a series-connected block for selecting horizontal sync pulses and a frequency synthesizer,  serially connected key,  pulse counter and decoder,  and a block for isolating clock pulses of stereo pairs,  from the first to the third inputs of the block selection of horizontal sync pulses connected to the outputs of the first pulse shapers in each path for receiving and processing codes of video signals,  the output of the block is connected to the first input of the frequency synthesizer and to the first control input of the key,  the second group of inputs of the frequency synthesizer is connected to the second group of outputs of the block,  management  the first output of the synthesizer  frequencies connected in parallel to the signal input of the key,  to the first control inputs of the first and second registers in the first or third channels of the video signal,  second output of the synthesizer  frequency is connected to the second control inputs of the first and second registers in the first to third channels of the video signal and to the third control inputs in the first and second channels of sound reproduction,  to the fourth control inputs of which the third output of the frequency synthesizer is connected,  the fourth output of the frequency synthesizer is connected to the control inputs of the first to third blocks of code processing,  the fifth output of the frequency synthesizer is connected to the third inputs of the blocks of the reception of the radio signal in the first and second paths of the reception and processing of codes of video signals,  the sixth output of the frequency synthesizer is connected to the third input of the radio signal receiving unit in the third path of receiving and processing video signal codes,  the seventh output of the frequency synthesizer is connected to the third control inputs of the first to third first delay units and to the control inputs of the first to third adders,  the eighth output of the frequency synthesizer is connected to the first control inputs from the first to third of the first delay blocks,  the first and third inputs of the stereo clock sync pulses block are connected to the outputs of the second pulse shapers in 1-3 paths of receiving and processing video signal codes,  its fourth input is connected to the output of the block selection of horizontal sync pulses,  the first and second outputs of the decoder are connected to the first and second control inputs in the first and second channels of sound reproduction,  the second control input of the key and the control input of the pulse counter are combined and connected to the second output of the decoder,  the first to third code processing units are identical,  each includes a trigger,  the first,  second,  third delay blocks,  first to fourth registers,  adder,  fifth and sixth registers,  the information inputs of the first and second registers are bitwise combined and connected to the outputs of the first block of delays,  the inputs of which are the first information input of the code processing unit,  the information inputs of the third and fourth registers are bitwise combined and connected to the outputs of the second block of delays,  the inputs of which are the second information input of the code processing unit,  whose control input is the combined trigger input and adder control input,  the outputs of the second register are connected to the first inputs of the adder,  the outputs of the first register are connected to the inputs of the fifth register and through diodes to the first inputs of the adder,  the output of the fourth register is connected to the second inputs of the adder,  the outputs of the third register are connected to the inputs of the sixth register and through the diodes are connected to the second inputs of the adder,  the outputs of which are connected to the inputs of the third block of delays,  the first trigger output is connected in parallel to the control inputs of the fifth,  second and third registers,  the second trigger output is connected in parallel to the control inputs of the sixth,  fourth and first registers,  fifth outlets  the sixth registers and the third delay block are bitwise combined and are outputs of the code processing unit,  first to third first delay blocks are identical,  each includes an AND element,  the first,  second keys  the first,  a second pulse distributor and eight registers with the corresponding number of bits in each,  the first and second control inputs are the first and second inputs of the And element,  the signal inputs of the keys are combined and are the third control input of the first block of delays,  the output of the first key is connected to the input of the first pulse distributor,  the output of the second key is connected to the input of the second pulse distributor,  the outputs of the first pulse distributor are connected in series to the first control inputs of the bits of the first to eighth registers,  the last output of the first pulse distributor is connected to the second control input of the first key and to the first control input of the second key and through a diode is connected to the first control input of the last bits in the first to eighth registers,  the outputs of the second pulse distributor are connected to the first control inputs of the bits of the first to eighth registers in the reverse order:  the first output is connected to the last bit of the first to eighth registers,  the last output through the diode is connected to the first bits of the first to eighth registers,  and through a diode connected to the second control input of the second key and to the first control input of the first key,  the outputs of each first to eighth register are combined and are the first to eighth outputs of the first delay block,  the second (information) inputs of the bits of the first to eighth registers are bitwise combined and are the first to eighth information inputs of the first block of delays,  the block selection of horizontal sync pulses includes the first or third pulse counters,  the first,  second elements And,  the first and third elements are NOT and a diode,  the inputs of the block are the first or third counting inputs of the pulse counters,  to which respectively the first or third elements are NOT connected,  the outputs of which are combined and connected to the control inputs of the pulse counters,  the outputs of the first and second pulse counters are connected to the first and second inputs of the first element And,  whose output and the output of the third pulse counter are connected to the first and second inputs of the second AND element,  the output of which is the output of the block,  and through a diode connected to the control inputs of the pulse counters,  the stereo clock separation unit includes first to third pulse counters,  the first to third elements are NOT,  first to third elements And and a diode,  the first to third inputs of the block are the counting inputs of the pulse counters,  to which respectively the inputs of the first or third elements are NOT connected,  the outputs of which are combined and connected in parallel to the control inputs of the pulse counters,  the output of the first and second pulse counters are connected to the first and second inputs of the first element And,  whose output and the output of the third pulse counter are connected to the inputs of the second AND element,  the output of which and the fourth input of the stereo clock sync selection block are connected to the inputs of the third AND element,  the output of which is the output of the block,  and through a diode connected to the control inputs of the pulse counters,  characterized in  that on the transmitting side the frequency synthesizer has a tenth output,  connected to the trigger input,  a second frequency divider is introduced at the receiving side,  the input of which is connected to the output of the block selection of horizontal sync pulses,  and the output is connected to the input of the second amplifier,  ZD glasses with an IR receiver on the frame of ZD glasses and an IR transmitter,  located above the matte screen,  and the input of which is connected to the output of the block allocation of stereo pulses of stereo pairs,  the emitting window of the IR transmitter is located towards the screen,  the input window of the IR receiver is located opposite the emitting window of the IR transmitter,  a code store is inserted into each channel of the video signal,  the radiation modulation unit is made of 400 channels,  each of which contains a sequentially arranged emitter of three primary colors,  a micro lens and a focusing cone of the optical fiber (focon),  the inputs of the block are the inputs of the emitters,  connected to the corresponding outputs of the blocks of pulse amplifiers,  the radiating planes of the emitters are located in the rear focal plane of the micro-lenses,  in the front focal plane of which are the input windows of the focusing cones of the optical fibers,  emitters through micro lenses,  optical fiber focusing cones,  the reflector of the second piezoelectric deflector is optically connected to the reflector of the first piezoelectric deflector,  located in the rear focal plane of the projection lens,  in the outer focal plane of which a matte screen is located,  first to third code drives are identical,  each includes a serially connected key,  the signal input of which is the first control input of the code store and is connected to the eighth output of the frequency synthesizer,  the control input is the second control input and is connected to the output of the stereo pair clock allocation unit,  and trigger  odd-frame code storage device and even-frame code storage device,  the first and second information inputs of the code store are the bitwise combined information inputs of the code store of the odd frame and the information inputs of the code store of the even frame,  connected respectively to the outputs of the second delay unit and to the outputs of the adder,  the first trigger output is connected to the first control input of the odd frame code storage device,  the second output of the trigger is connected to the first control input of the drive codes even frame,  the third control input of the code storage device is the combined second control inputs of the code storage device of the odd frame and the code storage device of the even frame,  the third control input is connected to the seventh output of the frequency synthesizer,  the fourth control input is the combined third control inputs of the odd frame code store and the even frame code store,  the fourth control input is connected to the first output of the frequency synthesizer,  the outputs of the code store are the correspondingly combined outputs of the code store of the odd frame and the code store of the even frame,  the odd-frame code store and the even-frame code store are identical,  each includes 400 register blocks,  the first control input of the first block of registers is the first control input of the odd (even) frame code storage device,  the second control inputs of the register blocks are combined and are the third control input of the drive of codes of the odd (even) frame,  the third control inputs of the register blocks are combined and are the second decreasing input of the odd (even) frame code storage ring,  the first control output of each block of registers is the first control input for each subsequent block of registers,  the first control output of the last (400th) block of registers is connected in parallel to the fourth control input of all 400 block of registers,  the first and second inputs of the register blocks are combined bitwise are the first and second information inputs of the odd (even) frame code storage unit,  the outputs of the blocks of the registers are the outputs of the drive codes odd (even) frame,  each block of registers includes the first,  second,  third,  fourth keys  the first,  second,  third,  fourth pulse distributors,  the first eight registers  connected in series with the first pulse counter and the first decoder,  the output of which is connected in parallel to the third control inputs of the bits of the first eight registers,  second eight registers,  the second pulse counter and the second decoder connected in series,  the output of which is connected in parallel to the third control inputs of the bits of the second eight registers,  the first (information) inputs of the bits of the first eight registers are bitwise combined and are the first information input of the master block,  the first (information) inputs of the bits of the second eight registers are bitwise combined and are the second information input of the register block,  the outputs of the bits of the first eight registers and the outputs of the bits of the second eight registers are bitwise combined and are the first to eighth outputs of the register block,  the first control input is the combined first control inputs of the first and third keys,  the signal inputs of which are combined and are the third control input of the register block,  the signal inputs of the second and fourth keys are combined and are the second control input of the register block,  the fourth control input of the register block through the diode is connected to the first control input of the second key,  the second control input of the fourth key and to the second output of the trigger,  the first output of which is connected to the second control input of the second key and to the first control input of the fourth key,  the counting inputs of the first and second pulse counters through the diodes are combined and connected to the trigger input,  the output of the first key is connected to the input of the first pulse distributor,  whose first to last outputs are connected to the first control inputs of the bits of the first eight registers from the first to the last,  the last output of the first pulse distributor is connected to the second control input of the first key and is the first control output of the register block,  the output of the second key is connected to the input of the second pulse distributor,  the outputs of which are sequentially connected to the second control inputs of the bits of the first eight registers in order from the first bit to the last,  the last output of the second pulse distributor is connected to the counting input of the first pulse counter,  the output of the third key is connected to the input of the third pulse distributor,  the outputs of which are sequentially connected to the first control inputs of the bits of the second eight registers in order from the first bit to the last,  the last output of the third pulse distributor is connected to the second control input of the third key,  the fourth key output is connected to the input of the fourth pulse distributor,  the outputs of which from the first to the last are connected to the second control inputs of the bits of the second eight registers in the reverse order:  the first output is connected to the last digits,  and the last output is connected to the first bits of the second eight registers,  the last output of the fourth pulse distributor is connected to the counting input of the second pulse counter.

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