RU2165681C1 - Digital television system - Google Patents

Abstract

FIELD: radio communications; ultrahigh- frequency digital television systems. SUBSTANCE: system has on sending end photoelectric converter, five analog-to-digital converters, sine-wave master oscillator, frequency synthesizer, two video signal code shapers, and transmitter; on receiving end it has antenna, touch-sensitive control unit, first and second video-signal code processing and receiving channels, three delay units, three OR-gate units, three pulse amplifier units, beam modulation unit, frequency divider, line sweep unit, frame sweep unit, two amplifiers, two piezoelectric deflectors, two positive reference voltage sources, two negative reference voltage sources, opaque screen, and two channels. Novelty is that two self-moving pulse distributors and dual-channel transmitter are provided on sending end each transmitter channel incorporating single-band signal shaper and that on receiving end control signal shaping channel is introduced, first code receiving and processing channel is provided with flip-flop, four video signal registers, two adders, and five delay units. EFFECT: reduced power requirement. 16 dwg

Description

 The invention relates to radio communications technology and can be used for digital television in the UHF range, reserved for analog television.

 An analogue is the “Digital color television system” [1], which contains a photoelectric converter, a shaper of the luminance signal and two color difference signals, four ADCs, a sine wave generator and a frequency divider, an encoder, a group signal shaper and a television / TV / signal transmitter, on the receiving side, a TV signal receiving unit, a bipolar amplitude detector, two pulse shapers, a luminance signal channel, a channel of the first color-difference signal and a channel of the second color a difference signal, and a sound channel. The system solves the problem of reducing the occupied frequency band on the air to 1215 Hz. Its disadvantage is the high energy intensity due to the use of transmitting tubes and picture tubes and a high clock frequency in the system of 121.5 MHz.

The prototype adopted "Digital television system" [2], containing the transmitting side of the photoelectric transducer, including the lens, the first and second piezoelectric reflectors at the ends, horizontal and vertical units, two sources of positive reference voltage, two sources of negative reference voltage, two dichroic mirrors, three micro-lenses, three photodetectors and three pre-amplifiers, five ADCs, a master oscillator of sinusoidal oscillations, a frequency synthesizer, a shaper in synchronization signals, a shaper of video signal codes E _R , a shaper of codes of video signal E _G , a shaper of codes of video signal E _B , a four-channel radio signal transmitter and a receiving side.

The latter includes a touch control unit, a path for receiving and processing codes for synchronization signals, a path for receiving and processing codes for video signals E _R , a path for receiving and processing codes for video signals E _G , a path for receiving and processing codes for video signals E _B , three blocks of delay elements, three blocks of OR elements , three blocks of pulsed amplifiers, a radiation modulation block containing three emitters, three sets of optical fibers and an optical system, a frequency divider, horizontal and vertical blocks, two piezoelectric reflectors with reflectors at the ends, two sources Single negative reference voltage, two positive reference voltage source, matt screen and two channel sound.

Three ADCs convert analog video signals of the primary colors R, G, B to 8-bit codes, the fourth and fifth ADCs convert audio signals to 16-bit codes. The transmitting side generates four digital streams: a stream of synchronization signal codes and three streams of video signal codes E _R , E _G , E _B , which are transmitted by four amplitude-modulated frequencies. On the receiving side, four radio signals are received, amplified, detected by bipolar amplitude detectors, and without converting the codes into analog video signals, a color image is displayed on the screen, codes of audio signals are converted into analog signals. The clock frequency of 54 MHz, the occupied frequency band on the air 388 Hz. The energy intensity of the system is reduced by excluding transmitting television tubes on the transmitting side and color picture tubes on the receiving side. The disadvantage of the prototype is the transmission of information by four radio channels.

 The aim of the invention is to reduce the energy consumption of the system and occupied bandwidth by transmitting information by two carrier frequencies over two radio channels.

 The technical result is to reduce the energy consumption of the system with the exception of the transmitting side of the two transmission channels, in the receiving side of two paths for receiving and processing codes, and reducing the occupied frequency band on the air to 213 Hz.

The system is a simultaneous two-channel digital. Encoding on the transmitting side 2: 4: 2, image playback on the receiving side 4: 4: 4. The transmitting side generates two code streams, the first stream of video signals E _R and E _B with sampling sampling 6.75 MHz, the second stream of video signals E _G with 13.5 MHz sampling. The transmitter is two-channel, transmission is carried out by single-band signals - the upper side frequency from the spectrum of the amplitude-modulated signal. The occupied band on the first radio channel is 105.3 Hz, on the second - 108 Hz, in the amount of 213.3 Hz, which is 0.0027% of the 8 MHz analog television band. The receiving side receives two radio signals by two paths of receiving and processing codes of video signals, extracts the codes of lowercase and frame sync pulses, separates the digital streams through channels and converts the codes of video signals into a color image without a picture tube. Technical characteristics of the system are given in table 1.

 Information on the color tones R and B is carried by the frequency of the upper side of the carrier frequency and the polarity of the code signals. Information about the color tone G is carried by the frequency of the upper side of the carrier frequency and the polarity of the code signals. Amplitude codes carry information about the brightness of colors. The color saturation is set by the spectral band of the LEDs used in the emitter, the narrower their spectral band of radiation, the higher the color saturation. Sound codes are transmitted in three codes at the end of each line.

 The essence of the claimed system is that in a digital television system containing a transmitting side as part of a photoelectric converter, five ADCs, a sine wave oscillator, a frequency synthesizer, first and second video signal shapers and a transmitter and a receiving side containing an antenna, a sensor control unit, first and second paths for receiving and processing video signal codes, three blocks of delay elements, three blocks of OR elements, three blocks of pulse amplifiers, radiation modulation block, div a frequency amplifier, a horizontal scanning unit, a first amplifier and a first piezoelectric deflector, a first positive reference voltage source, a second negative reference voltage source, a vertical scanning unit, a second amplifier and a second piezoelectric deflector, a third positive reference voltage source, a fourth negative reference voltage source, a matte screen and two sound channels, the first and second self-propelled pulse distributors are introduced on the transmitting side, the transmitter is made two-channel, in each the channel of which the shaper of the single-band signal is input, a channel for generating control signals is introduced on the receiving side, which contains a sequentially connected horizontal sync pulse allocation unit, a sampling pulse generator and a self-propelled pulse distributor, a key, a pulse counter and a decoder, a pulse shaper and a frame sync pulse allocation unit, five triggers, four video signal registers, two adders, five b shackles delay elements and delay element.

 The block diagram of the transmitting side is shown in FIG. 1, block diagram of the receiving side - FIG. 2, the formation of a raster and the shape of the control voltage of the sweeps - FIG. 3, the structure of the transmitted digital streams - FIG. 4, the ADC of the video signal - FIG. 5, the design of the piezoelectric deflector - FIG. 6, the ADC of the sound signal - FIG. 7, a first video signal encoder — FIG. 8, a second video code generator — FIG. 9, the block selection line / frame / clock pulse - Fig. 10, the summing amplifier - FIG. 11, the sampling pulse generator - FIG. 12, a radiation modulation unit - FIG. 13, timing diagrams of the system — FIG. 14, the frequency spectrum of the signal in the transmitter - FIG. fifteen.

 Transmitting side / Fig. 1 / includes a photoelectric converter 1, which is a three-color video signal sensor R, G, B, made up of a lens 2, a first piezoelectric deflector 3 with a reflector at the end, a first source of positive reference voltage 4, a second source 5 of negative reference voltage, the first amplifier 6, block 7 line scan, consisting of a master oscillator 8 and the output stage 9, the second piezoelectric deflector 10 with a reflector at the end, the third source 11 of the positive reference voltage, the fourth source 12 is negative a solid reference voltage, a second amplifier 13, a frame-sweep unit 14 containing an AND 15 element, a master oscillator 16 and a summing amplifier 17, a first 18 and a second 19 dichroic mirrors, the first 20, the second 21, the third 22 micro lenses, the first 23, the second 24, third 25 photodetectors, first 26, second 27, third 28 preamplifiers.

The photoelectric converter 1 is a part of the transmitting television camera 29, which includes the first ADC 30, the second ADC 31, the third ADC 32. The transmitting side includes the fourth ADC 33, the fifth ADC 34, the inputs of which are accompanied by sound signals E _Zv1 , E _Zv2 , the master oscillator 35 of the sinusoidal oscillations, the synthesizer 36 frequencies, the first driver 37 of the codes of video signals, the second driver 38 of the codes of the video signals, the first 39 and second 40 self-propelled pulse distributors, the transmitter 41 of the radio signals made of two channels: The first channel includes a carrier frequency generator 42, a single-band signal conditioner 43 and an output amplifier 44, the second channel includes a carrier frequency generator 45, a single-band signal conditioner 46 and an output amplifier 47. Each of the single-band signal conditioners 43, 46 consists of a series-connected ring modulator and a strip a filter that filters the lower side frequency in the spectrum of the amplitude-modulated signal.

The receiving side is a digital television receiver contains / Fig. 2 / antenna, sensor control unit 48, a first path for receiving and processing video codes, a second path for receiving and processing codes for video signals, a channel for generating control signals and two sound reproduction channels. The first path for receiving and processing codes of video signals receives and processes codes for video signals E _R and E _B and comprises series-connected radio signal receiving unit 49, a radio frequency amplifier 50 and a bipolar amplitude detector 51, a channel for processing video signal codes E _R , a channel for processing video signal codes E _B and trigger 52.

The channel for processing the video signal codes E _R contains the first pulse shaper 53, the first 54, the second 55 keys, the first 56 and the second 57 video signal registers E _R , the first 58, the second 59, the third 60 delay element blocks, the delay element 61 , the fourth 62 key, the output of which is connected to the third 63 and fourth 64 registers of the video signal E _R , adder 65, first 66 and second 67 triggers, serially connected to the third key 68 and the first block 69 of the sound registers.

The channel for processing video signal codes E _B contains a second pulse generator 70, fifth 71, sixth 72 keys connected in series, the first 73 and second 74 video signal registers E _B , the first 75, second 76 and third 77 delay element blocks, delay element 78 are connected to the output , the eighth key 79, the output of which is connected to the third 80 and fourth 81 registers of the video signal E _B , adder 82, first 83 and second 84 triggers connected in series with the seventh 85 key and the second block 86 of sound registers.

The second path of the reception and processing of codes of video signals receives and processes the codes of video signal E _G and contains the serially connected block 87 of the reception of the radio signal, the amplifier 88 of the radio frequency and the bipolar amplitude detector 89, the first and second channels of processing the codes of video signal E _G. The first video signal processing channel E _G includes a first pulse generator 90, a first key 91, a first video signal register E _G and a second delay element unit 93 connected in series with a second key 94 and a first audio register block 95 in series. The second channel for processing video signal codes E _G includes a second pulse shaper 96, a third key 97, a second video signal register E _G 98 and a first delay element block 99, a fourth key 100 and a second sound register block 101 in series.

 A coordinated operating procedure for the receiving side provides a channel for generating control signals, comprising a horizontal sync pulse allocation block 102, a sampling pulse generator 103 and a self-propelled pulse distributor 104, a key 105, a pulse counter 106, a decoder 107, a pulse shaper 108 and a frame clock highlighting section 109.

 The receiving side includes the first 110, second 111 and third 112 blocks of OR elements, the first 113, second 114 and third 115 blocks of pulse amplifiers, block 116 modulation of radiation, serially connected frequency divider 117/2: 1 /, block 118 horizontal scanning, the first amplifier 119 and a first piezoelectric deflector 120 with a reflector at the end, a first source of positive reference voltage 121, a second source of negative reference voltage 122, a frame scanning unit 123 consisting of an And 124 element, a driving generator 125 and a summing amplifier 126, a second amplifier Pezodeflektor 127 and second reflector 128 on the end, a third source 129 of positive reference voltage, the fourth source of negative reference voltage 130 and matt 131 screen.

 The receiving side includes two sound channels, each of which contains a DAC 132, a low-pass filter 133, a power amplifier 134 and a loudspeaker 135. The ADCs 30, 31, 32 are made identically / Fig. 5 / and each contains a serially connected amplifier 136 and a piezoelectric deflector 137 with a reflector at the end, a first source of positive reference voltage 138, a second source of negative reference voltage 139, an emitter 140 comprising a pulsed LED 141, aperture diaphragm 142 and a micro lens 143, a multi-element photodetector line 144 and encoder 145.

 All piezoelectric deflectors / 3, 10, 120, 128, 137, 157 / are end bimorph piezoelectric elements with a light reflector at the end [3, p. 192], structurally executed / Fig. 6 / the same [4, p. 118] from the first 146 and second 147 piezoelectric plates, the internal electrode 148, the first 149 and the second 150 external electrodes. One end of the piezoelectric plates is fixed in the holder 151, at the free end there is a light reflector 152.

 ADC 33, 34 performed / Fig. 7 / identical in the composition of series-connected voltage divider 153, key block 154, matching amplifier 155, amplifier 156 and piezoelectric deflector 157 with a reflector at the end, the first source of positive reference voltage 158, the second source of negative reference voltage 159, emitter 160 as part of a pulse LED 161 , aperture diaphragm 162 and a micro lens 163, a multi-element photodetector line 164, a first decoder 165, an encoder 166, a second decoder 167, a pulse counter 168 connected in series, the third decoder 169 and block 170 registers.

The first video signal code generator 37 generates the video signal codes E _R and E _B / FIG. 8 / and consists of four channels. The first channel includes serially connected the first block of 171 AND elements, the first 172, the second 173 OR elements, and the first output switch 174 and the first self-propelled pulse distributor 175. The second channel includes a series-connected second block 176 of AND elements, a third 177, a fourth 178 OR elements, and a second output switch 179 and a second self-propelled pulse distributor 180. The third channel includes serially connected the third block of 181 AND elements and the fifth OR element 182 and the third self-propelled pulse distributor 183, the fourth channel includes the serially connected fourth block 184 of the AND elements and the sixth OR element 185 and the fourth self-propelled pulse distributor 186.

Block 37 includes first 187 and second 188 keys, a pulse counter 189 and a decoder 190. The second video signal code generator 38 generates the video signal codes E _G and consists of / Fig. 9 / from a serially connected trigger 191 and a switching unit 192 and four channels. The first channel includes serially connected the first block of 193 AND elements, the first 194, the second 195 OR elements and the first output switch 196 and the first self-propelled pulse distributor 197. The second channel includes a series-connected second block 198 of AND elements, a third 199, a fourth 200 OR elements, and a second output switch 201 and a second self-propelled pulse distributor 202. The third channel includes a third block of 203 AND elements and a fifth OR element 204, and a third self-propelled pulse distributor 205, the fourth channel includes a fourth block 206 of AND elements and a sixth OR element 207, and a fourth self-propelled pulse distributor 208. Shaper 38 includes first 209 and second 210 keys and serially connected pulse counter 211 and decoder 212.

 The horizontal sync pulse allocation block 102 and the frame sync pulse allocation block 109 are identical and each contains / Fig. 10 / first 213, second 214 pulse counters, first 215 and second 216 elements are NOT, element And 217 and a diode. Block 102 generates horizontal sync pulses of 15625 Hz, block 109 produces frame sync pulses of 25 Hz.

 The sampling pulse generator 103 is implemented / FIG. 12 / from the first 218, second 219 and third 220 self-propelled pulse distributors. The first self-propelled pulse distributor 218 multiplies the frequency of 15625 Hz by three, the second distributor 219 - by twelve, the third distributor 220 - by twelve. From the first output, sampling pulses of 6.75 MHz come out, from the second output, sampling pulses of an audio signal 46875 Hz. All self-propelled pulse distributors are made according to the scheme [5, p. 274].

 Block 116 modulation of radiation includes / Fig. 13 / the emitter 221 of the three primary colors / R, G, B / and the optical system 222. The emitter 221 is an emitting matrix of the corresponding number of LEDs in three colors: red R, green G and blue B. The optical system 222 includes a collimator and a lens. Summing amplifiers 17 and 126 are identical and each contains / Fig. 11 / nine-digit pulse counter 223, decoder 224, first 225 and second 226 keys, first 227 and second 228 pulse shapers and output amplifier 229.

,
где 15625 Гц - частота строк,

- число пар отсчетов в строке при двухполярной передаче,
8_раз - число разрядов в коде.The clock frequency in the system is determined by the ratio

,
where 15625 Hz - line frequency,

- the number of pairs of samples in a row with bipolar transmission,
8 _times - the number of bits in the code.

Photoelectric converter 1 generates three analog video signals of three colors, which are fed to the inputs of the ADC 30, 31, 32. Photoelectric converter 1 and three ADCs are structurally placed in the transmitting chamber 29, the output of which is three digital code of video signals E _R , E _G , E _B. ADCs convert analog video signals to 8-bit codes. Shapers 37, 38 codes of video signals convert parallel codes of video signals and sound into serial ones and replace unit pulses in them with positive and negative half-sinusoids of a 54 MHz monofrequency from a frequency synthesizer. The master oscillator 35 generates sinusoidal oscillations with a stability of 10 ^-7 .

 A frequency synthesizer 36 generates frequencies from the frequency of the master oscillator 35 and generates: 13.5 MHz pulses from the first output for the ADC 31 clock input and the first control input of the second video signal code generator 38, 6.75 MHz pulses from the second one for the ADC 30 and 32 clock inputs , for the first control inputs of the ADC 33, 34, for the first control input of the first driver 37 and for the second control input of the second driver 38, from the third pulses 46875 Hz for the second control inputs / clock / ADC 33, 34, from the fourth sine wave 54 MHz for the second control input of the first driver 37 of the codes of the video signals and for the third control input of the second driver 38 of the codes of the signals, from the fifth pulse 15625 Hz for the first input of the block 14 frame scan, for the third control inputs of the ADC 33, 34, for the third control input of the first driver of 37 codes , for the fourth control input of the second driver 38 codes and for the input of the first self-propelled distributor 39 pulses from the sixth output pulses of 25 Hz for the second input of block 14 and for the input of the second self-propelled aspredelitelya 40 pulses with a seventh pulses 7812.5 Hz input unit 7 for horizontal scanning, the eighth sinusoidal oscillations 6.75 MHz generators 42, 45 of the carrier frequency.

The ADC 33, 34 converts two sound signals into 16-bit codes, which are fed to the third information input of the first code generator 37 and to the second information input of the second code generator 38. A self-propelled distributor of 39 pulses with the arrival of a signal U _p starting 15625 Hz from the fifth output of block 36 generates a code of eight units 11111111, which is the horizontal sync pulse code / 863th count of each line /, to the third information input of the second shaper 38 codes and to the fourth information input the first shaper 37 codes. A self-propelled distributor of 40 pulses with the arrival of a signal U _p starting 25 Hz from the sixth output of block 36 produces a code of eight units 11111111, which is the frame sync pulse code / 864th count in the last line of the frame /, to the fourth information input of the second shaper 38 codes and to the fifth information input of the first shaper 37 codes.

 Shapers 43, 46 of single-band signals provide the upper side frequencies 526.5 MHz and 540 MHz to the inputs of the output amplifiers 44, 47, which are amplified and radiated into the air.

 The receiving side receives two radio signals, amplifies them, detects, separates the detected signals according to the polarity of the half-sine waves, extracts horizontal and frame sync pulses, separates the codes of video signals and sound through its channels, restores the sampling frequency to 13.5 MHz and reproduces the image on the screen with stereo audio accompaniment .

 Lens 2 / Fig. 1 / creates a color image in the focal plane in which the reflector of the piezoelectric deflector 3 is located. The reflector of the piezoelectric deflector 3 is located on the free end and has a length of 6.25 mm and a width of 0.01 mm The dimensions are taken according to the size of the deploying image element 0.01 x 0.01 mm. The length corresponds to the number of lines in the raster 625 x 0.01 = 6.25 mm. According to the control voltages from the amplifier 6, the piezoelectric deflector 3 vibrates the end with the reflector relative to the reflector of the second piezoelectric deflector 10, scanning the image line.

 The horizontal scanning unit 7 outputs a linearly varying voltage at the output / Fig. 3 / in the form of an isosceles triangle. The voltage first increases in proportion to time, the reflector of the piezoelectric deflector 3 rotates from left to right at a uniform speed, upon reaching the edge of the raster, the scan voltage decreases in proportion to time, the reflector returns at the same speed. The control voltage period is equal to the duration of two lines, therefore, to build a raster of 625 lines at 25 frames, the piezoelectric deflector 3 oscillates with a frequency of 7812.5 Hz. In one period, two lines are expanded. The frequency of 7812.5 Hz is supplied from block 36 to the input of block 7. Block 7 consists of a master oscillator 8 and an output stage 9, which is a ramp generator [6].

 The control voltage of a triangular shape from block 7 is amplified in the amplifier 6 and causes the piezoelectric deflector 3 to oscillate with a frequency of 7812.5 Hz, line scanning is with a frequency of 15625 Hz. The signal from the amplifier 6 is supplied to the internal electrode 148 / Fig. 6 /, voltage from the source 4 of the positive reference voltage is applied to the external electrode 149, voltage from the source 5 of the negative reference voltage is applied to the external electrode 150. When a control voltage is applied to the internal electrode, the piezoelectric plates are deformed: one lengthens, the other shortens [4, p. 122], a bending moment of forces occurs, the end face with the light reflector 152 rotates and deflects the vertical strip of the image.

The image of the vertical line enters the reflector of the second piezoelectric deflector 10, which scans the image vertically, performing a frame scan. The physical process of operation of the piezoelectric deflector 10 is the same as the piezoelectric deflector 3. The width of the reflecting strip is 0.01 mm, the length is 8.54 mm: 854 _readings x 0.01 mm. The piezoelectric deflector 10 oscillates with a frequency of 25 Hz, which is 50 fields per second. Frame scan is performed without reverse moves / Fig. 3 / according to the control voltages from the amplifier 13. A ramp step voltage is output from the output of the summing amplifier 17, which is amplified by the amplifier 13. In the first half of the scan period / first field of the frame / reflector of the piezoelectric deflector 10 rejects the image down, in the second half of the period / second field of the frame / there is a scan up. As a result, an interlaced scan of 2: 1 multiplicity is performed without reverse moves in both rows and frames.

 Summing amplifier 17 / Fig. 11 / sums the triangular voltage from the master oscillator 16 with frequency pulses of 15625 Hz from block 36. Each pulse of the line moves the line at the end of its stroke a step in the width of two lines at the time of the ray entry over the edge of the screen from both sides / Fig. 3 /, five samples per line from each edge are allocated to this. It turns out parallel 625 lines.

The purpose of the blocks from 223 to 228 is to send to the second input of the amplifier 229 at the right time positive / odd lines from 1 to 625 / and negative / even lines from 624 to 2 / pulses of the corresponding amplitude and duration. Before the frame scanning of signals U ₀ from element And 15 starts, the bits of the counter 223 are reset, the counter counts the horizontal pulses 15625 Hz, at the same time this signal opens the first key 225, which passes 15625 Hz pulses to the first pulse shaper 227, issuing positive pulses of the corresponding amplitude and duration, and feeds them to the second input of the amplifier 229. There is a scan of the first field of the frame. With the arrival of the 313rd pulse, the counter 223 generates a code 100111001, which is decoded by the decoder 224 into a signal, closing the first key 225 with a leading edge and opening the second key 226, transmitting 15625 Hz pulses to the second pulse shaper 228, issuing negative pulses to the second input of the amplifier 229.

 The amplifier generates a stepwise linearly incident voltage, and the second field of the frame is scanned. With the arrival of the leading edge of the next frame pulse to the input of element And 15, the counter 223 is reset, the process is repeated. Mixed color rays reflected from the piezoelectric deflector 10 are directed: red from the first dichroic mirror 18 is reflected and collected by the lens 20 into the photodetector 23, blue pass the first dichroic mirror 18, reflected from the second 19 and the lens 22 are collected into the photodetector 25, the green color passes through both mirrors 18, 19 and lens 21 are assembled into a photodetector 24. From the photodetectors, analog video signals are fed to their pre-amplifiers 26, 27, 28.

 The ADCs 30, 31, 32 have one conversion principle, which consists in scanning the beam / Fig. 5 / from the LED 141 by the reflector of the piezoelectric deflector 137 along the plane of the entrance pupils of the photodetector line 144 of the multi-element photodetector, the light pulse is converted into an electrical signal that excites one of the input buses of the encoder 145, which gives a code for the instantaneous value of the input video signal. The conversion is performed with a sampling of 13.5 MHz in the ADC 31 and with a sampling of 6.75 MHz in the ADC 30, 32. The sampling pulses are fed to the input of the LED 141 from the corresponding outputs of block 36. The slotted aperture 142 and the micro lens 143 form a beam with an aperture equal to the size of one the input window of the photodetector of line 144. A pulsed LED AL402A with a pulse rise time of 25 ns, with a satisfactory margin of 13.5 MHz / 74 ns /, was adopted as a radiation source. The signal from the amplifier 136 is fed to the internal electrode 148 of the piezoelectric deflector / Fig. 6/137, the light reflector 152 rotates and deflects the beam along the entrance pupils of the line 144, which contains 255 photodetectors for encoding video signals with an 8-bit code.

The photodetectors in the line are avalanche photodiodes of the APD with a response time of 10 ns. The output of each photodetector is connected to the corresponding input of the encoder 145. The encoder is represented by K155IV1 microcircuits with a response time of 20 ns [7, p. 231]. When the signal from the photodetector arrives at the input of the encoder 145, an 8-bit code representing the instantaneous value of the video signal appears in parallel at the output. The encoder generates codes from 00000001 to 11111111. The first photodetector of line 144 corresponds to the code 00000001, the second to 00000010, the third to 00000011, etc., the 255th to 11111111. The conversion time in the total is 30 ns / 10 ns + 20 ns / or 33 · 10 ⁶ prev / s, with a margin satisfying the frequency of 13.5 MHz / 74 ns /. ADC 31 information creation speed:
13.5 MHz x 8 _times = 108 Mbps,
in the ADC 30, 32 at 54 Mbps. The ADC 33, 34 converts two audio signals into 16-bit codes. During one line of the ADC, three codes are formed each, sampling 46875 Hz.

To obtain codes with higher bit depth, the transfer coefficient of the voltage divider 153 is changed. The divider represents / FIG. 7 / seven-step resistive divider. Block 154 keys has seven keys for connecting the corresponding stage of the divider to the matching amplifier 155, which is an emitter follower. Line 164 multi-element photodetector contains 1024 photodetector, which provides the conversion of the sound signal in a ten-digit code 2 ¹⁰ . The resolution is adopted at 10 μV, the coding range of the ruler is 0 - 0.01024 V. Converting signals exceeding 2 ¹⁰ into the code is performed by the first decoder 165, the second decoder 167, the divider 153 and the key block 154. With their help, the coding range is 0 - 0.65536 V, i.e. 2 ¹⁶ .

The pulse from each photodetector enters the decoder 165, from it to the encoder 166. If there is no signal at the input of the divider 153, a code from one zeros arrives at the input of the second decoder 167, the signal from the first output of the decoder 167 opens the first key in block 154, thereby determining the coefficient 1 0 transmission of the divider 153. When the signal reaches the value 2 ¹⁰ , a signal appears on the second output of the decoder 167, which opens the second key in block 154 and closes the first key, the coefficient becomes 0.5. With code 2 ^{11, the} coefficient is 0.25, with code 2 ¹² - 0.125, with code 2 ¹³ - 0.0625, with code 2 ¹⁴ - 0.03125, with 2 ¹⁵ - 0.015625, which remains until code 2 ¹⁶ . With a decrease in the signal amplitude, the inverse process proceeds with an increase in the transmission coefficient. Units in codes are represented by the presence of an impulse, zeros by their absence.

During one line, the encoder 166 will issue three codes that enter block 170 containing three registers. In the process of receipt, the codes are shifted from register to register by shift pulses U _sd . In block 170, three codes are accumulated, which are then sequentially issued to the first and second generators 37, 38 of the video signal codes. The output signals come from the three outputs of the third decoder 169 at the moments of following 429, 430, 431 sampling pulses / 6.75 MHz /. The output signals form a counter of 168 pulses and a third decoder 169. The counter 168 is nine-digit, keeps a count of sampling pulses of 6.75 MHz. One cycle counts 432 pulses. At moments 429, 430, 431 pulses, the decoder 169 gives three sound codes from block 170 to the driver 37/38 / to the first inputs of the AND elements of blocks 181, 184/203, 206 /. The counter 168 is reset to the leading edge of the pulse U _{0 of the} frequency of the lines 15625 Hz at the time of the 432th sampling pulse.

The first generator 37 of the codes of the video signals gives the codes of the video signal E _R , the units of which are represented by positive half-periods of the sine wave / 54 MHz /, and the codes of the video signal E _B , whose units are represented by the negative half-periods of the sinusoid. The second generator 38 of the codes of the video signals gives the codes of only the video signal E _G , the units of which are represented by positive half-sine waves / odd samples of the line / and negative half-sinusoids / even samples of the line /.

The operation of the first driver 37 of the video signal codes / FIG. 8/. Shaper 37 generates video codes E _R and E _B. Codes with ADC 30 go to the first inputs of AND elements of block 171, codes from ADC 32 go to the first inputs of AND elements of block 176. Pulses from the first and second self-propelled distributors 175, 180 pulses arrive at the second inputs of I elements. Distributors are made according to the scheme [5, p. 274], each has eight digits, trigger pulses U _p are 6.75 MHz pulses arriving at the first (block 189) control input of the code generator 37. From the outputs of AND elements, pulses through OR elements 172, 173 in the first channel and 177, 178 in the second channel open output keys 174, 179 for a duration of 18.5 ns, at the signal inputs of which sinusoids of the 54 MHz monofrequency with a stability of 10 ^-7 .

The first output switch 174 in the open state passes one positive half-sine wave, the second output key 179 passes one negative half-sine wave. At the inputs of the shaper 37, the unit symbols in the codes are represented by pulses; at the output, its unit symbols are represented by positive half-sine waves / E _R / + odd samples and negative half-sine waves / E _B / - even line samples. Timing diagrams in FIG. 14. The outputs of the output keys 174, 179 are combined and are the output of the first shaper 37 codes, the output signal is represented by full or incomplete sinusoids of the 54 MHz monofrequency, which modulate the carrier frequency in block 43. The video signal E _R is represented by odd samples 1 through 853 in each line , the video signal E _B appears as even line samples from 2 to 854. The sampling frequency is 6.75 MHz. Samples 857 through 862 are audio codes from the ADC 33. The audio code consists of two parcels of eight bits each.

 The first half of the code, bits 1 through 8 go to the inputs of the block 181 of AND elements and through the OR elements 182, 173 go to the input of the first output key 174, the second half of the code, bits 9-16 go to the inputs of the AND elements of block 184 and through the OR elements 185, 178 enter the input of the second output key 179. There are no codes in samples 855, 856, at this time the process of switching keys 187, 188 and keys 68, 85, 95, 101 on the receiving side is in progress. In sample 863, there is a line sync pulse code of eight units 11111111, in 864 sample of the last line of the frame, there is a frame clock code.

 The keys 187, 188 are designed to separate the codes of video signals from sound codes. The key 187 is opened by the signal from the first output of the decoder 190 at the time of resetting the counter 189 pulses and remains open until 428 sampling pulses per line. The counter 189 has nine digits, is reset by each pulse of the line 15625 Hz / leading edge of the 432th pulse /. After closing the key 187 and opening the key 188 / moment 428 of the pulse, 855 counting / three inputs of sound codes are received at the inputs of the OR elements 173, 178. At the moment 432 of the pulse, the code of the 863rd sample of the line from block 39 is received at the third input of the OR element 173, and if this line is the last in the frame, the code of the frame sync pulse from block 40/864 the line count / is received at the third input of the OR element 178.

The operation of the second driver 38 of the video signal codes / FIG. 9/. Shaper 38 generates only video signal codes E _G. Codes with the ADC 31 come with a frequency of 13.5 MHz to the inputs of the block 186 switching, branching the stream of codes in 13.5 MHz into two at 6.75 MHz. Block 192 includes four K176KT1 microcircuits, which are 4-channel switches with a response time of 25 ns [8, p. 222]. The outputs of the first two microcircuits are connected to the first inputs of the AND elements of block 193, the outputs of two other microcircuits are connected to the first inputs of the AND elements of block 198 of the second channel. Alternate connection of channels to the outputs of block 192 is performed by trigger 191, at the input of which 13.5 MHz pulses are received.

 The second inputs of the elements And blocks 193, 198 receive sequentially pulses from the first and second self-propelled distributors 197, 202 pulses, each having eight bits, the starting pulses for them are pulses of 6.75 MHz received at the second control input of the shaper 38. From the outputs of the elements And the pulses of the codes through the OR elements 194, 195 in the first channel and 199, 200 in the second channel open the output keys 196, 201, respectively, for a duration of 18.5 ns. At the signal inputs of the output keys, sinusoids of the monofrequency 54 MHz are received. The first output switch 196 in the open state passes the positive half-sine wave, the second output key 201 in the open state passes the negative half-sine wave. At the output of the shaper, 38 units in the codes of odd samples of the line are represented by positive half-sine waves, in codes of even samples of a line by negative half-sines, zeros are represented by the absence of both of them.

The output signal from the shaper 38 is represented by full and incomplete sinusoids of 54 MHz, which modulate the second carrier frequency in block 46. The video signal codes E _{G are} represented by samples from 1 to 854 lines, the sampling frequency is 13.5 MHz. In 857-862 samples are three codes of the sound signal, which are received from the ADC 34 at the first inputs of the elements And blocks 203 / third channel /, 206 / fourth channel /. In 863 samples there is a horizontal sync pulse code, in 864 samples of the last line of the frame there is a frame sync code coming from block 40 to the third input of OR 200.

 Keys 209, 210 perform the functions of separating video signal codes and audio codes. The key 209 is opened by the signal from the first output of the decoder 212 at the time of resetting the counter 211 and remains open in the process of generating 854 code lines. At the moment 428 of the sampling pulse, the key 209 is closed and the second key 210 is opened, three sound signal codes are received at the second inputs of the OR elements 195, 200. At the moments 429, 430, 431 pulses, three sound codes pass, the key 210 closes, the 432 pulse opens the first key 209, the process repeats. The output keys 174, 179, 196, 201 are made according to the diode bridge circuit [9, p. 169] with a response time of up to 10 ns. Generators 42, 45 of the carrier frequency are frequency multipliers, sinusoidal oscillations of 6.75 MHz are fed to their inputs. In the generator 42 6.75 MHz is multiplied by 70, the first carrier frequency is 472.5 MHz, in the generator 45 6.75 MHz is multiplied by 72, the second carrier is 486 MHz.

The spectrum of the amplitude-modulated signal / Fig. 15 / consists of a carrier and two side frequencies. One of the side frequencies and the carrier itself are in the information sense redundant, therefore, in each of the formers 43, 46 of the single-band signal, the carrier frequency is suppressed [10, p. 234] and the lower side frequency is filtered out. Blocks 43 and 46 each include a ring modulator and a bandpass filter. A ring modulator suppresses the carrier frequency, a band-pass filter filters the lower side frequency [10, p. 235]. In the first channel of the transmitter 41 carries information of the video signal codes E _R , E _{B, the} upper side frequency is 526.5 MHz / 472.5 + 54 / and, with a stability of 10 ^-7, occupies the broadcast band ± 52.65 Hz / 105.3 Hz /. In the second channel of the transmitter 41, the information of the video signal codes E _G is carried by the upper side frequency 540 MHz / 486 + 54 /, occupies the broadcast band ± 54 Hz or 108 Hz. The transmitted frequencies are located close to each other, which allows you to receive them on one antenna. The occupied band by the system is 213.3 Hz.

 Two radio signals arrive at the antenna of the receiving side / Fig. 2 /. The radio signals are received by blocks 49, 87. The blocks are selectors of the decimeter range channels / ACS / with electronic tuning. Each block contains an input circuit and a preliminary radio frequency amplifier, this is the first half of SK-D-24 [11, p. 132] without a frequency converter. The blocks receive radio signals in the range 470 ... 790 MHz.

 The band-pass filter of the radio frequency pre-amplifier is tuned by applying bias voltage to the varicaps from the electronic switch of the sensor control unit 48, which is the program selection control unit, for example, the USU-1-15 type [11, p. 86], the radio frequency allocated by the pre-amplifier bandpass filter through the communication loop / in SKD-24 is L 11 / is fed to the input of the amplifier 50/88 / of the radio frequency, where it is amplified to the required value, and fed to the input of the bipolar amplitude detector 51/89 /. Bipolar amplitude detectors are made according to the scheme [12, p. 112].

 From the first outputs of blocks 51, 89, the detected positive half-sinusoids with a frequency of 54 MHz are supplied to the inputs of the first formers 53, 90 pulses. From the second outputs of blocks 51, 89, the detected negative half-sinusoids of 54 MHz are supplied to the inputs of the second shapers 70, 96 pulses. The pulse shapers are made according to the scheme of an asymmetric trigger with emitter coupling [13, p. 209], forming rectangular pulses from harmonically varying signals. The shapers give out pulses of the same polarity and a duration equal to the duration of the pulses in the codes on the transmitting side. Units in codes are represented by the presence of an impulse, zeros by their absence. After turning on the power of the receiving side, all keys are in the closed state. The operating procedure of the receiving side is set by the timely opening and closing of keys by control signals. The decisive role belongs to the block 102 allocation line clock.

The condition for issuing a horizontal sync pulse is the simultaneous arrival from shapers 53, 90 of the codes to the inputs of block 102 of eight units each 11111111. In all codes of the line, except the 863rd, one of the two codes will always have one or more zeros, according to which the elements are NOT 215 216 / Fig. 10 / reset the counters 213, 214. With the arrival of codes 11111111 at the same time, block 102 generates a horizontal sync pulse, which starts the sampling pulse generator 103, opens the key 105 and enters blocks 117, 123. The sampling pulses go to the self-propelled pulse distributor 104, which generates a clock frequency of 54 MHz 6.75 MHz by multiplying by eight pulses in the generator 108, a switch 105 and a signal U _vyd issuing control inputs of the first and second registers E _G video signal 92, 98.

Shaper 108 pulses along the leading edge of the sampling pulse generates a control signal U _{from a} duration of 148 ns, opening the keys 54, 71, 91, 97 for a time of 148 ns. The keys 55, 72 and 62, 79 are alternately opened and closed by pulses from the trigger 52 / Fig. 2 /, determining the passage of codes into their registers 56, 57, 63, 64, 73, 74, 80, 81. Codes from the drivers 53, 70, 90, 96 pulses at the moments of the open state of the keys fill the bits of the video signal registers. To obtain the sampling frequency of the video signal E _R and E _B from 6.75 MHz to 13.5 MHz, intermediate / middle / code codes are obtained from each previous and subsequent codes. For this, adders 65, 82 are used, two additional registers / 57, 64, 74, 81 / and four delay element blocks / 59, 60, 76, 77 / two flip-flops 66, added to each channel E _R and E _B 67, 83, 84 and one delay element 61, 78.

Разряд 0 обозначает разряд переноса при сумме кодов.To obtain intermediate values, the stream of video signal codes E _{R with} keys 55, 62 branches into two at 3.375 MHz. Each code is used by the adder 65/82 / twice: the first time as the previous, the second time as the next / Fig. 16/. For this, two registers 56, 57 and 63, 64 are used in each stream. Adder 65/82 / adds the codes from the corresponding registers, and the least significant bit of the sum code is discarded, which means dividing the sum of binary numbers by two. As adders, K555IM6 microcircuits are used [7, p. 258] with an addition time of 24 ns. Division of the sum by two is performed by shifting the sum code by one bit so that the least significant bit of the code is discarded. A shift by one bit is performed by the corresponding connection of the outputs of the adder 65/82 / to the inputs of the block 60/77 / delay elements:

Bit 0 denotes a carry bit in the sum of codes.

The process of obtaining intermediate values is shown in FIG. 16. Codes from the key 55 are sent in parallel to the video signal registers E _R , codes from the key 62 are sent in parallel to the video signal registers 63, 64 of the E _R. The simultaneous issuance of codes from the registers in the adder 65 provides the block 61 delay, delaying the output signal U _iss for 148 ns. The triggers 66, 67 supply codes to the adder 65 from the necessary registers, directing the signal _Uout to the registers 57, 63 or 56, 64. First / circuit 1 of FIG. 16/1 code from register 57 and 2 code from register 63 are issued. The adder performs addition for 24 ns and issues the sum code without the least significant bit to the block of delay elements 60, delaying the code by 50 ns. The intermediate code arrives at OR 110 first.

Block 58 delays the code from register 63 to 148 ns, but the first 74 ns are added, so the code from register 63 enters block 110 after 74 ns for the intermediate code from block 60. The code from register 57 to block 110 does not pass, exit he diodes are closed. The output signals from the triggers 66, 67 reset the registers when codes are issued, but with the very first code / circuit 1 / the register 56 is not reset, since the output signal from the second output of the trigger 66 has not yet arrived in it. To reset the register 56 in this case, the signal issuance from the register 57 is supplied to the control input of the register 56 as a signal U _{0 of} zeroing without issuing a code from the register 56.

In the second addition / scheme 2 /, the second code is added again from register 64 and the first time of the third code received in register 56. In this case, the signal _Uout from the second output of trigger 66 gives the third code from register 56 to the adder 65 and resets it, the signal U _vyd from the fourth register 64 repeatedly issues the second code to the adder 65 and resets it. The received intermediate code, 74 ns after the third code from block 58, goes to block 110. After it, 74 ns to block 110, the code comes from block 59, which caused a delay of 148 ns, but the first half of the delay is added. In the third addition / scheme 3 /, the third code is added again from register 57 and the fourth time from the register 63 for the first time. Block 110 receives the intermediate code first from block 60/74 ns after the code from block 59 /, then through 74 ns code from block 58. During the fourth addition / scheme 4 /, the fourth code is added again from register 64 and the new fifth code from register 56. At block 110, first the code from block 60 and after 74 ns the code from block 59. Next, the processes go to same way. As a result, the codes in the block of elements OR 110 go with a frequency of 13.5 MHz.

The stream of video signal codes E _{B with the} keys 72, 79 branches into two at 3.375 MHz, then the described process of increasing the sampling frequency of the video signal codes to 13.5 MHz follows. For a temporary coincidence of the video signal codes E _G with the video signal codes E _R and E _B, after register 92, a block of delay elements 93 is introduced, which delays the codes by 148 ns, and a block 99 of delay elements delays the codes by 222 ns / 148 + 74 /, respectively. As a result, the video signal codes E _R , E _G , E _B are fed to the inputs of blocks 113, 114, 115 of pulse amplifiers with a frequency of 13.5 MHz, which makes it possible to reproduce the image on the screen in a ratio of 4: 4: 4. The timely opening and closing of the keys 68, 85, 94, 100 is ensured by the key 105, the pulse counter 106 and the decoder 107. The counter 106, having counted 427 sampling pulses from the beginning of the line, generates a code 110101011, by which the decoder 107 generates a pulse that opens the keys from the first output 68, 85, 94, 100, transmitting sound codes into blocks 69, 86, 95, 101 sound registers. Counting time 855/856 is spent on the process of opening keys 68, 85, 94, 100.

 When the 431st pulse arrives at the counter 106, the decoder 107 generates a pulse from the second output, closing the keys 68, 85, 94, 100, resetting the counter 106 and closing the key 105. During the open state, the keys are passed to blocks 69, 86, 95, 101 sound registers with three codes each, which are output by pulses of 46875 Hz from the second output of generator 103 are output to DAC 132, where they are converted into analog signals and reproduced by loudspeakers 135. Blocks 113, 114, 115 of pulse amplifiers contain amplifiers with the number of LEDs of the same color each. The amplifier generates a voltage with the arrival of the code pulse to emit its LED. Blocks of pulse amplifiers are represented by 533AP6 microcircuits with a response time of 18 ns [7, p. 128].

 The radiation modulation unit 116 performs luminance modulation of the three-color radiation according to the code value of each video signal. Block 116 includes an emitter 221 of three primary colors and an optical system 222. The emitter contains a matrix of red, green, and blue LEDs of the HLMP type manufactured by the Hewlett-Packard company [14, p. 71]. LEDs are located in the focal plane of the optical system 222 / Fig. thirteen/. The number of LEDs in each color is 12 pcs. The distribution of LEDs according to the weights of the digits of the code in table 2.

где в числителе суммарная сила света от излучателя,

- коэффициенты двоичного кода в 4, 5, 6, 7, 8 разрядах,
0,5·10^-6 м² - площадь развертывающего элемента на экране.The total radiation of the three-color LEDs is mixed by the optical system and focuses on the reflector of the first piezoelectric deflector 120. For the red color of the radiation, HLMP-AL00 LEDs with a light intensity of 400 mcd were used [14, p. 71], a wavelength of 0.590 μm at a current of 0.02 A. Green LEDs emit HLMP-AM00 with a light intensity of 800 μd, a wavelength of 0.526 μm at a current of 0.02 A. Blue LEDs emit HLMP-AB00 with a light intensity of 300 μd , a wavelength of 0.475 μm at a current of 0.02 A. The brightness modulation is performed by switching on the radiation of the number of LEDs according to the weight of the code discharge according to Table 2. Color mixing is carried out by the optical system when the radiation is focused on the piezoelectric reflector 120 line scan. The brightness, saturation and hue of the resulting color on the screen 131 are determined
total energy and the mutual ratio of the components of the three colors. The scanning element on the screen is adopted in 0.5 mm ² / 0.7 x 0.7 mm /, the maximum brightness of the scanning element on the screen without taking into account losses when projecting radiation to the screen is

where in the numerator is the total light intensity from the emitter,

- coefficients of the binary code in 4, 5, 6, 7, 8 bits,
0,5 · 10 ^-6 m ² - the area of the deploying element on the screen.

The light intensity equation for red / 400 mcd / and green / 800 mcd / LEDs with blue / 300 mcd / is additionally attenuated by light filters. The maximum brightness of the scanning spot, taking into account losses in the projection to the screen 50% is 7,171,875 cd / m ² and will be sufficient to monitor the on-screen image with vivid color with the persistence of vision / averaging the brightness of the screen frame period /. The mixed radiation is directed to the reflector of the piezoelectric deflector 120, which, according to the control voltages from the amplifier 119, performs a horizontal line scan of the beam on the reflector of the second piezoelectric deflector 128, performing a frame scan along with the horizontal scan on the screen. The emitter LEDs consume: 36 _pcs · / 5 V · 0.02 A / = 3.6 VA. The piezoelectric deflectors 120, 128 are controlled by control voltages from the horizontal scanning unit 118 and the vertical scanning unit 123. The horizontal scan voltage (as in block 7) has a triangular shape with a frequency of 7812.5 Hz, which is obtained by dividing 15625 Hz by two in the divider 117. The control voltage period is equal to the duration of two lines.

Block 118 consists of a master oscillator and an output stage. Amplifier 119 amplifies the control voltage from block 118 and drives the piezoelectric deflector 120 in oscillatory motion with a frequency of 7812.5 Hz. Piezoelectric deflector 128 oscillates at a frequency of 25 Hz. Summing amplifier 126 is identical to amplifier 17 on the transmitting side. The width of the reflective strip of the piezoelectric deflector 120 0.02 mm, the length of the strip of the piezoelectric deflector 128: 0.02 mm · 854 _count = 17.08 mm. The beginning of the frame scan is determined by the moment of coincidence of the leading edges of the horizontal and frame sync pulses at the input of the And element 124. The summing amplifier 126 produces a stepwise linearly increasing voltage / Fig. 3 / for the first field of the frame and a stepwise decreasing voltage for the second field of the frame. The condition for the block 109 to issue a frame clock is the simultaneous arrival of codes 11111111 from its formers 70, 96 pulses at its two inputs.

 System operation.

From the photodetectors 23, 24, 25 of the photoelectric converter 1, three analog video signals of three colors, after amplification by preliminary amplifiers, are fed to the ADC inputs 30, 31, 32. Two audio signals are fed to the ADC 33, 34. The video signal E _{G is} converted into an 8-bit code with a frequency 13.5 MHz, video signals E _R , E _{B are} converted to 8-bit codes with a frequency of 6.75 MHz, audio signals are converted to 16-bit codes with a frequency of 46875 Hz. The first 37 and second 38 code generators form two code streams: the first video signal code stream E _R , E _B , and the second code stream E _G. At the outputs of the shapers 37, 38 codes, the unit symbols in the codes are represented by positive and negative half-sine waves of a frequency of 54 MHz, which modulate the carrier frequencies in the transmitter 41. The clock frequency is 54 MHz. The information transfer speed is 216 Mbit / s, its playback speed with an image of 324 Mbit / s. Digital information is transmitted by the upper side frequencies of the carrier frequencies. Two radio signals are received at the receiving side antenna.

The first and second paths for receiving and processing codes produce radio frequency amplification, detection and separation of codes on two channels. Dedicated line and frame clocks organize the order of the receiving side. Adders 65, 82 with blocks of delay elements receive the codes of the intermediate samples of the video signals E _R and E _B in the intervals between the transmitted codes from the transmitting side. Codes with a frequency of 13.5 MHz come to the inputs of the blocks of pulse amplifiers 113, 114, 115. Block 116 modulation of radiation produces, according to the codes, the emission of LEDs. Mixed radiation is deployed by piezoelectric deflectors 120, 128 on screen 131. The claimed system can be applied to digital television in the UHF band allocated for analog television without interfering with the latter.

Used sources
1. Patent N 2103839, cl. H 04 N 11/04, bull. N 3 for 1998.

 2. Patent N 2128890, cl. H 04 N 11/04, bull. N 10 for 1999, a prototype.

 3. Handbook of laser technology, ed. Bayborodina, Kiev, 1978, p. 192-194.

 4. Fridland I.V., Soshnikov V.G. "Automatic control systems in video recording devices", M., 1988, p. 118, fig. 5.5, p. 122, fig. 5.10.

 5. Ilyin V.A. "Telecontrol and telemetry", M., 1982, p. 274.

 6. Cooper V.A. "Generators of linearly varying voltage", M., 1988, p. 57, 106.

 7. Digital integrated circuits, Minsk, 1991, p. 128, 231, 258.

 8. Shilo VA, "Popular digital microcircuits", Chelyabinsk, 1989, p. 222.

 9. Handbook of Automation, ed. V.E. Nize, M., 1983, p. 169.

 10. Radio transmitting devices, M. S. Shumilin and others. M., 1981, p. 234, fig. 13.3c, p. 235.

 11. Brodsky M.A. "TVs of color image", Minsk, 1988, p. 86, fig. 2.55, p. 132, fig. 4.2.

 12. Handbook of Broadcasting, ed. A.V. Vykhodtsa, Kiev, 1981, p. 112, fig. 81.

 13. Barkan V.F., Zhdanov V.K. "Amplification and impulse technology", M., 1981, p. 209.

 14. Radio N 7, 1998, p. 71.

 15. Calculation of elements of laser scanning systems, EV Dneprovsky and others. Minsk, 1986, p. 56, tab. 2.3.

Claims (1)

A digital television system containing the transmitting side of the photoelectric converter, the first, second, third analog-to-digital converters (ADCs), the inputs of which are connected to the corresponding outputs of the photoelectric converter, the fourth and fifth ADCs, to the information inputs of which sound signals are connected in series sinusoidal oscillator and frequency synthesizer, first and second video signal shapers, first and third information input the first video signal shaper is connected to the outputs of the first and fourth ADCs, the first and second information inputs of the second video signal shaper are connected to the outputs of the second and fifth ADCs, and the radio transmitter containing the corresponding number of channels, the inputs of which are connected to the corresponding output of the frequency synthesizer, and each channel includes a carrier frequency generator and an output amplifier, the first output of the frequency synthesizer is connected to the clock input of the second ADC and to the first control input of the second video signal code generator, the second output of the frequency synthesizer is connected to the first control inputs of the fourth and fifth ADCs, to the first control input of the first video code generator and to the second control input of the second video code generator, the third output of the frequency synthesizer is connected to the second control inputs of the fourth and fifth ADCs the fourth output of the frequency synthesizer is connected respectively to the second and third control inputs of the first and second shapers of the video signal codes, the fifth you the frequency synthesizer is connected to the third and fourth control inputs of the first and second video signal shapers and to the third control inputs of the fourth and fifth ADCs, the photoelectric converter contains a lens, a first piezoelectric reflector with an end face located in the focal plane of the lens, and a second piezoelectric deflector with an end face reflector optically coupled to the reflector of the first piezoelectric deflector, serially connected to the horizontal scanning unit, the input of which is connected to the seventh output of frequency synthesizer, and the first amplifier, the output of which is connected to the first input of the first piezoelectric deflector, the first source of positive reference voltage, the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first a piezoelectric deflector, connected in series to a frame-scan unit, the first and second inputs of which are connected respectively to the fifth and sixth outputs of the synthesizer t, and a second amplifier whose output is connected to the first input of the second piezoelectric deflector, a third source of positive reference voltage, the output of which is connected to the second inputs of the second amplifier and second piezoelectric deflector, a fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and second piezoelectric deflector , the first and second dichroic mirrors, located one after another and against the reflector of the second piezoelectric deflector, three micro-lenses, three pre-amplifiers, output which are the outputs of the photoelectric converter, the input window of the first photodetector is optically connected through the first micro lens and the first dichroic mirror to the reflector of the second piezoelectric deflector, the input window of the second photodetector is optically connected through the second micro lens and through both dichroic mirrors to the reflector of the second piezoelectric deflector, the input window of the third photodetector is optically connected through the third micro lens, the second dichroic mirror and through the first dichroic mirror with a reflector of the second the piezoelectric deflector, the frame scanning unit of the photoelectric converter contains a series element And, a master oscillator and a summing amplifier, the second input of which is connected to the first input of the element And, the control input of the summing amplifier is connected to the output of the element And, the first, second and third cerebral palsy are identical and each is made the composition of the series-connected amplifier and piezoelectric deflector with a reflector at the end, the first source of positive reference voltage, the output of which is connected to the second input I will give an amplifier and a piezoelectric deflector, a second source of negative reference voltage, the output of which is connected to the third inputs of the amplifier and a piezoelectric deflector, an emitter as part of a pulsed LED, a slit diaphragm and a micro lens, and an encoder whose outputs are ADC outputs, and the control input is a pulse LED input, the fourth and the fifth ADC are identical and each contains a series-connected voltage divider, a key block, a matching amplifier, an amplifier, and a piezoelectric deflector with a reflector at the end, ne the first source of positive reference voltage, the output of which is connected to the second inputs of the amplifier and the piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the amplifier and the piezoelectric deflector, an emitter consisting of a pulsed LED, a slit diaphragm, and a micro lens, the first decoder, encoder, and the second decoder, the output of which is connected to the corresponding inputs of the first decoder and the inputs of the key block, contains serially connected a pulse counter, a third decoder and a block of registers, the other inputs of which are connected to the outputs of the encoder and its first three control inputs are connected to the three outputs of the third decoder, the input of the ADC is the input of the voltage divider, the first control input is the counter input of the pulse counter, the second is the combined pulse input LED and the fourth control input of the register block, the third is the control input of the pulse counter, the output is the output of the register block, the first encoder of video signals contains um four channels whose outputs are combined, the first channel includes the first block of AND elements, the first and second OR elements and the first output switch, and the first self-propelled pulse distributor, the second channel includes the second block of AND elements, the third and fourth OR, and the second output key, and the second self-propelled pulse distributor, the first inputs of the first and second blocks of elements And are the first and second information inputs of the first shaper of video signal codes, the other inputs of the first block of AND elements are connected to the outputs of the first self-propelled pulse distributor, the second inputs of the second block of elements AND are connected to the outputs of the second self-propelled pulse distributor, the third channel includes the third block of AND elements and the fifth OR element, and the third self-propelled pulse distributor, the output of the fifth the OR element is connected to the second input of the second OR element, the fourth channel includes a fourth block of AND elements and a sixth OR element, and a fourth self-propelled pulse distributor, the output of the sixth OR element is connected to the second input of the fourth OR element, the second inputs of the third and fourth blocks of elements AND are connected respectively to the outputs of the third and fourth self-propelled pulse distributors, the first inputs of the third and fourth blocks of AND elements are the third information input of the first driver video signal codes, which includes the first and second keys and series-connected pulse counter and decoder, two outputs of which connected respectively to the first and second control inputs of the first and second keys, the output of the first key is connected to the inputs of the first and second self-propelled pulse distributors, the output of the second key is connected to the inputs of the third and fourth self-propelled pulse distributors, the output of the first video code generator is the combined output of the output keys, the first control input is the combined key input and the counting input of the pulse counter, the second control input is the combined signal input x inputs of the first and second output keys, the third control input is the control input of the pulse counter, the second encoder of the video signals contains a trigger and a switching unit and four channels connected in series, the inputs of the first and second channels are connected to the corresponding outputs of the switching unit, and the outputs of the four channels are combined, the first channel includes a series-connected first block of AND elements, a first and second OR element, and a first output switch, and a first self-propelled pulse distributor, in The second channel includes the second block of AND elements, the third and fourth OR elements, and the second output switch, and the second self-propelled pulse distributor, the first inputs of the first and second blocks of AND elements connected to the corresponding outputs of the switching unit, the second inputs of the first block of AND elements connected to the outputs the first self-propelled pulse distributor, the second inputs of the second block of elements AND are connected to the outputs of the second self-propelled pulse distributor, the third channel includes a series connection The third block of AND elements and the fifth OR element, and the third self-propelled pulse distributor, the output of the fifth OR element is connected to the second input of the second OR element, the fourth channel includes the fourth block of AND elements and the sixth OR element, and the fourth self-propelled pulse distributor, the output of the sixth the OR element is connected to the second input of the fourth OR element, the second inputs of the third and fourth blocks of AND elements are connected to the outputs of the third and fourth self-propelled pulse distributors, in The second driver of the video signal codes includes the first and second keys and a pulse counter and a decoder connected in series, the two outputs of which are connected to the first and second control inputs of the first and second keys, the output of the first key is connected to the inputs of the first and second self-propelled pulse distributors, the output of the second key connected to the inputs of the third and fourth self-propelled pulse distributors, the output of the second video signal shaper is the combined output of the output key th, the first and second information inputs are the inputs of the switching unit, the inputs of the third and fourth blocks of elements And, the first control input is the trigger input, the second control input is the combined key input and the counting input of the pulse counter, the third control input is the combined input of the signal inputs of the first and second output keys, the fourth control input is the control input of the pulse counter, and containing the receiving side, including the antenna, the touch control unit, the first t the act of receiving and processing codes of video signals, the second path of receiving and processing codes of video signals, the inputs of which are connected to the antenna, three blocks of delay elements connected respectively to the inputs of the first, second, third blocks of OR elements, first, second, third blocks of pulse amplifiers, modulation block radiation, a series-connected frequency divider, a horizontal scanning unit, a first amplifier and a first piezoelectric deflector with a reflector at the end, the first source of positive reference voltage, the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector, a second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector, connected in series to the frame scan unit, the second amplifier and the second piezoelectric deflector with a reflector at the end, the third source of the positive reference voltage, output which is connected to the second inputs of the second amplifier and the second piezoelectric deflector, the fourth source of negative reference voltage, the output of which is connected n to the third inputs of the second amplifier and the second piezoelectric deflector, and a matte screen located opposite the reflector of the second piezoelectric deflector, which is optically connected to the reflector of the first piezoelectric deflector, which is optically coupled to the radiating side of the radiation modulation unit, the corresponding inputs of which are connected to the outputs of the first, second, and third blocks pulse amplifiers, the inputs of which are connected through the first, second and third blocks of elements OR to the outputs of the corresponding three blocks of delay elements, the receiving side it includes two sound channels, each of which contains a series-connected digital-to-analog converter (DAC), a low-pass filter, a power amplifier and a loudspeaker, the first path for receiving and processing video signal codes contains a series-connected radio signal receiving unit, a radio frequency amplifier, and a bipolar amplitude detector , channel for processing video signal codes E _R and a channel for processing video signal codes E _B , channel for processing video signal codes E _R includes a first pulse shaper connected in series, the input of which is connected to the first output of the bipolar amplitude detector of its path, the first and second keys and the first register of the video signal E _R , the third key and the first block of sound registers are connected in series, the input of the third key is connected to the output of the first key, and the fourth key and the second register of video signal E are connected in series _R the outputs of which are connected to the inputs of the block of delay elements, the channel for processing video signal codes E _B includes a second pulse shaper connected in series, the input of which is connected to the second output of the bipolar amplitude detector of its path, the fifth and sixth keys and the first register of the video signal E _B , the seventh key and the second block of sound registers are connected in series, the seventh key input is connected to the fifth key output, and the eighth key and the second video signal register are connected in series E _B the outputs of which are connected to the inputs of the block of delay elements, the outputs of the first and second blocks of sound registers are connected to the inputs of the first DAC of the sound codes, the second path for receiving and processing video signal codes contains serially connected radio signal receiving unit, radio frequency amplifier, bipolar amplitude detector, and two code processing channels video signal E _G , the first channel for processing video signal codes E _G includes a first pulse shaper connected in series, the input of which is connected to the first output of the bipolar amplitude detector of its path, the first key and the first register of the video signal E _G , and the second key and the first block of sound registers connected in series, the input of the second key is connected to the output of the first key, the second channel for processing the video signal codes E _G includes a second pulse shaper connected in series, the input of which is connected to the second output of the bipolar amplitude detector of its path, the third key and the second register of the video signal E _G , and the fourth key and the second block of sound registers are connected in series, the input of the fourth key is connected to the output of the third key, the outputs of the second register of the video signal E _G connected to the inputs of the block of delay elements, the outputs of the first and second blocks of sound registers are connected to the inputs of the second DAC of the sound codes, the outputs of the touch control unit are connected in parallel to the corresponding inputs of the blocks of reception of the radio signal in the first and second paths of the reception and processing of codes of video signals, the radiation modulation unit includes an optical the system, the output of which is optically coupled by the reflector of the first piezoelectric deflector, the frame-scan unit contains a series-connected element And, the master oscillator and the sum the amplifying amplifier, the output of which is the output of the vertical scanning unit and is connected to the first input of the second amplifier, the second input of the summing amplifier is connected to the first input of the And element, its control input is connected to the output of the And element, the summing amplifiers in the vertical and vertical units of the receiving and transmitting sides are identical and each contains a serially connected pulse counter and decoder, first and second keys, first and second pulse shapers, and an output amplifier, signal inputs of the first and second keys it and the counting input of the pulse counter are combined and are the second input of the summing amplifier, the first input of which is the first input of the output amplifier, the first control input of the first key, the second control input of the second key and the control input of the pulse counter are combined and are the control input of the summing amplifier, the second control input the first key and the first control input of the second key are combined and connected to the output of the decoder, the output of the first key is connected to the input of the first pulse shaper , the output of the second key is connected to the input of the second pulse shaper, the outputs of the first and second pulse shapers are combined and connected to the second input of the output amplifier, the output of which is the output of the summing amplifier, characterized in that on the transmitting side in the first shaper of the video signal codes the third inputs of the second and fourth OR elements are the fourth and fifth information inputs, and in the second video signal generator, the third inputs of the second and fourth OR elements are the third and the fourth information inputs, the second information input of the first encoder of video signals is connected to the output of the third ADC, and the first and second self-propelled pulse distributors are introduced, the input of the first self-propelled pulse distributor is connected to the fifth output of the frequency synthesizer, its outputs are combined and the combined output is connected to the fourth information input the first driver of the codes of video signals and to the third information input of the second driver of the codes of video signals, the input of the second self-propelled the pulse distributor is connected to the sixth output of the frequency synthesizer, its outputs are combined and the combined output is connected to the fifth information input of the first video signal shaper and the fourth information input of the second video signal shaper, the clock inputs of the first and third ADCs are connected to the second output of the frequency synthesizer, in the first, the second and third ADCs introduced a line of multi-element photodetector, the input of which is optically connected to the reflector of the piezo-reflector ADC, and its outputs are connected to the input m of the encoder, a multi-element photodetector line is introduced in the fourth and fifth ADCs, the input of which is optically connected to the reflector of the ADC piezoelectric deflector, and its outputs are connected to the corresponding inputs of the first decoder, the radio signal transmitter is made two-channel, into each channel of which a single-band signal shaper is inserted, the first input of which is connected to the output of the carrier frequency generator, and the output is connected to the input of the output amplifier of its channel, the second inputs of the shapers of single-band signals are connected: channel to the output of the first generator of video signal codes, the second channel to the output of the second generator of video signals, each driver of a single-band signal includes a ring modulator and a bandpass filter connected in series, the inputs of the carrier frequency generators of the first and second channels are connected to the eighth output of the frequency synthesizer, a channel is introduced on the receiving side generating control signals, comprising a sequentially connected horizontal sync pulse allocation unit, a discrete pulse generator and a self-propelled pulse distributor, a key, a pulse counter and a decoder connected in series, a pulse shaper and a frame sync extraction block, a key signal input and a pulse shaper input are combined and connected to the first output of the sampling pulse generator, the output of the pulse shaper is connected in parallel to the control inputs of the first and the fifth key in the video signal processing channels E _R and E _B respectively, and to the control inputs of the first and third keys in the first and second channels of processing video signal codes E _G , the first control input of the key, the input of the frequency divider and the first input of the vertical scanning unit are combined and connected to the output of the horizontal sync pulse allocation unit, the first and second inputs of which are connected to the outputs of the first pulse shapers in the channel for processing video signal codes E _R and in the first channel for processing the video signal codes E _G , the first output of the decoder is connected to the control inputs of the third key in the channel for processing video signal codes E _R of the seventh key in the channel for processing video signal codes E _B to the input of the second key in the first channel for processing video signal codes E _G and to the input of the fourth key in the second channel of the processing of video signal codes E _G , the second output of the decoder is connected in parallel to the control input of the pulse counter, to the second control input of the key of the channel for generating control signals, to the second control inputs of the third and seventh keys in the channel for processing video signal codes E _R and the channel for processing video signal codes E _B to the second control inputs of the second and fourth keys of the first and second channels of the processing of video signal codes E _G , the first and second inputs of the frame sync pulse allocation unit are connected to the outputs of the second pulse shapers in the channel for processing the video signal codes E _B and in the second channel for processing video signal codes E _G , the output of the frame sync selection block is connected to the second input of the frame scan unit, the horizontal sync block selection block and the frame clock block are identical and each includes two pulse counters, two NOT elements, one AND element and a diode, the inputs of the first and second elements are NOT connected to the inputs the first and second pulse counters, the outputs of the elements NOT and the output of the AND element through a diode are combined and connected to the control inputs of the pulse counters, the outputs of the first and second pulse counters are connected s to the inputs of the element And whose output is the output of the pulses, the inputs of the pulse counters are connected: the block allocation of the horizontal sync pulse to the outputs of the first pulse shapers in the first and second paths of receiving and processing codes of video signals, the block allocation of the frame sync pulse to the outputs of the second pulse shapers in the first and second the paths for receiving and processing video signal codes, a sampling pulse generator contains three self-propelled pulse distributors connected in series, the input is self-propelled pulse distributor, the first output is the output of the third self-propelled pulse distributor, the second output is the output of the first self-propelled pulse distributor, a trigger is inserted into the first path for receiving and processing video signal codes, the input of which is connected to the first output of the sampling pulse generator of the control signal generation channel, the first output the trigger is connected in parallel to the first control input of the second key and to the second control input of the fourth key in the processing channel video signal E _R , to the first control input of the sixth key and to the second control input of the eighth key in the channel for processing video signal codes E _B , the second trigger output is connected in parallel to the second control input of the second key and to the first control input of the fourth key in the channel for processing video signal codes E _R , to the second control input of the sixth key and to the first control input of the eighth key in the channel for processing video signal codes E _B in the video signal processing channel E _R information inputs of the first and second registers of the video signal E _R combined and connected to the output of the second key, the third and fourth video signal registers E are introduced into the channel _R whose information inputs are combined and connected to the output of the fourth key, a delayed element is connected in series, the input of which is connected to the second control input of the second key, and the first trigger, the first output of which is connected to the first control input of the second video signal register E _R , the second output is connected to the first control input of the video signal register E _R , a second trigger is introduced, the input of which is connected to the first control input of the second key, the first output is connected to the first control input of the third video signal register E _R , the second output is connected to the first control input of the fourth video signal register E _R , an adder was introduced, the first information inputs of which are connected to the outputs of the second video signal register E _R and through diodes to the outputs of the first video signal register E _R , the second information inputs of the adder connected to the outputs of the fourth register of the video signal E _R and through diodes - to the outputs of the third register of the video signal E _R the outputs of which are connected to the inputs of the first block of delay elements, the outputs of the first register of the video signal E _R connected to the inputs of the second block of delay elements, the outputs of the adder are connected to the inputs of the third block of delay elements, the outputs of the first, second and third blocks of delay elements are combined and connected to the inputs of the first block of OR elements in the channel for processing video signal codes E _B information inputs of the first and second registers of the video signal E _B combined and connected to the output of the sixth key, the third and fourth video signal registers E are introduced into the channel _B whose information inputs are combined and connected to the output of the eighth key, a delayed element is connected in series, the input of which is connected to the second control input of the sixth key, and the first trigger, the first output of which is connected to the first control input of the second video signal register E _B , the second output is connected to the first control input of the first register of the video signal E _B , a second trigger is introduced, the input of which is connected to the first control input of the sixth key, the first output is connected to the first control input of the third video signal register E _B , the second output is connected to the first control input of the fourth video signal register E _B , an adder is introduced, the first information inputs of which are connected to the outputs of the second video signal register E _B and through diodes to the outputs of the first register of the video signal E _R , the second information inputs of the adder are connected to the outputs of the fourth video signal E _B and through diodes to the outputs of the third register of the video signal E _B the outputs of which are connected to the inputs of the first block of delay elements, the outputs of the first register of the video signal E _B connected to the inputs of the second block of delay elements, the outputs of the adder are connected to the inputs of the third block of delay elements, the outputs of the first, second and third blocks of delay elements are respectively combined and connected to the inputs of the second block of elements OR, in the first channel for processing video signal codes E _G a block of delay elements has been introduced, the inputs of which are connected to the outputs of the first video signal register E _G , and its outputs are combined with the corresponding outputs of the block of delay elements of the second channel for processing video signal codes E _G and connected to the inputs of the third block of OR elements, the clock inputs of all the video signal registers, both adders and blocks of sound registers are connected in parallel to the output of the self-propelled pulse distributor in the channel for generating control signals, the control inputs of the blocks of sound registers are connected in parallel to the second output of the sampling pulse generator in the channel of formation control signals, an emitter of three primary colors is introduced into the radiation modulation unit, containing the corresponding number of LEDs each and of colors and located in the focal plane of the optical system, the inputs of the emitter of the three primary colors are connected to the outputs of the respective blocks of pulse amplifiers, the output of the block through the optical system is connected to the reflector of the first piezoelectric deflector.

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