RU2194370C2 - Tv digital system of high definition - Google Patents

Abstract

FIELD: radio communication, television starting from decimeter range of ground TV networks allocated for analog television. SUBSTANCE: technical result is reduced power input of system thanks to exclusion of two transmission channels on transmitting side and two reception paths on receiving side and enhanced TV image resolution. This technical result is achieved by insertion of first and second power-operated pulse distributors on transmitting side, of channel forming control signals, unit processing codes of video signals, first and second delay elements and adder into channel E_R of video signal and into channel E_G of video signal, unit of delay elements into first channel E_B of video signal, second unit of delay elements and adder into second channel E_B of video signal on receiving side. In addition three units of pulse amplifiers are inserted into equipment on receiving side. Each radiator of radiation modulation unit includes light-emitting diodes of three basic colors. Clock frequency in system is 70 MHz, occupied frequency band is 252 Hz, information transmission rate is 280 Mbit/s and information presentation rate is 840 Mbit/s. EFFECT: reduced power input into system. 18 dwg, 2 tbl

Description

 The invention relates to radio communications technology and can be used for television broadcasting, starting with the decimeter range of terrestrial TV networks reserved for analog television.

The digital television system [1] was adopted as a prototype, it includes a transmitting side, including a photoelectric converter, including a lens, first and second piezoelectric reflectors with a reflector at the end, horizontal and vertical scanning units, two sources of positive reference voltage, two sources of negative reference voltage, two dichroic mirrors, three micro-lenses, three photodetectors and three pre-amplifiers, five ADCs, a sine wave oscillator, a frequency synthesizer, a signal code generator synchronization signals, video signal generator E _R , video signal generator E _G , video signal generator E _B , four-channel radio signal transmitter, and a receiving side including a touch control unit, a signal reception and processing channel for synchronization codes, a signal reception and processing channel for E _R , a path for receiving and processing video codes E _G , a path for receiving and processing video codes E _B , three blocks of delay elements, three blocks of OR elements, three blocks of pulse amplifiers, a modulation block of radiation containing three emitters, three sets of optical fibers and an optical system, the receiving side includes a frequency divider, horizontal and vertical units, two piezoelectric deflectors with a reflector at the end, two sources of positive reference voltage, two sources of negative reference voltage, matte screen and two sound channels escorts. Three ADCs convert analog video signals of primary colors to 8-bit parallel codes, the fourth and fifth ADCs convert audio signals to 16-bit codes. The transmitting side emits four streams of codes: the first is the synchronization signals and three streams of codes of video signals E _R , E _G. E _B , which modulate the amplitude of the four carrier frequencies. On the receiving side, four radio signals are received, amplified, detected by bipolar amplitude detectors, and without converting the codes into analog video signals, a color image is reproduced on the matte screen, and codes of audio signals are converted into analog ones. The clock frequency of 54 MHz, occupied band on the air 432 Hz. The disadvantages of the prototype are: the transmission of information on four radio channels and the insufficient resolution of the television image in a raster of 625 lines.

 The aim of the invention is to reduce the energy consumption of the system and increase the resolution of the television image. The technical result of the claimed device is to reduce the energy consumption of the system by the exception in the transmitting side of two transmission channels, in the receiving side of two reception paths and increasing the resolution of the television image when playing a raster of 1000 active lines with the number of samples 1400 per line. Resolution Elements in Frame 1,400,000.

The inventive system is simultaneous, color coding on the transmitting side 2: 2: 4, when playing 4: 4: 4, the sampling frequency of the video signals E _R , E _G , on the transmitting side 8.75 MHz, on the receiving side when playing 17.5 MHz . The sampling frequency of the video signal E _In the transmitting side and the receiving side of 17.5 MHz. Separate video coding by linear pulse code modulation. The upper side frequency of the carrier and the polarity of the code signals carry information about the color tones R and G, and the lower side frequency of the same carrier carries the color tone B. Information about the brightness carry the amplitude codes of the video signals. The color saturation is set by the emission spectrum of the LEDs used in the emitters, the narrower their spectrum, the higher the color saturation. The number of encoded samples E _R , E _G per line on the transmitting side 700, when played on the receiving side 1400. The number of encoded samples of the video signal E _B on the transmitting side 1400. The number of encoded lines in a raster on the transmitting side 500, the number of lines in the raster when playing 1000 , all active, frames 25, fields in frame 2. Technical parameters of the system in the table. 1. The transmitting side generates two stream of codes: the first stream of video signal codes E _R and E _G , the second stream of codes E _B. Two-channel transmitter, one carrier frequency is used. The receiving side receives two radio signals by two paths of receiving and processing codes of video signals, selects lowercase / SSI / and frame / CSI / clock pulses, divides digital streams along its channels, separates codes of audio signals, doubles the frequency of the video signals Е _R and Е _G , doubles the number of lines in a raster, converts codes by electron-optical scanning into a color image on a matte screen. Sound codes are transmitted four codes at the end of each line. The essence of the claimed system is that in a digital high-definition television system containing a transmitting side, which includes a photoelectric converter, three analog-to-digital converters / ADC /, the inputs of which are connected to the outputs of the photoelectric converter, the fourth and fifth ADCs, to the information inputs of which are fed sound signals, a sine wave generator and a frequency synthesizer, first and second video signal shapers and a radio signal transmitter including two channels, the first of which includes a carrier frequency amplifier, an amplitude modulator and an output amplifier, the second channel includes an amplitude modulator and an output amplifier, a receiving side including an antenna, a touch control unit, a first video signal reception and processing path including a radio signal receiving unit, a radio frequency amplifier, bipolar amplitude detector, two PFN channel video signal E _R, E containing video register _R, the first key and the first block of the audio registers, a video channel E _G, soda zhaschy Register video E _G, the second key and the second block of the audio registers, a second path for receiving and processing video codes, comprising a reception unit of radio signal, a radio frequency amplifier, a bipolar amplitude detector, two PFN first channel video signal _EV having a first register video signal _EV , the third switch and the third sound unit registers the second channel video signal _EV having a second video signal _EV register unit delay elements, the fourth switch and the fourth block of the audio registers and including three unit and pulse amplifiers, a radiation modulation unit containing two emitters and an optical system, a horizontal and vertical scanning unit, and a matte screen, the first and second self-propelled pulse distributors are introduced on the transmitting side, in the transmitter the input of the amplitude modulator of the second channel is connected to the output of the carrier frequency amplifier of the first channel, on the receiving side a channel for generating control signals is introduced, including a block for selecting a horizontal sync pulse / SSI /, a frequency synthesizer, a self-propelled pulse distributor, cells h, counter pulses, the decoder and the block selection frame pulse in channel video signal E _R introduced processing unit codes a video signal E _R, the first block elements delays the adder and second block elements delays in channel video E _G introduced video block codes processing E _G, first unit delay elements, an adder, and a second unit delay elements, the first channel video signal _EV introduced unit delay elements, the second channel video signal _EV introduced second unit delay element and an adder, and at the receiving end is entered the fourth, fifth, sixth blocks of pulse amplifiers, in the radiation modulation block each of the emitters contains the corresponding number of LEDs of three primary colors, the first emitter is located above the second, the emission plane of both is located in the rear focal plane of the optical system, the inputs of the first emitter are connected to the outputs of the first, second, third blocks of pulse amplifiers, the inputs of the second emitter are connected to the outputs of the fourth, fifth, sixth blocks of pulse amplifiers.

The block diagram of the transmitting side in figure 1, the formation of the raster and the types of control voltages of the sweep in figure 2, the functional diagram of the ADC video signal in Fig. 3, a functional diagram of the ADC of the sound signal of FIG. 4, a piezoelectric deflector structure of FIG. 5, a functional diagram of a first video signal encoder in FIG. 6, a functional diagram of the second video code generator / E _B / in FIG. 7, the sequence of digital streams in FIG. 8, a block diagram of the receiving side in FIG. 9, a circuit diagram of a bipolar amplitude detector in FIG. 10, a block diagram of a horizontal sync pulse allocation unit / SSI / in FIG. 11, a frame sync pulse allocation block / CSI / in FIG. 12, a summing amplifier on Fig, functional block diagram of the processing of video signal codes E _R / E _B / on Fig, radiation modulation block on Fig, timing diagrams of the system in Fig. 16, the spectra of the amplitude-modulated signal in the channels of the transmitter of FIG.

The transmitting side / Fig. 1/ includes a photoelectric transducer 1, which is a sensor of three primary colors, which is made of a lens 2, a first piezoelectric deflector 3 with a reflector at the end, the first source of positive reference voltage 4, the second source 5 of negative reference voltage, the first amplifier 5, block 7 line scan from the master oscillator 8 and the output stage 9, the second piezoelectric deflector 10 with a reflector at the end, the third source 11 of the positive reference voltage, the fourth source 12 is negative reference voltage, the second amplifier 13, the block 14 frame scan of the element And 15, the master oscillator 16 and the summing amplifier 17, the first 18 and second 19 dichroic mirrors, the first 20, second 21, third 22 micro lenses, the first 23, second 24, third 25 photodetectors, the first 26, the second 27, the third 28 preamplifiers. The photoelectric converter 1 is part of the transmitting television camera, which includes the first ADC 29 / video signal E _R / second ADC 30 / video signal E _G /, the third ADC 31 / video signal E _B /. The transmitting side includes a fourth ADC 32 and a fifth ADC 33 of a sound signal, serially connected a master oscillator 34 of a sinusoidal oscillation and a synthesizer 35 frequencies, a first driver 36 of the codes of the video signals, the second driver 37 of the codes of the video signals, the first self-propelled distributor 38 of the pulses, forming the horizontal sync pulse code, the second self-propelled a pulse distributor 39 forming a frame sync pulse code. Transmitter 40 has two channels. The first channel contains a serially connected carrier frequency amplifier 41, an amplitude modulator 42 and an output amplifier 43, the second channel contains an amplitude modulator 44 and an output amplifier 45. The first amplitude modulator 42 consists of a ring modulator that suppresses the carrier frequency and a bandpass filter [2 s .234], filtering the lower side frequency in the spectrum of the amplitude-modulated signal. The second amplitude modulator 44 consists of a series-connected ring modulator that suppresses the carrier frequency, and a band-pass filter that filters the upper side frequency / Fig.17/.

 The ADCs 29, 30, 31 are identical (Fig. 3/), each contains a series-connected video amplifier 46 and a piezo-deflector 47 with a reflector at the end, a source of positive reference voltage 48, a source of negative reference voltage 49, an emitter 50, including a pulsed LED 51, a slit diaphragm 52 and a micro lens 53, a quantizing line of 54 optical fibers, a block 55 of photodetectors and an encoder 56.

 The ADCs 32, 33 are identical and each contains / Fig. 4/ voltage divider 57, key block 58, matching amplifier 59, amplifier 60 and piezoelectric deflector 61 with a reflector at the end, a positive reference voltage source 62, a negative reference voltage source 63, an emitter 64 of a pulse LED 65, a slit aperture 66, and a micro lens 67, a quantizing line of 68 optical fibers, a photodetector unit 69, a first decoder 70, an encoder 71, a second decoder 72, a pulse counter 73, a third decoder 74 and a register block 75. All piezoelectric deflectors are structurally identical (Fig. 5/), each includes [3 p.118] the first 76 and the second 77 piezo plates, the inner electrode 78, the first 79 and the second 80 external electrodes, one end of the piezo plates is fixed in the holder 81, fixed to the free end light reflector 82.

 The first generator 36 codes of video signals includes / Fig.6/ three channels. The first and second channels are identical. The first includes a series-connected block of 83 AND elements, the first 84 and second 85 OR elements, and the first output switch 86, and the first self-propelled pulse distributor 87. The second channel includes a block of 88 AND elements, a third 89 and a fourth 90 OR elements and an output switch 91, and a second self-propelled pulse distributor 92. The third channel includes a series-connected first block of 93 AND elements and a fifth OR element 94, and a first self-propelled pulse distributor 95, series-connected a second block 96 of AND elements and a sixth OR element 97, and a second self-propelled pulse distributor 98, includes the first 99 and second 100 keys , and series-connected pulse counter 101 and decoder 102.

 The second generator 37 of the codes of the video signals includes / Fig.7/ connected in series trigger 103 and block 104 switching, and three channels. The first and second channels are identical. The first includes a series-connected block of elements 105 and, the first 106 and second 107 OR elements and an output switch 108, and a self-propelled pulse distributor 109, the second channel includes a series-connected block of 110 AND elements, a third 111 and a fourth 112 OR elements, and an output switch 113, and a self-propelled pulse distributor 114, the third channel includes a block of 115 elements and a fifth OR element 116, and a self-propelled pulse distributor 117, a second block of 118 elements and a sixth OR element 119, and a self-propelled pulse distributor 120. And includes the first 121 and second 122 keys and serially connected pulse counter 123 and decoder 124.

The receiving side / digital television receiver / contains / Fig.9/ antenna, the unit 125 of the touch control, the first and second paths for receiving and processing codes of video signals, a channel for generating control signals. The first path for receiving and processing video signal codes includes a radio signal reception unit 126, a radio frequency amplifier 127, a bipolar amplitude detector 128, first 129 and second 130 pulse shapers, a video signal channel E _R , which contains a video signal register E _R , a video signal code processing unit E _R , a first block of delay elements 133, an adder 134 and a second block of delay elements 135, a first key 136 and a first block of sound registers 137, a video signal channel E _G , which contains a video signal register E _G 138, a video signal code processing unit 139 E _G , a first delay element block 140, an adder 141 and a second delay element block 142, a second key 143 and a second sound register block 144. The second path for receiving and processing video codes includes radio reception unit 145, a radio frequency amplifier 146, double pole amplitude detector 147, the first 148 and second 149 pulses conditioners, and two channels of video signal _EV. The first channel of the video signal E _B includes a first register 150 of the video signal E _B , a delay element block 151, a third key 152, and a third audio register block 153. The second channel of the video signal E _B includes a series-connected second register 154 of the video signal E _B , the first block 155 of the delay elements, the second block 156 of the elements of the delay and the adder 157, sequentially connected the fourth key 158 and the fourth block 159 of the sound registers. The control signal generating channel includes a serially connected horizontal sync pulse allocation unit 160, a frequency synthesizer 161 and a self-propelled pulse distributor 162, a key 163, a pulse counter 164 and a decoder 165 connected in series, and a frame sync selection block 166. The receiving side contains the first 167, second 168, third 169, fourth 170, fifth 171 and sixth 172 pulse amplifier units, a radiation modulation unit 173, a 2: 1 frequency divider 174, a horizontal scanning unit 175, a first amplifier 176, a first piezoelectric deflector 177 with a reflector at the end, the first source of positive reference voltage 178, the second source of negative reference voltage 179, the frame scan unit 180 from the element And 181, the master oscillator 182 and the summing amplifier 183, the second amplifier 184 and the second piezoelectric deflector 185 with a reflector at the end, t a positive reference voltage source 186, a fourth negative reference voltage source 187, an opaque screen 188. The receiving side includes two sound channels, each of which contains a series-connected DAC 189, a low-pass filter 190, a power amplifier 191 and a speaker 192.

The video signal processing unit E _R and the video signal processing unit E _G 13 are identical and each includes a trigger 193, first 194 and second 195 key blocks, first 196, second 197, third 198 and fourth 199 registers, first 200 , second 201, third 202, fourth 203, fifth 204 delay element blocks, each includes eight delay elements / by the number of bits /, adder 205 and the corresponding number of diodes / in this embodiment, 16 /. The information input of the block is the combined inputs of the blocks 194, 195 of the keys, the control input is the input of the trigger 193. The output of the block 132 is the combined outputs of the blocks 202, 203,204 of the delay elements.

 The operation of block 132/139 / is illustrated in Fig. 14.

 The horizontal sync pulse allocation unit 160 (Fig. 11/) includes the first 206, second 207, and third 208 pulse counters, the first 209, second 210, third 211 NOT elements, the first 212 and second 213 AND elements and a diode. The block inputs are the counting inputs of the pulse counters, the output is the output of the And 213 element. The block 166 for isolating the frame sync pulse / Fig. 12/ includes a pulse counter 214, an element NOT 215, an And 216 element, and a diode. The block inputs are the counting input of the counter 214 and the second input of the And 216 element. The output is the output of the And 216 element.

 The summing amplifiers 17 and 183 / FIG. 13/ are identical and each includes a pulse counter 217, a decoder 218, a first 219 and a second 220 keys, a first 221 and a second 222 pulse shapers and an output amplifier 223. The inputs are a counting input of a pulse counter 217 and a first input output amplifier 223, the output is the output of the output amplifier. The control input is the combined inputs of the second control input of the key 219, the first control input of the second key 220 and the control input of the pulse counter 217.

 The radiation modulation unit 173 (Fig. 15/) includes a first emitter 224 of three primary colors, a second emitter 225 of three primary colors and an optical system 226. The first emitter is located above the second. The radiating plane of the emitters is located in the rear focal plane of the optical system, in the front focal plane of which there is a reflector of the first piezoelectric deflector 177 / Fig. 9/. The radiating sides of the emitter 224, 225 through the optical system, the reflectors of the piezoelectric deflectors 177, 185 are optically connected to the matte screen 188. The inputs of the first emitter 224 are connected to the outputs of the pulse amplifier units 167, 168, 169, the inputs of the second emitter 225 are connected to the outputs of the blocks 170, 171, 172 pulse amplifiers.

The clock frequency in the system is:
500 _lines • 25 Hz • 700 _counts • 8 _bits. = 70 MHz
where 500 _lines • 25 Hz - line frequency 12.5 kHz,
700 - the number of encoded samples in the line of the transmitting side,
8 _bits - the number of bits in each code.

Photoelectric converter 1 generates three analog video signals supplied to the ADC inputs 29, 39, 31. Photoelectric converter 1 and three ADCs are structurally placed in a television transmitting camera, the output of which is three digital code of video signals Е _R , Е _G , Е _B. ADCs 29, 30, 31 convert analog video signals into 8-bit codes. Shapers 36, 37 codes of video signals convert parallel codes of video signals and sound into sequential ones and replace the representation of units from pulses with positive half-sine waves in codes E _R and odd codes E _B , and negative half-sine waves in codes E _G and even codes E _B monofrequency 70 MHz The master oscillator 34 generates sine waves with a stability of 10 ^-7 . A frequency synthesizer 35 generates from the frequency of the master oscillator 34 frequencies and issues: from the first output pulses 17.5 MHz to the clock input of the ADC 31 and to the control input of the second shaper 37 codes, from the second output pulses of 8.75 MHz to the clock inputs of the ADC 29, 30 , to the first control inputs of the ADC 32, 33, to the first control input of the first driver 36 and to the second control input of the second driver 37, from the third output pulses of 50 kHz to the second control inputs of the ADC 32, 33, from the fourth output sinusoidal oscillations of 70 MHz to the second control input first second shaper 36 and to the third control input of the second shaper 37, from the fifth output pulses of 12.5 kHz to the third control inputs of the ADC 32, 33, to the first input of the block 14 frame scan, to the third control input of the first shaper 36 codes and to the fourth control input second shaper 37 codes, from the sixth output pulses of 25 Hz to the second input of block 14 and to the input of the second self-propelled distributor of 39 pulses, from the seventh output pulses of 6.25 kHz to the input of block 7 horizontal scanning, from the eighth output sine wave carrier frequencies 630 MHz input to the transmitter 40.

The ADCs 32, 33 convert two audio signals into 16-bit codes, which come from the ADC 32 to the second information input of the first video signal code generator 36, and from the ADC 33 to the second information input of the second code generator 37. A self-propelled distributor of 38 pulses with the arrival of a start signal U _П from the third output of the second shaper 37 codes gives a code of eight units 11111111, which is a horizontal sync pulse code, to the fourth information input of the first shaper 36 codes and to the third information input of the second shaper 37 codes. The second self-propelled distributor of 39 pulses with the arrival of a starting U _P pulse of 25 Hz gives a code of eight units 11111111, which is a frame sync pulse code, to the fourth information input of the second shaper 37 codes. Block 7 from the master oscillator 8 and the output stage 9. The control voltage is triangular isosceles shape / Fig. 2 / s of block 7 is amplified in amplifier 6 and causes the piezoelectric deflector 3 to oscillate at a frequency of 6.25 kHz, line scanning is at a frequency of 12.5 kHz. The signal from the amplifier 6 is supplied to the internal electrode 78 / Fig. 5/, the voltage from the source 4 is applied to the external electrode 79, and the voltage from the source 5 is applied to the external electrode 80. When a control voltage is applied to the internal electrode, deformation occurs [3 p.122] piezoelectric plates: one lengthens, the second is shortened, a bending moment of forces arises, the end face with light reflector 82 rotates and deflects the vertical strip of the image, horizontal scan of the image. The image of the vertical strip enters the reflector of the second piezoelectric deflector 10, which produces a vertical scan of the image, performs a frame scan. The operation of the piezoelectric deflector 10 is the same as the piezoelectric deflectors 3, but it oscillates with a frequency of 25 Hz, or 50 fields per second. The width of the piezoelectric reflector 3 0.01 mm. The width of the reflector of the piezoelectric deflector 10 is also 0.01 mm, the length is 7 mm / 0.01 mm • 700 counts /. Both line and frame sweeps go without reverse moves (Fig. 2/) in terms of control voltages from amplifier 6 and 13. From the output of summing amplifier 17, a ramp voltage is amplified by amplifier 13. In the first half of the scan period, the piezoelectric reflector 10 deflects the image down, in the second half of the period / second field of the frame / there is a scan up. The summing amplifier 17 sums the triangular voltage from the master oscillator 16 with pulses of 12.5 kHz, which gives a linear step voltage for the amplifier 13. Each pulse of the line moves the line at the end of its stroke a step in the width of two lines at the time of the beam entry beyond the frame crane with one and the other. 500 lines per frame are received on the transmitting side. The output of the summing amplifier 17 produces a linearly varying step voltage. The purpose of the blocks 217-222 to submit / Fig.13/ to the second input of the amplifier 223 at the right time, positive or negative pulses of the corresponding amplitude and duration. Before the frame scan, _the zeroing signal U _about from the And element 15 resets the bits of the counter 217. The 9-bit counter 217 counts 12.5 kHz pulses, the count cycle is 500. At the end of the scan of the first field of the frame with the arrival of 250 pulses / 499 a line of odd lines / counter 217 normalizes the code 11111010, which is decoded by the decoder 218 into a signal that closes the first key 219 with a leading edge and opens the second key 220, which transmits 12.5 kHz pulses to the second pulse shaper 222, which provides positive pulses to the second input of the amplifier 223. It should be Vertkov second field of the frame / up /. With the arrival of the leading edge of the next frame pulse to the input of AND element 15, the counter 217 is reset to zero, followed by a downward scan / first field of the frame /. Colored rays reflected from the reflector of the piezoelectric deflectors 10: red is reflected from the first dichroic mirror 18 and is collected by a micro-lens 20 into a photodetector 23, blue color passes through a first dichroic mirror 18, reflected from a second dichroic mirror 18 and collected by a micro-lens 22 is collected into a photodetector 25, both mirrors pass through and green with a micro lens 21, it is assembled into a photodetector 24. From the photodetectors, analog video signals are fed to their preamplifiers 26, 27, 28.

The ADCs 29, 30, 31 have one conversion principle, which consists in scanning the beam (Fig. 3) from the LED 51 by the reflector of the piezoelectric deflector 47 along the plane of the entrance pupils of the optical fibers of the quantizing line 54. The light pulse is converted by the photodetector in block 55 into an electrical signal that excites one of the input bus encoder 56, which gives the code instant value of the input video signal. The conversion frequency in the ADC is 29, 30 8.75 MHz, in the ADC 31 - 17.5 MHz The slotted aperture 52 and the micro-lens 53 form a beam with an aperture equal to the size of one input window of the optical fiber of the quantizing array of 54 optical fibers of 0.02 mm. The radiation source was a pulsed LED AL402A with a pulse rise time of 25 ns, which with a margin satisfies a sampling rate of 17.5 MHz / 57.14 ns /. Quantizer line 54 includes 255 optical fibers for encoding video signals with an 8-bit code 2 ⁸ . Photodetectors are LFD avalanche photodiodes with a response time of 10 ns, made by microelectronic technology at the output ends of the optical fibers. The inputs of each photodetector are connected to the corresponding inputs of the encoder 58, which represents the K155IV1 microcircuit (4 p.231) with a response time of 20 ns. The encoder generates codes from 00000001 to 11111111. The first fiber corresponds to the code 00000001, the second to 00000010, the third to 00000011, etc. 255-у - 11111111. The conversion time consists of the response time of the photodiode 10 ns plus the response of the encoder 20 ns, in the amount of 30 ns or 33 • 10 ⁶ prev / s, with a margin satisfying sampling of 17.5 MHz / 57.14 ns /. Codes with the ADC 29, 30 enter the shaper 36 codes with a frequency of 8.75 MHz, codes with the ADC 31 enter the second shaper 37 with a frequency of 17.5 MHz.

 Information creation speed of the ADC is 29, 30 at 70 Mbit / s, the ADC is 31 140 Mbit / s: 17.5 MHz • 8 times /.

The ADCs 32, 33 convert two audio signals into 16-bit codes. During one line, each ADC generates four codes, the sampling frequency is 50 kHz / 12.5 kHz • 4 /. The sampling pulses arrive as signals to the radiation of the LED 65 / Fig. 4/. A quantizing line of 68 optical fibers contains 1024 optical fibers, converts the audio signal into a 10-bit code 2. The resolution is 10 μV, the coding range of the ruler is 0-0.01024 V. Conversion to a code of signals exceeding 2 ¹⁰ is performed by a decoder 70 , a second decoder 72, a voltage divider 57 and a key block 58. With their use, the coding range is 0-0.65536 V, i.e. 2 ¹⁶ . During one line, the encoder 71 issues four codes that enter the block 75 registers containing four 16-bit register. In the process of receipt, the codes are shifted from register to register by pulses U _sd . Then the codes are issued one after another to the generator 36/37 / codes at the moments of discrete pulses 696, 697, 698, 699 / Fig. 8/. The output signals are normalized by a counter of pulses 73 and a decoder 74. A 10-bit counter counts pulses of 8.75 MHz, a cycle of counting 700 pulses, is reset by the leading edge of the pulse of the frequency of the lines 12.5 kHz at the time of the 700th pulse of the line.

The first generator 36 codes of video signals generates codes of video signals E _R and E _{G /} Fig. 6/ from 1 to 695, four codes of the first audio signal 696, 697, 698, 699 and 700 are a horizontal sync pulse code, a total of 700 pairs of codes. The second generator 37 of the codes of the video signals generates the codes of the video signal E _{B /} Fig. 7/ from 1 to 1390, four audio codes from 1391/1392 to 1397/1398, the horizontal sync code 1399 and the frame sync code 1400 / Fig. 8/. A total of 1400 codes.

 The operation of the shaper 36 codes of video signals / 6 /.

Codes from the encoder 56 of the ADC 29 / Е _R / arrive at a frequency of 8.75 MHz at the first information input - the first inputs of a block of 83 elements and in parallel. Codes from the encoder 56 ADC 30 / Е _G / arrive at a frequency of 8.75 MHz to the second information input - the first inputs of the block of 88 elements And in parallel. The second inputs of both blocks of elements And receive pulses from their self-propelled pulse distributors 87, 92, which have eight discharges and are made according to the scheme (5 p. 274). From the outputs of the AND elements, the pulses of the codes come sequentially to the first / third /, then to the second / fourth / OR elements. From the OR element 85, 90, the pulses open their output switch 86, 91 for a duration of 14.28 ns. The output switch 86 in the open state transmits one positive half-cycle of the mono-frequency sinusoid 70 MHz, the output switch 91 in the open state transmits one negative half-cycle of the sinusoid 70 MHz At the input driver 36 in units of codes presented pulses, and the output unit in the codes E _R represented by positive half-sine, units E _G codes are represented by negative half-sine pulse. Zeros appear to be the absence of both. Timing diagrams of the operation of the shaper 26/37 / in Fig.16. The outputs of the output keys 86, 91 are combined and are the output of the driver 36. The output signal is represented by full and incomplete sinusoids of the 70 MHz monofrequency with a stability of 10 ^-7 , which are modulating signals for the carrier frequency in the first amplitude modulator 42/1 /. The time 695 counts is used to switch the keys 99, 100. The sound code is divided into two packages of 8 bits: the first half of the code from 1 to 8 bits through blocks of 93 AND elements, 94 OR elements goes to the second input of the second OR 85 element and goes to the control the input of the first output key 86, the second half of the sound code from 9 to 16 bits through blocks 96, 97 goes to the second input of the fourth element OR 90, from it to the control input of the second output key 91. In the sound codes from 1 to 8 bits of the unit appear to be positive sine, 9 to 18 discharges with negative sine waves. Keys 99, 100 are designed to separate audio codes from video signal codes. The key 99 is opened U signal _from the first output of decoder 102 at the time of resetting the counter 101 / 700th count / and remains open on the 694 count, at time 695 the reference signal U _of CO second output of decoder switch 99 is closed, opens the second switch 100, which closes with a signal U _s from the first output of the decoder 102. The counting cycle of the counter 101 700 pulses. The SSI code forms a self-propelled dispenser 38, it arrives at the third inputs of the second 85 and fourth 90 OR elements, from the output of the key 86 units of the SSI code are represented as positive sine waves, from the output of the key 91 units of the SSI appear as negative sine waves.

The operation of the shaper 37 codes of the video signal E _{In /} Fig.7/.

The video signal codes E _B from the encoder 56 of the ADC 31 are supplied with a frequency of 17.5 MHz to the first information input - the inputs of the switching unit 104 in parallel. From the outputs of block 104, the codes in parallel form are alternately fed to the first inputs of the elements AND of blocks 105, 110. Next, the operation of the driver 37 is similar to the operation of the driver 36 codes. The second information input is the first inputs of blocks 115, 118 elements I. The switching unit is designed to split the 17.5 MHz stream into two at 8.75 MHz. The outputs of the switching unit 104 to the units 105, 110 are connected in turn by control signals from the trigger 103. The decoder 124 has a third output that provides a control pulse U _P for starting the first self-propelled distributor of 38 pulses at the moment 699 of the line sampling pulse so that the clock sync pulses go from the output shaper 37 codes at the time of the 700th count of the line. The SSI code is supplied to the third information input of the shaper 37 — to the third input of the second OR element 107. The frame sync pulse goes to the fourth information input of the shaper 37 — to the third input of the fourth OR element 112. Sound codes 1 through 8 of the bits go to the second input of the OR element 107, the sound codes from 9 to 16 bits are fed to the second input of the OR element 112. The output signal from the driver 37 represents the full and incomplete sinusoids of the frequency of 70 MHz and is a modulating signal carrier frequency in the amplitude modulator 44. Carrier The 630 MHz frequency synthesizer from the frequency synthesizer 35 enters the transmitter at the input of the carrier frequency amplifier 41, from the output of which it goes in parallel to the first input of the amplitude modulator 42 and to the first input of the amplitude modulator 44. In the first amplitude modulator 42, the carrier frequency is suppressed and the lower side frequency 560 MHz / 630-70 /. In the second amplitude modulator 44, the carrier frequency is suppressed and the upper side frequency of 700 MHz / 630 + 70 / is filtered out. As a result, a modulated upper side frequency of 700 MHz is emitted from block 43 to the air, occupying a stability band of ± 70 Hz or 140 Hz when the master oscillator 34 is 10 ^-7 , and a modulated lower side frequency of 560 MHz, occupying the ± band, is emitted from block 45 56 Hz or 112 Hz. In total, the occupied band is 252 Hz. Compared to the analog 8 MHz band, 252 Hz television is 0.003%.

Two radio signals are received by blocks 126, 145 receiving radio signals, which are selectors decimeter range / ACS / with electronic tuning and perform radio signal reception in the range 560-790 MHz. Each represents the first half of SKD-24 [6 p.132] and includes an input circuit, a radio frequency amplifier, and a mixer / on a VT2 transistor is used from the frequency converter [6 fig.4.21]. The band-pass filter of the radio frequency amplifier in each range is tuned by applying bias voltage to the varicaps from the electronic switch of the touch control unit 125, which is the program selection unit, for example, USU-1-15 [6 p. 86]. The amplified radio frequency signal through the communication loop L11 [6 p.132] is fed to the mixer emitter / transistor VT2 /, the corresponding frequency necessary for detecting a single-band signal [7 p.146], which carries this program, is supplied to the mixer emitter from the frequency synthesizer 161. The local oscillator circuit and the IF filter, available in SKD-24 [6 Fig. 4.2], are not needed. The signal from the VT2 collector, which is the output signal of block 126/145 /, is fed to the input of the amplifier 127/146 / radio frequency, where it is amplified to the required value and fed to the input of the bipolar amplitude detector 128/147 /. The second inputs of the synthesizer 161 frequencies are connected to the second group of outputs of the block 125 / after the diodes VD11-VD18 [6 p. 86] /. When the program guide is switched on, the voltage from the corresponding diode determines the output of the carrier frequency from the frequency synthesizer 161 to the third inputs of blocks 126, 145. Sine waves of another carrier frequency, respectively, to the carrier frequency transmitting side transmitter. Bipolar amplitude detectors 128, 147 are made according to the scheme [8 p.112] / Fig. 10/. Diode D1 selects the positive envelope of the modulating sinusoidal signal. The diode D2 from the modulating isolates the envelopes of the positive half-sinusoid / symbols of units of codes E _R /, the diode D3 from the modulating emits the envelopes of the negative half-sinusoids / symbols of units of the units E _G /. From the first output of the bipolar amplitude detector 128/147 /, the detected positive half-sine waves with a frequency of 70 MHz are fed to the input of the shaper 129/148 / pulses. The detected negative half-sinusoids of 70 MHz from the second output of the detector are fed to the input of the second driver 130/149 / pulses. The pulse shapers are made according to the scheme of an asymmetric trigger with emitter coupling [9 p.209], forming rectangular pulses from harmonically changing signals. The pulses from the formers have one polarity and a duration equal to the pulse duration in the codes on the transmitting side. Units in codes are represented by the presence of an impulse, zeros by their absence. After turning on the power, the keys of the receiving side are in the closed state. The operating procedure of the receiving side is determined by control signals that are generated by the channel for generating control signals. The decisive role belongs to the block 160 allocation horizontal line clock. The condition for issuing the SSI is the simultaneous arrival from three formers 129, 130, 148 pulses of codes of eight units 11111111 to the inputs of block 160. In all codes of the line, except for the 700th, one or more zeros will almost always be present, especially in the codes of three lines according to which the elements are NOT / Fig. 11 / reset the counters of block 160. With the arrival of three codes 11111111, block 160 gives out a pulse, which is a 12.5 kHz SSI pulse. The SSI opens the key 163, is fed to the first input of the frame scan block 180, to the second input of the frame sync pulse allocation block 166 and is a frequency synchronization pulse in the frequency synthesizer 161. Own frequency stability of the synthesizer 161 frequencies 10 ^-6 . Fine tuning of the frequency of the synthesizer 161 for the frequency and phase of the master oscillator 34 in the transmitting side is performed on the leading edge of the SSI from block 160, which is fed to the first input of the frequency synthesizer 161. A frequency synthesizer 161 generates 8.75 MHz sampling pulses from the first output, 50 kHz sampling pulses of the sound signal from the second output, generates sinusoidal oscillations of the required carrier frequency from the third output, and 17.5 MHz sampling pulses from the fourth output. The 8.75 MHz pulses for the self-propelled distributor of 162 pulses are trigger U _P signals. The self-propelled distributor 162 generates a clock frequency of 70 MHz, multiplying 8.75 MHz by 8. The video signal codes E _R from the output of the pulse shaper 129 are received in serial form at the input of the video signal register 131 E _R , filling in the bits of which the code acquires a parallel form, and in parallel form is issued by 8.75 MHz sampling pulses to the inputs of the video signal processing unit E _R 132. Block 132/139 / produces intermediate / middle / codes between each transmitted code and each subsequent one to double the repetition rate of codes E _R / E _G / s from 8.75 MHz to 17.5 MHz. Block 132/139 / performs the addition of two codes / previous and subsequent / and dividing the amount in half. From the output of block 132/139 / codes E _R / Е _G / follow with a frequency of 17.5 MHz to block 167 pulse amplifiers, to the first inputs of adder 134 and to the inputs of block 133 of delay elements. Block 133 delays each code for a line duration of 80 μs. At the first inputs of adder 134, the code of the current line from block 132 is received, the same code comes to the second inputs after delaying it by 80 μs by block 133, i.e., the last line. The adder 134 adds these codes, and the sum is divided in half by the corresponding connection of the outputs of the adder 134 and the inputs of the pulse amplifier unit 170. The resulting code is an intermediate line code between the past and current lines. Thus, the adder 134/141 / doubles the lines of the video signal E _R / E _G /.

From the output of the second pulse shaper 130, the codes E _G are sequentially fed into the register 138 of the video signal E _G , which converts the codes into parallel. The further process of processing the E _G codes is similar to the process in the video signal channel E _R. At the inputs of block 168, codes E _{G of the} current line encoded in the transmitting side are received, at the inputs of block 171 of pulse amplifiers, intermediate line codes generated by adder 141 are received. The signals from blocks 167, 168 are fed to the inputs of the first emitter 224 of three primary colors in block 173 / FIG. 15 /, the beam of which reproduces 500 lines encoded on the transmitting side. The signals from the pulse amplifier units 170, 171 are fed to the inputs of the second emitter 225 in the radiation modulation unit 173, the beam of which reproduces 500 intermediate lines.

 The operation of the block 132/139 / code processing / Fig.14/.

Разряд 0 означает разряд переноса при сумме кодов. Процесс получения промежуточных кодов на фиг.14. При удвоении частоты следования кодов до 17,5 МГц период следования их составляет 57,14 нс. Сложение занимает 24 нс, следовательно, блок 204 элементов задержек должен задерживать код еще на 33,14 нс. По истечении 57,14 нс код 1

поступает с блока 204 на выход блока 132. Следующий код 2 поступает с блока 203 через 57,14 нс. Это код "0", который был выдан с регистра 198 в блок 203. Блок 203 задерживает код на 114,28 нс, но первая половина задержки в 57,14 нс приходится на время сложения плюс время задержки кода в блоке 204. Поэтому код 2 из блока 203 выходит вслед за кодом 1 через 57,14 нс. С приходом 2-го импульса на вход триггера 193 со второго его выхода сигнал U_выд2 выдает из регистра 196 первый код "1 код" через диоды в сумматор 205 и в блок 202 элементов задержек, задерживающий код на 114,28 нс. Сигнал U_выд2 выдает из регистра 199 код "0" в сумматор 205. Идет сложение, деление суммы пополам. Через 10 нс вслед за выдачей кода из регистра 199 регистры 198, 199 заполняются вторым кодом с блока 195 ключей. Через 57,14 не после кода 2 с блока 204 на выход следует код 3

еще через 57,14 нс с блока 202 следует код 4 "1 код". С приходом 3-го импульса в триггер 193 сигнал U_выд3 выдает из регистра 197 первый код "1 код" в сумматор 205 и "2 код" из регистра 198 в сумматор и в блок 203. Следует заполнение третьим кодом регистров 196, 197. Идет сложение и деление пополам. С выхода блока 204 выходит код 5

через 57,14 нс следует с блока 203 код 6 "2 код". С приходом 4-го импульса в триггер 193 с него следует сигнал U_выд4, он выдает код "3 код" из регистра 196 и "2 код" из регистра 199. Следует заполнение четвертым кодом регистров 189, 199, сложение в сумматоре 205, на выходе блока 204 появляется код 7

, через 57,14 нс с блока 202 следует код 8 "3 код". Далее эти процессы, чередуясь, повторяются, пока включена приемная сторона. Сумматоры 134, 141 идентичны, представляют собой микросхемы К555ИМ6, производят сложение кодов одних и тех же отсчетов предыдущей и последующей строк, деление пополам выполняется как уже описано: соответствующее подключение выходов сумматора 134 /141/ и входов блока 170 /171/ импульсных усилителей. В связи с тем, что сумматоры задерживают коды при сложении на 24 нс, перед блоками 167, 168, 169 включены блоки 135, 142, 151 элементов задержек, они выполняют задержку кодов на 24 нс. В этом случае коды в блоки 167, 168, 170, 171 приходят синхронно.Block 132/139 / receives intermediate codes from each previous and subsequent codes from the transmitting side, which doubles their repetition rate from 8.75 MHz to 17.5 MHz. Since each code is used twice: once as the previous, second time as the next, block 132/139 / has four registers 196, 197, 198, 199. With the arrival of the 1st pulse of 8.75 MHz on the trigger 193 pulse U _vyd1 from the first trigger output, it simultaneously outputs the code "0" from register 197 and the code "0" from register 198 and resets them. The code from register 197 goes to the first inputs of adder 205, the code from register 198 goes through diodes to the second inputs of adder 205 and to the inputs of block 203 of delay elements, which has 8 delay elements, which delays the code by 114.28 ns. From register 131, the first code in parallel is fed to the inputs of the first 194 and second 195 key blocks. The signal U _vyd1 opens the keys in block 194, containing eight keys by the number of bits. The code from block 194 passes through a block of delay elements 200, which delays the code by 10 ns for timing the arrival of the code in the registers 196, 197 after issuing the code from them, and the first code enters the registers 196, 197. The adder 205 performs the addition of the codes, and the amount is divided in half. The K555IM6 microcircuit [4 p. 258] with an addition time of 24 ns was used as an adder. The code is divided in half by shifting the sum code by one bit so that the least significant bit of the sum code is discarded. A shift by one bit is performed by the corresponding connection of the outputs of the adder 205 to the inputs of the block 204 delay elements:

Bit 0 means carry bit when the sum of the codes. The process of obtaining intermediate codes in Fig.14. When doubling the repetition rate of codes to 17.5 MHz, the repetition period is 57.14 ns. Addition takes 24 ns, therefore, the delay element block 204 must delay the code by another 33.14 ns. After 57.14 ns, code 1

comes from block 204 to the output of block 132. The next code 2 comes from block 203 through 57.14 ns. This is the code "0", which was issued from register 198 to block 203. Block 203 delays the code by 114.28 ns, but the first half of the delay of 57.14 ns is the addition time plus the code delay time in block 204. Therefore, code 2 leaves block 203 after code 1 after 57.14 ns. With the arrival of the second pulse to the input of the trigger 193 from its second output, the signal U _vy2 generates from the register 196 the first code "1 code" through the diodes to the adder 205 and to the delay element block 202, delaying the code by 114.28 ns. The signal U _vyd2 generates from the register 199 the code "0" in the adder 205. There is an addition, division of the amount in half. After 10 ns, after issuing the code from register 199, registers 198, 199 are filled with the second code from key block 195. After 57.14, not after code 2 from block 204, code 3 follows the output

after another 57.14 ns from block 202, code 4 "1 code" follows. With the arrival of the third pulse in the trigger 193, the signal U _vyd3 generates from the register 197 the first code “1 code” to the adder 205 and “2 code” from the register 198 to the adder and to block 203. The third code of registers 196, 197 should be filled in. There is addition and halving. From the output of block 204, code 5

after 57.14 ns, code 6 "2 code" follows from block 203. With the arrival of the 4th pulse in the trigger 193, it follows a signal U _vy4 , it gives the code "3 code" from register 196 and "2 code" from register 199. The fourth code of registers 189, 199 should be filled, addition in adder 205, by the output of block 204 appears code 7

, after 57.14 ns from block 202, code 8 "3 code" follows. Further, these processes, alternating, are repeated while the receiving side is turned on. Adders 134, 141 are identical, are K555IM6 microcircuits, add codes of the same samples of the previous and next lines, divide in half as described above: the corresponding connection of the outputs of the adder 134/141 / and the inputs of the block 170/171 / of pulse amplifiers. Due to the fact that the adders delay the codes when added by 24 ns, blocks 135, 142, 151 of the delay elements are included in front of blocks 167, 168, 169, they delay the codes by 24 ns. In this case, the codes in blocks 167, 168, 170, 171 arrive synchronously.

The operation of the video signal channels E _{B /} Fig. 9/.

Codes from shaper 148 enter the first register 150 of the first channel of the video signal Е _В , from the output of register 150, the codes are sent in parallel to the input of the delay element block 156, to the first inputs of the adder 157, and through the delay element block 151 to the inputs of the pulse amplifier unit 169. Codes from the pulse shaper 149 are received in the second register 154 of the video signal Е _в , with it in parallel form through the first 155 and second 156 blocks of delay elements to the second inputs of the adder 157. The adder 157 is designed to obtain codes of intermediate lines by adding the codes of the same samples of the previous samples and the subsequent lines of the raster with dividing the amount in half. Codes of intermediate lines are received in block 172 pulse amplifiers. The adder is a chip K555IM6. The signals from the block 169 pulse amplifiers are fed to the inputs of the first emitter 224, the beam of which reproduces 500 lines of image encoded on the transmitting side. The signals from block 172 are fed to the inputs of the second emitter 225, the beam of which reproduces intermediate lines of the image obtained by the adder 157. The blocks of pulse amplifiers are represented by 533AP6 microcircuits with a response time of 18 ns [4 p.128].

Block 173 radiation modulation performs luminance modulation of three colors R, G, In two lines simultaneously, respectively, the values of the codes of the video signals E _R , E _G , E _B. The first emitter 224 modulated in brightness beam reproduces the image of 500 lines encoded on the transmitting side and transmitted to the receiving side. The second emitter 225, with a brightness-modulated beam, reproduces an image of 500 intermediate lines, the sample codes of which are obtained by adders 134, 141, 157. The reproducing raster contains 1000 active lines with 1400 samples in a line, which defines 1400000 resolution elements in a frame. The key 163 is opened by the SSI, the counter 164 pulses 10-bit produces a discrete pulse count of 8.75 MHz, the counting cycle is 700 pulses. With the arrival of the 694th pulse, the decoder 165 decrypts the binary code of the 694th pulse and generates a signal U _{from the} first output, opening the keys 136, 143, 152, 158, passing four sound codes during 696, 697, 698, 699 discrete pulses. The duration of the 695 impulse is to open the keys. Sound codes enter blocks of sound registers 137, 144, 153, 159, each of which contains four 8-bit registers. The registers are filled in as codes arrive, and issued by signals U _vy 50 kHz from the second output of the frequency synthesizer 161 in the DAC 189, which convert the codes into analog audio signals. Analog audio signals pass filter 190 low-frequency, amplified in power amplifier 191 and reproduced loudspeakers 192. With the advent of the counter 163 699-th pulse decoder 165 from the second output signal U _of closing keys 136, 143, 152, 158, 164, and resets the counter closes the key 163. The codes of sound signals enter the channels of video signals, but starting from 1391 line counts / Fig. 8/, the rays reproducing the image are already beyond the edge of the screen frame. The emitters 224, 225 include each LED red radiation 12 pcs., Green radiation 12 pcs., Blue - 12 pcs. type HLMP- manufactured by the Hewlett-Packard company [10 p.71]. The emitting windows of the LEDs are located in the rear focal plane of the optical system 226. The distribution of LEDs of the same color according to the discharge weights in the table. 2.

 The total emission of the three-color LEDs in the emitter is mixed by the optical system 226 when focusing in two color spots on the reflector of the first piezoelectric deflector 177. For red radiation, HLMP-AL00 LEDs with a light intensity of 400 mcd [10 p. 71] at a current of 0.02 A are accepted. For HLMP-AM00 LEDs with a light intensity of 800 μd with a wavelength of 0.526 μm and a current of 0.02 A are accepted for blue radiation. HLMP-AB00 LEDs with a light intensity of 300 μd with a wavelength of 0.475 μm and a current of 0.02 A are accepted.

где в числителе суммарная сила света от одного излучателя, принято, что красный, зеленый и синий светодиоды имеют силу света синего светодиода /300 мкд/,
1/2-1/32 - коэффициенты двоичного кода в 4;5,6,7,8 разрядах,
0,5•10^-6 м² - площадь разрешающего элемента на экране.Brightness modulation is performed by switching on the radiation of the number of LEDs according to the discharge weight according to Table 2. The brightness, saturation and hue of the resulting color on the screen is determined by the total energy and the mutual ratio of the three colors R, G, B in each emitter. The resolving element on the screen in the line is 0.5 mm ² / 0.7 • 0.7 mm /. The maximum brightness of the resolving element at the time of radiation on the screen without taking into account projection losses is

where in the numerator the total light intensity from one emitter, it is assumed that the red, green and blue LEDs have a blue light intensity / 300 mcd /,
1 / 2-1 / 32 - binary code coefficients in 4; 5,6,7,8 bits,
0,5 • 10 ^-6 m ² - the area of the resolving element on the screen.

The light intensity adjustment of red / 400 mcd / and green / 800 mcd / LEDs with blue / 300 mcd / is performed by attenuating filters / the number of LEDs is also possible /. The maximum brightness of the screen element permitting taking into account losses in the projection to the screen 50% is 7,171,875 cd / ^m2, which is sufficient to create a bright color image on the screen observed by the viewer. And since the scan is carried out simultaneously by two resolving elements of two lines, the total brightness will be twice as high. The piezoelectric deflector 177 according to the control voltage of the amplifier 176 performs a horizontal scan of two beams on the reflector of the second piezoelectric deflector 185, performing a vertical scan along with the horizontal on the screen 188. The LEDs of one emitter consume: 35 pcs • / 5 V • 0.02 A / = 3.6 VA .

 Two emitters consume 7.2 VA. The piezoelectric deflectors are controlled by control voltages from the horizontal scanning unit 175 and the vertical scanning unit 180. Horizontal scan voltage has a triangular isosceles shape with a frequency of 6.25 kHz. Amplifier 176 amplifies the voltage and drives the piezoelectric deflector 177 with a line frequency of 12.5 kHz. The piezoelectric deflector 185 oscillates at a frequency of 25 Hz. The summing amplifier 183 is identical to the transmitting side amplifier 17. The width of the reflective strip of the piezoelectric deflector 185 0.04 mm, length 28 mm: 0.02 mm • 1400. The beginning of the frame scan is determined by the coincidence of the leading edges of the horizontal and vertical sync pulses at the input of the And 181 element. The summing amplifier 183 produces a stepwise linearly increasing voltage (Fig. 2/) for one field of the frame and a stepwise linearly decreasing voltage for another field of the frame. The condition for the block 166 to issue a frame sync pulse / CSI / is the simultaneous arrival at the first input / Fig. 12/ of the code 11111111 from the output of the pulse shaper 149 and to its second SSI pulse input from the SSI block 160.

 System operation.

 From the photodetectors 23, 24, 25, three analog video signals after amplification by preliminary amplifiers are fed to the ADC inputs 29, 30, 31. Two sound signals are fed to the ADC inputs 32, 33.

Video signals E _R , E _{G are} converted to 8-bit codes with a sampling of 8.75 MHz, video signals E _{B are} converted to 8-bit codes with a sampling of 17.5 MHz. Sound signals are converted to 16-bit codes with sampling of 50 kHz. Shapers of codes 36, 37 of the video signals form sequential codes from parallel codes and replace the representation of units from pulses with half-sinusoids of the single frequency of 70 MHz in them. The clock frequency in the system is 70 MHz. The information transfer rate is 280 Mbps. On the transmitting side, video signals of 500 lines of a raster are encoded, video signals E _R and E _G of 700 samples per line, video signal E _B of 1400 samples per line. Information of codes E _R and E _G is transmitted by the upper side frequency of the carrier of 700 MHz, codes E _B is transmitted by the lower side frequency of 560 MHz of the same carrier. The occupied frequency band is 252 Hz. The receiving side receives two radio signals, amplifies the radio frequency, bipolar amplitude detection, extracts the SSI, CSI, in the channels of the video signals E _R , E _G doubles the frequency of the repetition codes of the line samples and the number of lines twice, respectively 17.5 MHz and 1000 lines, in the channels of the video signal Е _В doubled the number of lines 1000 twice. The modulation block 173, respectively, of the two-line codes emits LEDs from the emitters 224, 225, the color image is piezoelectric deflectors 177, 185 are scanned in two lines on matte screen 188. The volume of reproduced information 840 Mbit / s: 280 Mbit / s • 3.

 The technical and economic effect of the claimed system relative to the prototype is to increase the amount of information generation while reducing the energy consumption of the system and increasing the resolution of the reproduced image. The system can be used for digital television broadcasting in the DTV range for analogue television over existing terrestrial TV networks.

Positive effects of using the inventive system:
- a small occupied frequency band of 252 Hz solves the problem of the distribution of the frequency resource,
- low power consumption: with a bandwidth of 252 Hz, less transmitter power is needed for radiation than with a band of several MHz,
- high noise immunity: the interference spectrum is wide, and the fraction of the interference energy will fall to the share of 252 Hz,
- increased electromagnetic compatibility: a narrow band makes it possible to spread frequencies well,
- low voltage of the receiving part: the value of the supply voltage is determined by the supply voltage of the microcircuits and LEDs, creates a condition for the safe operation of the receiver,
- lack of harmful radiation from the screen,
- the ability to use existing terrestrial TV networks in the range of 500-790 MHz, 31-60 channels of analogue TV.

Sources of information
1. Patent 2,128,890 C. H 04 N 11/04 bull. 10 for 1999, prototype.

 2. Radio transmitting devices, MS Shumilin et al., M., 1981, p. 234.

 3. Fridland I.V., Soshnikov V.G. "Automatic control systems in video recording devices", Moscow, 1988, p.118 fig.5.5, p.122 fig.5.10.

 4. Digital integrated circuits, Minsk, 1991, S. 128, 231, 258.

 5. Ilyin V.A. "Remote control and telemetry", M., 1982, S. 274.

 6. Brodsky M. A. "TVs of color image", Minsk, 1988, p. 86 fig. 2.55, p. 132 fig. 4.2.

 7. Radio communications, broadcasting, television, ed. HELL. Fortushenko, M., 1981, p. 146.

 8. Handbook of Broadcasting, ed. A.V. Vyhodtsa, Kiev, 1981, c.1l2 fig. 81.

 9. Barkan V.F., Zhdanov V.K. "Amplification and pulse technology", M., 1981, p.209.

 10. Radio 7, 1998, p. 71.

Claims (1)

A high-definition digital television system containing a transmitting side, which includes a photoelectric converter, first, second, third analog-to-digital converters (ADCs), the inputs of which are connected to the corresponding outputs of the photoelectric converter, the fourth and fifth ADCs, the information inputs of which are accompanied by sound signals connected in series to a sine wave generator and a frequency synthesizer, first and second video signal shapers, and a radio signal transmitter containing two channels, the first channel includes a serially connected carrier frequency amplifier, a first amplitude modulator and an output amplifier, the second channel includes a second amplitude modulator and an output amplifier connected in series, the first output of the frequency synthesizer is connected to the clock input of the third ADC and to the first control input of the second driver video signal codes, the second output is connected to the clock inputs of the first, second ADCs, to the first control inputs of the fourth and fifth ADCs, to the first control at the input of the first video signal encoder and to the second control input of the second video signal encoder, the third output is connected to the second control inputs of the fourth and fifth ADCs, the fourth output is connected to the second control input of the first video signal encoder and to the third control input of the second video signal encoder, fifth the output is connected to the third control input of the first video code generator, the fourth control input of the second video code generator ignals and to the third control inputs of the fourth and fifth ADCs, the eighth output is connected to the input of the radio signal transmitter, the first and second information inputs of the first video signal shaper are connected respectively to the output of the first ADC and the fourth ADC output, the first and second information inputs of the second video signal shaper respectively, to the output of the third ADC and to the output of the fifth ADC, the photoelectric converter contains a lens, a first piezoelectric deflector with a reflector at the end, a second piezo a deflector with a reflector at the end, optically connected to the reflector of the first piezoelectric deflector, a horizontal scanning unit from the master oscillator and the output stage, the first amplifier, the input of which is connected to the output of the horizontal scanning unit, and the output is connected to the first input of the first piezoelectric deflector, the first source of positive reference voltage, the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the first of the first amplifier and the first piezoelectric deflector, a frame scan unit and a second amplifier, the output of which is connected to the first input of the second piezoelectric deflector, a third source of positive reference voltage, the output of which is connected to the second inputs of the second amplifier and second piezoelectric deflector, the fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector, the first and second inputs of the frame scanning unit are connected to the fifth and sixth outputs of the frequency synthesizer, input A horizontal scanning unit is connected to the seventh output of the frequency synthesizer, the photoelectric converter contains the first and second dichroic mirrors, the first, second, third micro lenses, the first, second, third photodetectors, the first, second, third pre-amplifiers, the outputs of which are the outputs of the photoelectric converter, controlling the inputs of the photoelectric converter are the output of the vertical scanning unit and the output of the horizontal scanning unit, the vertical scanning unit includes an AND element defining a herator and a summing amplifier containing a pulse counter and a decoder connected in series, the first and second keys, the first and second pulse shapers and the output amplifier, the first, second, and third ADCs are identical and each contains a video amplifier and a piezoelectric deflector with a reflector at the end, a positive reference source voltage source of negative reference voltage, the emitter, including a pulsed LED, aperture diaphragm and a micro lens, contains a quantizing line of optical fiber c, the inputs of which are optically connected to the piezoelectric reflector, a series of photodetectors and an encoder, the outputs of which are the outputs of the ADC, and the input is the input of the video amplifier, the fourth and fifth ADCs are identical and each contains a voltage divider, a key block, a matching amplifier, an amplifier, and a piezoelectric deflector with reflector at the end, the source of the positive reference voltage, the source of the negative reference voltage, the emitter of a pulsed LED, a slit diaphragm and a micro lens includes the trailing light guide line, the photodetector block, the first decoder, the encoder and the second decoder and contains a pulse counter, the third decoder and the register block, the first video signal encoder includes three channels, the inputs of which are inputs of the first video signal encoder, and the outputs are combined, the first and second channels identical, the first channel contains a series-connected block of AND elements, the first and second OR elements and the first output key, and the first self-propelled pulse distributor of the first channel, in the second inputs of the And block of elements are connected to the outputs of the self-propelled pulse distributor of the first channel, the second channel contains series-connected block of And elements, the third and fourth OR elements and the second output key, and the second self-propelled pulse distributor of the second channel, the second inputs of the block of And elements are connected to the outputs of the second self-propelled pulse distributor of the second channel, the first inputs of the block of elements And the first channel are the first information input of the first driver of the codes of video signals, the first the moves of the block of elements And of the second channel are the second information input of the first driver of the codes of video signals, the outputs of the first and second output keys are combined and are the output of the first driver of codes of the video signals, the third channel includes the first and second blocks of elements of And, the inputs of which are the third information input, the fifth and sixth OR elements, the output of the fifth OR element is connected to the second input of the second OR element, the output of the sixth OR element is connected to the second input of the fourth OR element, and the first and second oh self-propelled pulse distributors, the outputs of which are connected respectively to the second inputs of the first and second blocks of AND elements, the first encoder of the video signals includes the first and second keys, a pulse counter and a decoder, the first output of which is connected to the first control input of the first key and the second control input of the second key , the second output is connected to the second control input of the first key and the first control input of the second key, the first control input of the first video code generator c is the combined input of the first and second keys and the counting input of the pulse counter, the second control input of the first shaper of video signals is the combined input of the signal inputs of the first and second output keys, the third control input of the first shaper of video signals is the control input of the pulse counter, the second shaper of video signals contains a trigger and a switching unit connected in series, the inputs of which are the first information input of the second driver video signals, and three channels, the first and second channels are identical, the first channel contains a block of AND elements connected in series, the first and second OR elements and an output switch, and a self-propelled pulse distributor, the second channel contains a block of AND elements, a third and fourth OR connected in series and the output key, and a self-propelled pulse distributor, the first inputs of the And blocks are connected to the corresponding outputs of the switching unit, the second inputs of the blocks of And are connected to the outputs of the self-propelled switch dividing the pulses of its channel, the outputs of the output keys are combined and are the first output of the second video signal code generator, the third channel includes two blocks of AND elements, the inputs of which are the second information input, the fifth and sixth elements of OR, the output of the fifth element of OR is connected to the second input of the second element of OR the first channel, the output of the sixth OR element is connected to the second input of the fourth OR element of the second channel, and two self-propelled pulse distributors, the outputs of which are connected to the second inputs of the corresponding their blocks of elements And, and includes the first and second keys, a pulse counter and a decoder, the first output of which is connected to the first control input of the first key and to the second control input of the second key, the second output of the decoder is connected to the second control input of the first key and to the first control input the second key, the first control input of the second encoder of video signals is the combined input of the first and second keys and the counting input of the pulse counter, the second control input of the second shaper to The video signal code is the combined input of the signal inputs of the output keys, the third control input of the second video code generator is the control input of the pulse counter, and contains the receiving side, which includes the antenna, sensor control unit, the first and second paths for receiving and processing video codes, the first inputs of which are connected to antenna, the second inputs are connected to the first group of outputs of the touch control unit, the first path for receiving and processing video signal codes is connected in series with the isolated radio signal receiving unit, the radio frequency amplifier and the bipolar amplitude detector, the first and second pulse shapers, the inputs of which are connected respectively to the first and second outputs of the bipolar amplitude detector, includes a video signal channel E _R containing the video signal register E _R whose signal input is connected to the output of the first pulse shaper, the first key is connected in series, the input of which is connected to the output of the first pulse shaper, and the first block of sound registers, the outputs of which are connected to the corresponding inputs of the first DAC (digital-to-analog converter) of the sound codes, the video signal channel E _G containing the video signal register E _G , the signal input of which is connected to the output of the second pulse shaper, the second key is connected in series, the input of which is connected to the output of the second pulse shaper, and the second block of sound registers, the outputs of which are connected to the corresponding inputs of the first DAC sound codes, the second path for receiving and processing video signal codes includes serially connected radio signal receiving unit, radio frequency amplifier and bipolar amplitude detector, first and second pulse shapers, the inputs of which are connected to responsibly to the first and second outputs of the bipolar amplitude detector, and two channels of video E _B , the first channel of the video signal E _B includes the first register of the video signal E _B whose signal input is connected to the output of the first pulse shaper, and a third key is connected in series, the signal input of which is connected to the output of the first pulse shaper, and the third block of sound registers, the outputs of which are connected to the corresponding inputs of the second DAC sound codes, the second channel of the video signal E _B includes a series-connected second video signal register E _B the signal input of which is connected to the output of the second pulse shaper, and the first block of delay elements connected in series with the fourth key, the input of which is connected to the output of the second pulse shaper, and the fourth block of sound registers, the outputs of which are connected to the corresponding inputs of the second DAC sound codes, receiving side contains the first, second, third blocks of pulse amplifiers, a modulation block of radiation, including two emitters and an optical system, a frequency divider connected in series, a block of st a sweep, the first amplifier and the first piezoelectric deflector with a reflector at the end, the first source of positive reference voltage, the output of which is connected to the second inputs of the first amplifier and the first piezoelectric deflector, the second source of negative reference voltage, the output of which is connected to the third inputs of the first amplifier and the first piezoelectric deflector, in series connected frame scan unit from a series-connected element And, a master oscillator and a summing amplifier, a second amplifier and a second piezode a reflector at the end, a third source of positive reference voltage, the output of which is connected to the second inputs of the second amplifier and the second piezoelectric deflector, a fourth source of negative reference voltage, the output of which is connected to the third inputs of the second amplifier and the second piezoelectric deflector, and a matte screen located opposite the reflector of the second a piezoelectric deflector optically connected to the reflector of the first piezoelectric deflector which is optically connected to the radiating side of the radiation modulation unit, respectively the incoming inputs of which are connected to the outputs of the first, second, and third blocks of pulse amplifiers, the receiving side includes two sound channels, each of which contains series-connected DACs of sound codes, a low-pass filter, a power amplifier, and a loudspeaker, characterized in that on the transmitting side the first encoder of the video signals the third inputs of the second and fourth elements OR are combined and are the fourth information input of the first encoder of the video signals, in the second m the video signal encoder the third information input is the third input of the second OR element, the fourth information input is the third input of the fourth OR element and the decoder has a third output, which is the second output of the second video signal encoder, the third information input of the first video signal encoder is connected to the output of the second ADC, the first and second self-propelled pulse distributors are introduced, the input of the first self-propelled pulse distributor is connected to the second output of the second of the video signal code generator, and the outputs are combined and connected to the fourth information input of the first video signal generator and the third information input of the second video signal generator, the input of the second self-propelled pulse distributor is connected to the sixth output of the frequency synthesizer, and its outputs are combined and the combined output is connected to the fourth information the input of the second encoder of the video signals, in the first channel of the transmitter, the second input of the first amplitude modulator is connected to the output of the first encoder of video signals, in the second channel of the transmitter the first input of the second amplitude modulator is connected to the output of the carrier frequency amplifier, and the second input is connected to the first output of the second encoder of video signals, each amplitude modulator includes a series-connected ring modulator and a bandpass filter, the input of the amplifier the carrier frequency is connected to the eighth output of the frequency synthesizer, a channel for generating control signals containing a newly connected horizontal sync pulse isolation unit, frequency synthesizer and self-propelled pulse distributor, key, pulse counter and decoder connected in series, and frame synchronization separation unit, key signal input is connected to the first output of the frequency synthesizer, the first key control input and the first frame scan input are connected to the output of the horizontal sync pulse allocation block, the first, second, third inputs of which are connected to the outputs of the first, second pulse formers s of the first path for receiving and processing codes of video signals and to the input of the first pulse shaper of the second path for receiving and processing codes of video signals, the first input of the block for extracting the frame clock is connected to the output of the second shaper for the second path for receiving and processing codes of video signals, the second input is connected to the output of the block for selecting horizontal signals clock, the output of the frame sync selection block is connected to the second input of the frame scan unit, the first output of the decoder is connected in parallel to ervym control inputs of the first and second keys in the channels of the video signal E _R and video signal E _G and the third and fourth keys in the first and second channels of the video signal E _B , the second output of the decoder is connected in parallel to the second control inputs of the same keys and to the control input of the pulse counter and the second control input of the key, the second output of the frequency synthesizer is connected in parallel to the control inputs of the first, second blocks of sound registers in the video signal channels E _R and E _G and to the inputs of the third and fourth blocks of sound registers in the channels of the video signal E _B , the third output of the frequency synthesizer is connected to the third inputs of the receiving blocks of the radio signal in the first and second paths of receiving and processing codes of video signals, the fourth output of the frequency synthesizer is connected to the control inputs of the adders in the channels of video signals E _R and E _G and in the video channels E _B , the first input of the frequency synthesizer is connected to the output of the horizontal sync pulse allocation unit, the second group of inputs of the frequency synthesizer is connected to the second group of outputs of the touch control unit, the horizontal sync pulse allocation unit includes three pulse counters, three NOT elements, two AND elements, and a diode, inputs of the first and second , the third elements are NOT connected to the inputs of the first, second, third pulse counters, the outputs of the elements are NOT and the output of the horizontal sync pulse allocation unit through the diode are combined and connected to the control m inputs of pulse counters, the outputs of the first and second pulse counters are connected to the first element And, the output of which and the output of the third pulse counter are connected to the inputs of the second element And, the output of which is the output of the horizontal sync pulse allocation unit, the inputs of the pulse counters are connected to the outputs of the first and second pulse shapers of the first path of receiving and processing codes of video signals and the output of the first shaper of the second path of receiving and processing codes of video signals, output unit The frame clock includes a pulse counter, a NOT element, an AND element, and a diode, a pulse counter output and a second input of a frame clock highlight block are connected to the inputs of an And element, the output of which is an output of a frame clock highlight block, the element is NOT connected to the pulse counter input, and the output its and the output of the element And through the diode are combined and connected to the control input of the pulse counter, the input of the pulse counter is the first input of the frame sync pulse allocation unit and is connected to the output second PFN second reception path and processing the video codes, the second input block allocation frame pulse connected to the output selection unit horizontal sync pulse, E the video signal into a channel _R input video signal processing unit E introduced _R , the first block of delay elements, the adder and the second block of delay elements, the first control input of the video signal register E _R connected to the first output of the frequency synthesizer, the second control input of the video signal register E _R connected to the output of the self-propelled pulse distributor in the channel for generating control signals, the inputs of the processing unit of the video signal codes E _R connected to the outputs of the video signal register E _R , control input of the video signal code processing unit E _R connected to the first output of the frequency synthesizer, the inputs of the first block of delay elements are connected to the outputs of the processing unit of the video signal codes E _R and the outputs are connected to the first inputs of the adder, the second inputs of the adder are connected to the outputs of the processing unit of the video signal codes E _R to which the inputs of the second block of delay elements are connected, to the outputs of which the inputs of the first block of pulse amplifiers are connected, the control input of the adder is connected to the fourth output of the frequency synthesizer, in the video signal channel E _G input video signal processing unit E introduced _G , the first block of delay elements, the adder and the second block of delay elements, the first control input of the video signal register E _G connected to the first output of the frequency synthesizer, the second control input is connected to the output of the self-propelled pulse distributor in the channel for generating control signals, inputs of the video signal code processing unit E _G connected to the outputs of the video signal register E _G , control input of the video signal processing unit E _G connected to the first output of the frequency synthesizer, the inputs of the first block of delay elements are connected to the outputs of the video signal code processing unit E _G , a the outputs are connected to the first inputs of the adder, the second inputs of which are connected to the outputs of the video signal code processing unit E _G to which the inputs of the second block of delay elements are connected, to the outputs of which the inputs of the second block of pulse amplifiers are connected, the control input of the adder is connected to the fourth output of the frequency synthesizer, in the first channel of the video signal E _B a block of delay elements has been introduced, the inputs of which are connected to the outputs of the first video signal register E _B and the outputs are connected to the inputs of the third block of pulse amplifiers in the second channel of the video signal E _B introduced a second block of delay elements and an adder, the first inputs of which are connected to the outputs of the second block of delay elements, the second inputs are connected to the inputs of the second block of delay elements, the control input of the adder is connected to the fourth output of the frequency synthesizer, the first control inputs of the first and second video signal registers E _B connected to the first output of the frequency synthesizer, their second control inputs are connected to the output of a self-propelled pulse distributor in the channel for generating control signals, the processing unit of the video signal codes E _R and a video signal processing unit E _G are identical and each includes a trigger, first, second blocks of keys, first, second, third and fourth registers, first, second, third, fourth and fifth blocks of delay elements, an adder and the corresponding number of diodes, information inputs of the first and second registers are combined and through the first the block of delay elements are connected to the outputs of the first block of keys, the information inputs of the third and fourth registers are combined and through the second block of delay elements are connected to the outputs of the second block of keys, the information input of the block The video signal codes are the combined inputs of the first and second key blocks, the control input is a trigger input connected to the first output of the frequency synthesizer, the first trigger output is connected to the control inputs of the second and third registers and the first key block, the second trigger output is connected to the control inputs of the first and the fourth registers and the second block of keys, the first inputs of the adder are connected to the outputs of the second register and through diodes to the outputs of the first register, the second inputs of the adder are connected to the outputs of of the fourth register and through diodes to the outputs of the third register, the adder control input is connected to the trigger input, the adder outputs are appropriately connected to the inputs of the fifth block of delay elements, the inputs of the third block of delay elements are connected to the outputs of the first register, the inputs of the fourth block of delay elements are connected to the outputs of the third the register, the outputs of the third, fourth and fifth blocks of delay elements are combined and are the output of the video signal code processing unit, a quarter is entered at the receiving side the fifth, fifth and sixth blocks of pulse amplifiers, the inputs of which are connected to the outputs of the adders, respectively, in the video signal channel E _R in the video channel E _G in the second channel of the video signal E _B , in the radiation modulation unit, each of the two emitters includes a corresponding number of LEDs of three primary colors, the first emitter is located above the second emitter, the emission plane of both emitters is located in the rear focal plane of the optical system, in the front focal plane of which there is a reflector of the first piezoelectric deflector, radiating sides of the emitters through optical system, the reflectors of the first and second piezoelectric deflectors are optically connected to a matte screen, the inputs of the first emitter are connected They are connected to the outputs of the first, second, and third blocks of pulse amplifiers; the inputs of the second radiator are connected to the outputs of the fourth, fifth, and sixth blocks of pulse amplifiers.

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