RU2369041C1 - Stereo-television system - Google Patents

Abstract

FIELD: communication means.

SUBSTANCE: invention pertains to radio communication technique and may be employed for digital television broadcasting. Result is achieved through introduction of three video signal analog-to-digital converters (ADC) and of six coders into the stereo-television system on the transmitting side, introduction of two CID matrixes into photoelectric converter, on the receiving side there are introduced two receiving registers, the second three colour signals channels of the left frame of the stereo-pair, and control signal conditioner is introduced into every colour signals channels of the left and right frames of the stereo-pair.

EFFECT: three times reduced power consumption of the system during transport-reception of video information due to radio signal transmission through the single radio link and its reception by one receive path.

19 dwg_, 2 tbl

Description

The invention relates to radio communications technology and can be used for digital broadcasting.

The stereo-television system [1] was adopted as a prototype [1], which contains a photoelectric converter / photoelectric converter / based on piezoelectric deflectors that generates two images of one object and includes right and left lenses, the corresponding number of piezoelectric deflectors, horizontal and vertical scan units, six photodetectors, six preamplifiers, and containing six keys, three ADCs of a video signal, two ADCs of a sound signal, a sine wave generator and a frequency synthesizer, three code shapers, two self-propelled pulse distributor / SRI /, trigger and three-channel transmitter of radio signals, on the receiving side containing an antenna, control unit, three paths for receiving and processing codes of video signals, LED flat-panel screen / LED screen /, channel for generating control signals, two sound reproduction channels, IR a transmitter located on the body of the SD screen and ZD glasses with an IR receiver on their frame. Each path for the reception and processing of video signal codes includes a radio signal reception unit, a radio frequency amplifier, a bipolar amplitude detector, two pulse shapers and a channel of one of the color signals, including two color signal registers / R, G, B /, the first delay block, the adder, the second block delays, two frame code stores and two pulse shaping units. In the transmitting side, the video mode is 960 × 540 × 50 Hz. Stereopair code information is transmitted by three radio channels. On the receiving side, three radio signals are received by three paths of receiving and processing codes of video signals of successively right and left frames of stereo pairs, signal codes R, G, B are distributed over their channels, in which doubling of samples in a line from 960 to 1920 and doubling of lines from 540 to 1080 is performed in frame. Codes in each channel are sent to two drive codes of the frame, from them to two blocks of pulse shapers and from them to the inputs of the SD screen, the image from which the viewer perceives the volume through the ZD glasses, the reproduced video mode is 1920 × 1080. The disadvantages of the prototype: the transmission of stereo pair information via three radio channels, its reception by three reception paths and the use of LED cells containing 24 LEDs in each LED screen determine the high energy intensity of the system.

The purpose of the invention is to reduce the energy intensity of the system. The technical result is to reduce the energy consumption of the system by three times when transmitting / receiving information, achieved by transmitting radio signals by one radio channel and receiving it by one channel for receiving and processing codes, and reducing the number of LEDs used in the LED screen by 8 times, achieved by using LED cells, containing three LEDs

The essence of the invention lies in the fact that in the stereo television system containing on the transmitting side of the photomultiplier, three ADC video signals, a code generator, two SRI and a radio signal transmitter, the receiving side, including the path for receiving and processing codes with signal channels R, G, B and SD- screen, on the transmitting side, three ADCs of the video signal, six encoders are introduced, two FDI arrays are introduced into the photoelectric converter, and the transmitter is single-channel, on the receiving side, information is received by one path for receiving and processing video codes, two are received GOVERNMENTAL register and the three channels of the left frame of the stereopair signals R _L, G _L, B _L, in each of the channels of the left and right stereopair frames are input decoder and driver control signals, and the LED display is performed in the SD-cells containing three LEDs.

The transmitting side in FIG. 1, the structure of the digital stream in FIG. 2, the encoder in FIG. 3, the operation diagrams of the encoder in FIG. 4, the code generator in FIG. 5, the receiving side in FIG. 6, the spectrum of the amplitude-modulated signal in FIG. .7, bipolar amplitude detector in Fig. 8, decoder in Fig. 9, code processing unit in Fig. 10, frame code storage in Fig. 11, register block in Figs. 12, 13, control signal generator in Fig. 14, SSI / SIS / selection block in Fig. 15, the LED cell in Fig. 16, the matrix element in Fig. 17, the arrangement of the emitting elements of the matrix in the LED screen on ig.18, temporary system performance chart in Figure 19.

On the transmitting side, a video mode of 800 × 1000 × 25 Hz is received, where 800 is the number of encoded samples in a line, 1000 is the number of encoded lines of a frame, 25 Hz is the frequency of stereo pairs: codes of color signals of the right frame R, G, B and codes of color signals of the left frame R _L , G _L , B _L are transmitted in the same stream in parallel / 2 /. The sampling frequency for analog-to-digital conversion of stereo pair signals is: f _ADC = 800 _counts × 1000 _pages × 25 Hz = 20 MHz.

Line frequency 25 Hz × 1000 _pages = 25 kHz.

. Период следования кодов в потоке 200 нс

период следования разрядов в коде 7,4 нс

27 число разрядов в суммарном коде, который состоит из трех 9-разрядных кодов сигналов R, G, B правого кадра стереопары, суммарный код левого кадра стереопары состоит из трех 9-разрядных кодов сигналов R_Л, G_Л, B_Л. Тактовая частота в системе составляет: f_T=5 МГц×27_разр=135 МГц.When creating a digital image with a high sampling frequency, there will always be codes of equal magnitude, and the higher the sampling frequency, the more equal the size of codes. In the inventive system, compression of the stream of frame codes separately for each color signal R, G, B of the right frame and R _L , G _L , B _{L of the} left frame of the stereo pair is applied. The compression coefficient in each color signal stream is taken to be 4. The sampling frequency at the output of each encoder is 5 MHz

. Codes in 200 ns

the discharge period in the code is 7.4 ns

27 the number of bits in the total code, which consists of three 9-bit codes of the signals R, G, B of the right frame of the stereo pair, the total code of the left frame of the stereo pair consists of three 9-bit codes of the signals of R _L , G _L , B _L. The clock frequency in the system is: f _T = 5 MHz × 27 _bits = 135 MHz.

The carrier frequency of the transmitter is taken f _H = 135 MHz × 15 = 2025 MHz. The upper side frequency f _B = 2025 MHz + 135 = 2160 MHz, the lower side modulating frequency f _HH = 2025 MHz-135 MHz = 1890 MHz. The transmitting side includes / Fig. 1 / photoelectric converter 1 / photomultiplier /, which is a sensor of the video signals of two images: the right and left, generates three color signals R, G, B of the right frame and three color signals R _L , G _L , B _{L of the} left frame stereopair and contains the first / right / lens 2, in the focal plane of which there is the photosensitive side of the array of PZI 3 - devices with charge injection technology Foveon X3 from a three-layer CMOS sensor [2 p.552, 3 p.832-835] with the corresponding optical resolution / not less than 1600 × 1000 /, provide They have a 24-bit color depth [3 p. 835], the first and third outputs of the FDI matrix 3 are connected respectively to the inputs of the preamplifiers 4, 5, 6. The photoelectric converter contains a second / left / lens 7 located at an appropriate distance from lens 2, in the focal plane of the lens 7 is the photosensitive side of the second PZI matrix 8, the first and third outputs of which are connected to the inputs of the pre-amplifiers 9 / R _L /, 10 / G _L /, 11 / V _L /, respectively. The transmitting side includes the first 12, second 13, third 14 ADCs of the video signal R, G, B, fourth 15, fifth 16 and sixth 17 ADCs of the video signal R _L , G _L , B _L , the first 18 to the sixth 23 encoders, encoder 24 codes, a sinusoidal oscillator 25 and a frequency synthesizer 26, the first 27 and second 28 keys, the first SRI 29, which generates the lowercase sync pulses of the SSI, the second SRI 30, which generates the codes of the lowercase sync pulses of the SSI, the second SRI 30, which generates the codes of the sync pulses of stereo pairs SIS, the first ADC 31 and the second ADC 32 of the sound signal, the inputs of which are audible s 3v1, 3v2, and a radio signal transmitter 33 including a carrier frequency amplifier 34 connected in series, an amplitude modulator 35 and an output amplifier 36. The amplitude modulator 35 comprises a ring modulator in series, in which the carrier is suppressed [4 p. 234], and a band-pass filter, filtering out unnecessary side frequency. The ADCs of the video signal 12-17 are identical and are accepted without changes from the prototype [1 p.5, Fig. 5], the ADCs 31, 32 of the sound signal are received without changes from the prototype [1 p.5, Fig. 8] and convert the sound signals to 16-bit codes arriving with sampling of 75 kHz from ADC 31 to the third information input of block 24 / Fig. 1/, from ADC 32 to the fourth information input of block 24. Encoders 18-23 are identical, each turns on / Fig. 3/ in sequence connected register 37, comparison circuit 38 / comparator /, pulse counter 39 and decoder 40, element block 41 connected in series a delay unit 42 and the key frame buffer memory 43 codes. Information inputs are bitwise integrated 1-8 inputs of the register 37, the first inputs 1-8 of the comparison circuit 38 and the inputs of the block 41 delay elements. The outputs are 1-9 outputs of the buffer storage 43 frame codes, its volume is at least 200 × 10 ³ 9-bit codes. The control input is the control input / 5 MHz / block 43. The generator 24 codes includes / 5/3 three channels. The first and second are identical, their outputs are combined. The first channel includes a serially connected first block of 44 AND elements, the first inputs of which are the first information input and receive codes R, G, B of the right frame of the stereo pair, the first 45 and second 46 OR elements, the first output key 47 and the first SRI 48, the second channel includes the second block 49 of AND elements, the first inputs of which are the second information input of block 24 and receive the codes R _L , G _L , B _{L of the} left frame of the stereo pair, the third 50 and fourth 51 OR elements, the second output key 52 and the second SRI 53. The third channel includes third block 54 element And, the first inputs of which are the third information input and receive audio signal codes from the ADC 31, the fifth OR element 55, the output of which is connected to the second input of the second OR element 46, and the third SRI 56 includes the fourth block 57 of AND elements, the first inputs of which are the fourth information input of block 24 and receive the codes of the audio signal from the ADC 32, the sixth element OR 58, the output of which is connected to the second input of the fourth element OR 51, and the fourth SRI 59. Code generator 24 includes the first 60, second 61 and third 64 keys and after ovatelno connected to the pulse counter 62 and a decoder 63. The blocks and elements 44, 49, 54, 57 each comprises 27 AND gates, HRE 48, 53, 56, 59 are 27-bit pulse propelled dispensers. The fifth information input is the signal input of the key 64, the sixth is the third input of the fourth OR element 51. The outputs of block 24 are: the first is the combined outputs of the output keys 47, 52, the second is the third output of the decoder 63. The control inputs are: the first is the combined signal inputs of the first 60 and the second 61 keys and the counting input of the pulse counter 62, the second - the signal inputs of the output keys 47, 52, the third - the control input / U _o / pulse counter, the fourth - the control input of the third key 64. The first output of the decoder 63 n to the first control input of the first key 60, the second output is connected to the second control input of the key 60 and to the first control input of the second key 61, the third output is connected to the second control input of the second key 61 and is the second output of the code generator 24. The second inputs of the elements AND blocks 44, 49, 54, 57 are connected to the outputs of the SRI 48, 53, 56, 59, respectively. The output of the first key 60 is connected to the inputs of the SRI 48, 53, the output of the second key 61 is connected to the inputs of the SRI 56, 59. Reception the side includes / Fig.6 / antenna, control unit / channel selection 65 /, one path for receiving and processing video signal codes - parallel to the right and left frames of the stereo pair, LED flat-panel screen / LED screen /, channel for generating control signals and two sound reproduction channels . The path of receiving and processing video signal codes simultaneously receives and processes the video codes of the right and left frames of the stereo pair and includes serially connected radio signal receiving unit 66, radio frequency amplifier 67, and bipolar amplitude detector 68 and first 69 and second 70 pulse shapers, includes first 71 and second 72 receiving registers, each of which contains 27 bits, three identical channel signals R, G, B of the right frame of the stereopair, three identical second channel signals R _L, G _L, B _L of the left frame stereo ares. The channels of the stereo frame’s right frame include: the signal channel R, the signal register R 73 connected in series, the decoder 74, the code processing unit 75, the frame code accumulator 76 and the control signal generator 77, the signal channel G of the G signal register 78, the decoder 79, the processing unit 80 codes, a drive 81 of frame codes and a driver 82 of control signals, a signal channel B — register 83 of a signal B, a decoder 84, a code processing unit 85, a drive 86 of frame codes and a driver 87 of control signals.

Channels left stereopair frame include signal channel R _A connected in series register 88 a signal R _L, the decoder 89, the block 90 code processing, the drive 91 of the frame codes and the driver 92 control signals, signal channel G _A - register 93 a signal G _L, the decoder 94 , a code processing unit 95, a frame code accumulator 96 and a control signal generator 97, a signal channel _VL - a signal register 98 _A , a decoder 99, a code processing unit 100, a frame code storage 101 and a control signal generator 102. The outputs of the drivers 77, 82, 87, 92, 97, 102 of the control signals are connected to the corresponding inputs of the LED screen 103 with an IR transmitter 104 located on its body. The receiving side includes ZD glasses 105 with an IR receiver 106 on their frame , the input window of the IR receiver 106 is located when used against the output window of the IR transmitter 104. The image from the SD screen by the viewer is perceived as surround through the ZD glasses 105. When the right and left frames are played on the screen, the glasses of the glasses alternately lose transparency, each eye sees its own frame, which gives st reoeffekt. The glasses of the ZD glasses are made using the technology of LCD cells of the translucent type, used as electronically controlled light filters / shutters / [3 p.558, 559, 564, 565]. With the arrival of a 25 Hz / U _{output signal} from the first output of trigger 114 / to the IR transmitter 104, it emits an IR pulse received by the IR receiver 106, which provides a control signal to the LCD cells of the left glass, dimming it for 20 ms, then the circuit The IR receiver emits a second signal in the LCD cells of the right glass, dimming it for 20 ms, as a result, each eye sees its own frame. In the inventive system, the second option is also included: the IR receiver circuit is connected by a connecting cable to the first output of the trigger 114, the same process of controlling the dimming of the glasses of the ZD glasses without the participation of the IR transmitter 104 is in progress. The operating procedure of the receiving side determines the control signal generation channel, which includes sequentially connected block 107 allocation of horizontal sync pulses / SSI /, frequency synthesizer 108, first key 109, counter 110 pulses and decoder 111, block 112 allocation of sync pulses stereopairs / SIS /, the second key 113 and trigger Ep 114. The receiving side includes identical first 115 and second 116 sound reproduction channels, each of which contains registers, a digital-to-analog converter / DAC / with a low-pass filter, a power amplifier and a loudspeaker.

LED display 103 represents the set of radiating elements according to the number of the frame resolution 1.6 × 10 ^6/1600 × 1000 / performed in a suitable screen material. The LED screen includes screen material and a matrix of radiating elements according to the number of frame resolutions. Each emitting element includes three LED cells / LED cells /, each of which emits one of the primary colors R, G, B. The LED cell contains /16 / white LED 153 and the corresponding color filter 154 on the radiating side. Three LED cells constitute a radiating element in the matrix (Fig. 17), the location of the LED cells in the matrix of the screen in Fig. 18. The radiation brightness level of an SD cell is perceived by sight in proportion to the number of radiation pulses performed by the cell LEDs per frame period / 20 ms /, which can be from one / 78 μs / to 255/20 ms /. The total emission of the three primary colors by the three LEDs of the radiating element forms the brightness and color tone of one pixel on the screen. As LEDs, LEDs with polymer organic molecules can be used — LEDs of the SDT / or PLED / technology [8 p. 43] or super-bright white LEDs of the Nichia and Ledtronics companies [9 p. 47]. LEDs - both SDT and super-bright technologies are executed in the screen material by the method of microelectronic technology. The sizes of superbright LEDs are allowed with a diameter of up to 0.5 mm / 16 /, the size of one emitting element in this case is 1 × 1 mm / 17 /, the size of the LED screen will be:

horizontally 1600 × 1 mm = 1600 mm,

vertical 1000 × 1 mm = 1000 mm,

188 cm or 74 ”diagonal.

Decoders 74, 79, 84, 89, 94, 99 are identical, each includes / Fig. 9/ connected in series the first 9-bit register 117, the drive 118 code frame with a capacity of 200,000 9-bit codes / 200 _count × 1000 _lines /, the second 9 a bit register 119, a first block of keys 120 of 8 keys and a third 8-bit register 121, serially connected a second block of keys 122 of eight keys, an 8-bit subtracting counter 123 pulses and a decoder 124, the first 125, the second 126, the third 127 and fourth 128 keys. The information inputs of the decoder are 1–9 inputs of the first register 117, the outputs are 1–8 outputs of the third register 121. The control inputs are: the first is the combined control input of the register 117 and the signal input / 5 MHz / of the third key 127, the second is the combined signal inputs / 20 MHz / keys 125, 126, 128. The ninth digit output of the second register 119 is connected in parallel to the first control input of the second key 126, to the second control inputs of the third 127 and fourth 128 keys and the first 125 keys and to the second control input of the first block 120 keys to the first control input of the second block of keys 122. The output of the first key 125 is connected to the first control input of the third register 121, the second control input of which is connected to the output of the second key 126, to which the counting input of the subtracting pulse counter 123 is connected. The output of the decoder 124 is connected in parallel to the first control input of the first key block 120, to the second control input of the second key block 122, to the first control inputs of the keys 125, 127, 128 and to the second control input of the second key 126. The output of the third key 127 is connected to the control input drive 118 frame codes, the output of the fourth key 128 is connected to the control input of the second register 119. The processing units 75, 80, 85, 90, 95, 100 are identical, each includes / Fig. 10/ trigger 129, the input of which is the control input / 20 MHz /, first 130 and WTO oh 131 blocks of 8 pieces in each of keys, the first 132, second 133, third 134, fourth 135 registers, an adder 136, fifth 137 and sixth registers 138, and 16 diodes. The information inputs of block 75 are the bitwise combined inputs of blocks 130, 131 of keys; codes with a frequency of 20 MHz are received in parallel form from decoder 74. The outputs are the bitwise combined outputs 0-7 of the adder 136 and the outputs 1-8 of the registers 137, 138, which perform storage / delay / codes for 50 ns. The output frequency of the codes from the block 75 40 MHz. The first trigger output 129 is connected to the control inputs of the registers 133, 134, 137 and to the control input of the key block 130, the second trigger output is connected to the control inputs of the first 132, fourth 135, sixth 138 registers and to the control input of the second key block 131. The trigger input is connected to the control input of the adder 136. The outputs of the first block 130 keys are connected to 1-8 inputs of the first 132 and second 133 registers. The outputs of the second block of keys 131 are connected to 1-8 inputs of the third 134, the fourth 135 registers. The outputs of the first register 132 are connected to the inputs of the fifth 137 of the register and through diodes to the first inputs of the adder 136, to which the outputs of the second 133 register are connected. The outputs of the third 134 register are connected to the inputs of the sixth 138 register and through the diodes to the second inputs of the adder, to which the outputs of the fourth register 135 are connected. The drives 76, 81, 86, 91, 96, 101 frame codes are identical, each includes / 11 / blocks of 139 registers by the number of lines in the frame / 1000 /. The information input of block 76/81 / is the bitwise integrated 1-8 inputs of blocks 139 _1-1000 . The control inputs are: the first is the first control input / 25 Hz / of the first block 139 of ₁ registers, the second is the combined second control inputs of U _output / 25 kHz / blocks of 139 registers, the third is the combined third control inputs of U _d / 40 MHz / blocks of 139 registers . Each control output of the previous block of registers is the first control input of each subsequent block of 139 registers. The control output of the last block 139 of ₁₀₀₀ registers is connected in parallel to the fourth control inputs of all blocks of 139 registers. The outputs of the drive 76 frame codes are the outputs of all blocks 139 registers. Blocks 139 registers are identical, each includes / 12, 13 / first 140 and second 141 keys, a distributor 142 pulses and eight registers 143 _1-8 , each of which contains 1600 bits by the number of samples in a row. The information inputs of the block 139 registers are the first to eighth bit-wise combined third inputs of the bits of the eight registers 143. The outputs are the parallel outputs of all the bits / 1600 / eight registers 143, total outputs 12800/1600 × 8 /. Outputs 1000 blocks 143 are the outputs of the drive frame 76 codes, these outputs 12.8 × 10 ^6/12800 × 1000 /. The control inputs are: the first is the first control input / 25 Hz / of the first key 140, the second is the signal input U _vy / 25 kHz of the second key 141, the third is the signal input U _d / 40 MHz / first key 140, the fourth is the first control input of the second key 141. The last output of the distributor 142 pulses is the control output of the block 139 registers for the next block 139 ₂ registers and is connected to the first control input of the first key 140 / Fig.12/. The output of the first key is connected to the input of the pulse distributor 142, the outputs of which are sequentially, starting from the first, connected to the first / clock / inputs of the bits of eight registers 143. The output of the second key 141 is connected in parallel to the second inputs of the bits of eight registers 143 and to the second control input of its key 141, having passed one pulse, Uout closes the key 141. The outputs of the frame code drives (Fig. 6/) are connected to the information inputs of their drivers 77, 82, 87, 92, 97, 102 of the control signals, the purpose of which is to perform transformations “Code - the number of radiation pulses” to obtain the corresponding duty cycle of the LED emissions for the frame period. Each of the control signal generators includes converters according to the frame resolution number 1600 × 1000 = 1.6 × 10 ⁶ . The shapers of the control signals are identical, each includes (Fig. 14/) a block of shapers of pulses 144, containing identical pulse-shaping circuits by the number of converters / 1.6 × 10 ⁶ / and which is the control input connected to the corresponding output of the trigger 114/6 /, and code-to-number of radiation pulses converters, the number of which is based on the number of frame resolutions. Each converter includes / FIG. 14/ series-connected decoder 145, the inputs of which are information inputs of the converter, a key block 146 of 255 keys and an output key 147, includes an SRI 148 and a power supply 149 for one LED in the LED screen. The outputs of the decoder 145 are connected to the first corresponding control inputs of the key block 146, the outputs of which are combined and connected to the control input U _{from the} output key 147, the signal input of which is connected to the output of the power supply 149. SRI 148 is connected to the corresponding output in block 144 and has 255 bits, the outputs of which are connected to the signal inputs of the corresponding keys in block 146 keys / input 2 /. The information inputs of block 77/82, 87 / are the information inputs of all converters “code - the number of radiation pulses”, the outputs of the output keys 147 are the outputs of the block 77/82, 87 /, which are connected to the corresponding inputs of the LED screen 103. The initial state of the output keys 147 and keys in blocks 146 closed. With the control pulse input to the driver input 77 of the pulse control signal from the corresponding trigger output 114 of the pulse shaper circuit of block 144, pulses U _{P of the} corresponding amplitude and duration are issued in parallel and all SRI 148 are put into operation. The duration of the SRI 148 is, the pulse passes from the first discharge to the last 255 the discharge is 20 ms / 50 Hz /. Codes from all drives of frame codes 76, 81, 86, 91, 96, 101 are issued in parallel and synchronously to decoders 145 of the shapers of control signals 77, 82, 87, 92, 97, 102. Output signals from decoders 145 / Fig. 14/, respectively the values of the codes are opened with the corresponding keys in blocks 146. With the arrival of a control signal to the input of block 144, the inputs of all SRI 148 receive pulses U _P , which start the SRI 148. At the outputs of 255 bits, a pulse arrives through 78 μs at the signal input of its key in block 146, which, having passed the public key block 146, opens the output key 147, and the same pulse closes the passed key, coming from its output to the second control input of the key, as in the key 141 of the block 139 / Fig.12/. Thus, all the keys of the block 146 after the operation of all 255 bits of the SRI 148 go into a closed initial state.

, где 20 мс /20000 мкс/ длительность кадра, 255 - разрешение 8-разрядного кода, число выходных сигналов с СРИ 148. Соответственно величине кода светодиод за период кадра запитывается по 78 мкс столько раз, сколько было открыто ключей в блоке 146 ключей /фиг.14/, чем больше величина кода, тем больше число импульсов излучений произвел светодиод за период кадра 20 мс. Пример распределения импульсов излучений в периоде кадра соответственно величине кода в таблице 1.Each pulse U _from block 146 opens the output key for a duration of 78 μs:

, where 20 ms / 20000 μs / frame duration, 255 is the resolution of the 8-bit code, the number of output signals from the SRI is 148. Accordingly, the LED code for the frame period is powered by 78 μs as many times as the keys were opened in the key block 146 / fig. .14 /, the larger the code value, the greater the number of pulses of radiation produced by the LED over a frame period of 20 ms. An example of the distribution of radiation pulses in the frame period, respectively, the code value in table 1.

Table 1 Decoder Input Code 145 The distribution of radiation pulses in the frame period The number of emissions per frame 00 ... 00 00 ... 000 0 00 ... 001 00 ... 128 000 one 00 ... 010 00 88 176 000 2 00 ... 011 00 64 128 192 00 3 . . . . . . . . . 11111110 1, 2, 3, 4 ... 253, 254 254 11111111 1, 2, 3, 4 ... 253, 254, 255 255

0 - no radiation,

1, 2, 3, 4 ... 255 - the sequence numbers of emissions in the frame period. Following radiation pulses in the frame period at equal time intervals corresponds to the natural perception of the human vision of the image in terms of reliability in color reproduction and brightness. The inertia of the operation of the LEDs should be up to 1 μs.

In blocks 76, 81, 86, the codes of signals R, G, B of the right frame of the stereo pair are concentrated, in blocks 91, 96, 101, the codes of signals R _L , G _L , B _{L of the} left frame of the stereo pair are concentrated.

The SIS 25 Hz pulse from block 112 opens the key 113, which passes the 50 Hz pulses of the frame frequency, the first pulse passing the key is the pulse of the right frame of the stereo pair. From the output of the key 113, 50 Hz pulses are fed to the input of the IR transmitter 104 and to the input of the trigger 114. Upon completion of filling in the drives 76, 81, 86, 91, 96, 101 frame codes of all registers 139/11 / stereopair right frame codes R, G, B and codes of the left frame of the stereo pair R _L , G _L , B _{L are} simultaneously and synchronously issued to the drivers 77, 82, 87, 92, 97, 102, of the control signals. The conversion of codes into the number of radiation pulses in them is parallel. The signal from the first output of flip-flop 114 U _{vy1 is} fed to the control input of blocks 77, 82, 87, pulse shaping circuits U _{P of} block 144 / Fig. 14/ start the SRI 148, pulses from the outputs of the discharges of which are sequentially through public keys in block 146 to the control input U _{from the} output key 147. Each pulse opens the output key 147 for a pulse duration U _from / 78 μs /, and the power supply 149 supplies its LED for 78 μs in the LED screen. Over a period of 20 ms of the right frame, each LED gives as many radiation pulses as the keys in block 146 were opened from the decoder 145. At this time, the left glass is darkened in the ZD glasses and the viewer sees the right frame with the right eye. After 20 ms, the signal U _out2 from the second output of flip-flop 114 arrives at the control inputs of blocks 92, 97, 102, in which SRI 148 are triggered from block 144 by signals U _P , the same processes follow as in blocks 77, 82, 87, and the viewer through the open left glass of the ZD glasses with his left eye sees the left frame of the stereo pair.

Next, the processes are repeated.

The block 107 allocation SSI and block 112 the allocation of clock pulses of stereopairs SIS identical, each includes / Fig.15/ 5-bit counter 150 pulses, decoder 151, element NOT 152 and two diodes. The information input of the block 107/112 / is the counting input of the counter 150 pulses, the control input is the control input U _{o of the} counter 150 pulses, which through the first diode is connected to the output of the corresponding driver / 69, 70 / pulses, Fig.6. In block 107, the information input is connected to the output of the pulse shaper 69, the control input is connected to the output of the pulse shaper 70. In block 112, the information input is connected to the output of block 70, the control input through a diode is connected to the output of block 70. The output of block 107 is the output of the decoder 151, which is connected through the second diode to the output of the element NOT 152, and together they are connected to the control input of the pulse counter 150 after the first diode. The SSI code is a 27-bit code from one unit. The SIS code is also a 27-bit code from one unit. The SSI code arrives at the counting input of block 107, at this moment there are no pulses from block 70, the SIS code goes to the counting input of block 112, at this moment there are no pulses from block 69 (Fig. 2/).

The operation of blocks 107/112 / Fig. 15.

With the receipt of the SSI code at the counting input of the counter of 150 pulses, it counts 27 pulses in a row, the code 11011 is generated in the counter. As a result, the outputs 1, 2, 4, 5 bits of the counter 150 show signals, they are decrypted by the decoder 151, and the output of block 107 appears pulse SSI / 25 kHz /. When the pulses of the SSI code are received from block 70, no code pulses arrive at the second input of block 107. Starting from the second code of the line, codes from 70 will go to the control input of counter 150, and with the arrival of each pulse, code 150 will reset to zero and will not be able to reach counts 27. In parallel with the counting input of the counter 150, there are line codes, and for each zero in the code the element NOT 152 gives a pulse to the control input of the counter and resets it. In addition, from the output of the decoder 151, the SSI signal through the second diode enters the control input of the counter 150 and resets it. Thus, the circuit block 107/112 / eliminates the appearance of a false signal SSI / SIS /.

Block 112 works similarly.

FEP 1 the first matrix of FDI 3 generates three analog video signals of the right frame and in parallel with the second matrix of FDI 8 generates three analog video signals of the left frame. For each of the three layers of FDI matrices from key 27 pulses of 25 kHz line frequency are received to read the pixel signals vertically, inputs of 1 matrix. At the second inputs of the matrices from the key 28 pulses of 20 MHz are received for reading the signals of the pixels horizontally [3 p.832]. The analog signals from the matrices are fed to preamplifiers 4–6, 9–11, from the outputs of which they go to the ADCs, respectively 12–14 and 15–17, from the outputs of which 8-bit codes of color signals with sampling rate of 20 MHz go to the inputs of the encoders 18 -20 of the right frame, to the inputs of the encoders 21-23 of the left frame. The synchronization of reading signals from FDI arrays is performed by opening the keys 27, 28 with a leading edge of the pulse of 25 Hz for a frame duration of 40 ms. Frequency synthesizer 26 outputs: a first output pulses of 20 MHz sampling ADC codes 12-17, from the second output pulses 5MHz U _vyd with encoders 18-23 and the first control input of the codes 24, ADC 31, 32, the third - the pulses 75 kHz sampling of the sound signal codes to the second control inputs of the ADC 31, 32, from the fourth - 135 MHz clock pulses to the second control input of block 24, from the fifth - 25 kHz line frequency pulses to the key 27 signal input, from the sixth - 25 Hz pulse stereopairs, from the seventh output - sinusoidal oscillations of the carrier frequency 20 25 MHz with a stability of 10 ^-7 to a transmitter of 33 radio signals.

The ADCs convert the analog video signals into 8-bit codes, which in parallel are fed to 1-8 inputs of encoders 18-23.

The work of the encoders, Fig.3.

При коэффициенте сжатия выше 4 частота 5 МГц выдачи будет тем более удовлетворять. Схема 38 сравнения выполняет сравнение кодов и представляется двумя микросхемами 53ОСП1 с временем срабатывания 18 нс [5 с.279]. При неравенстве кодов А>B появляется сигнал на выходе 2 блока 38 /в микросхеме выход 5 [5 с.272, рис.2.190]/, при равенстве кодов А=В сигнал с выхода 1 /в микросхеме вых.7/. При равенстве кодов сигнал с выхода 1 блока 38 закрывает ключи в блоке 42, поступает счетным импульсом в счетчик 39 импульсов и как сигнал U_выд на первый управляющий вход регистра 37. Счетчик 39 8-разрядный, максимальный код в нем 255 /11111111/, отсюда и максимальный коэффициент сжатия 255. Счетчик из микросхем К531ИЕ160 с временем срабатывания 8 нс [5 с.428]. При появлении неравных кодов со схемы 38 следует сигнал с выхода 2 или 3 /А<B/, которые объединены, сигнал с них используется для выдачи кода числа равных кодов из счетчика 39 импульсов через диоды на входы блока 43 и для заполнения в блоке 43 девятого разряда, с которого сигнал используется для опознания по нему кода числа равных кодов при декодировании. Этот же сигнал открывает ключи в блоке 42 /вход 1/ и обнуляет регистр 37 /вход 2/. Выданный перед этим с блока 43 код является первым кодом последовательности, диаграмма I фиг.4, они помечены крестиками. Коды, равные по величине и подсчитанные счетчиком 39, исключаются из потока, диаграмма III фиг.4, за счет их и идет сжатие потока кадра. Емкость буферного накопителя 43 составляет 200×10³ 9-разрядных кодов для обеспечения темпа следования кодов с частотой 5 МГц. При следовании подряд кодов, равных по величине более 255, в работу вступает дешифратор 40. При коде 11111111 дешифратор 40 выдает сигнал, который одновременно открывает ключи в блоке 42, обнуляет регистр 37, сигналом U_выд выдает код из счетчика 39 /вход 1/ и обнуляет счетчик 39 /вход 2/, а в 9-й разряд блока 43 поступает сигнал опознания кода числа равных кодов. Пропускная способность кодера определяется временем срабатывания схемы 38 сравнения, которая обеспечивает до 40 Мбайт/с и удовлетворяет требуемой 20 Мбайт/с. С выходом кодеров 18, 19, 20 9-разрядные коды в параллельном виде поступают на первый информационный вход формирователя 24 кодов /фиг.5/. С выходов кодеров 21, 22, 23 9-разрядные коды поступают на второй информационный вход формирователя 24 кодов. Первым кодом в первой строке кадра идет 27-разрядный код СИС, начиная со второй строки, первым кодом в каждой строке идет код ССИ. В сжатом потоке кодов со 2-го по 197 идут коды цветовых сигналов /фиг.2/, три кода 3в1 и три кода 3в2. Последовательно идущие три 9-разрядных кода R, G, B составляют 27-разрядный суммарный код правого кадра стереопары, три 9-разрядных кода R_Л, G_Л, В_Л составляют 27-разрядный код левого кадра стереопары. На выходе блока 24 единицы в суммарном коде правого кадра стереопары представляются положительными полусинусоидами моночастоты 135 МГц, а единицы в суммарном коде левого кадра стереопары представляются отрицательными полусинусоидами той же частоты.Codes are received at 1-8 inputs of the register 37, at the first inputs of the comparison circuit 38 and at the inputs of the block 41 delay elements. The initial state of the keys in block 42 is open. The code in block 41 is delayed by the response time of the comparison circuit / 18 ns / and arrives through the public keys of block 42 to the 1-8 inputs of the buffer storage 43 frame codes with a capacity of 200 × 10 ³ 9-bit codes. The comparison circuit 38 compares the size of each previous and subsequent codes in order to identify their equality or inequality. When following unequal codes, they pass through block 41, the public keys of block 42 and go to 1-8 inputs of the buffer storage 43 codes. The issuance of codes from block 43 is performed by a signal _Uout 5 MHz from the output 2 of block 26. The codes are received in block 43 when unequal codes are followed, with a frequency of 20 MHz. In the general stream of codes there are a large number of equal in size codes following in sequence. Due to equal codes following sequentially, the encoder performs compression of the stream of codes. The compression coefficient, floating from 1 to 255, the total compression ratio of the stream of frame codes is taken to be 4, so the output frequency from block 43 is 5 MHz

With a compression ratio above 4, a frequency of 5 MHz of output will be all the more satisfying. The comparison circuit 38 compares the codes and is represented by two 53 OSP1 microcircuits with a response time of 18 ns [5 p. 279]. With the inequality of codes A> B, a signal appears at the output 2 of block 38 / in the output 5 circuit [5 p.272, Fig. 2.190] /, with the equality of the codes A = B, the signal from output 1 / in the output 7 / chip. If the codes are equal, the signal from the output 1 of block 38 closes the keys in block 42, arrives as a counting pulse in the counter 39 pulses and as a signal U _comes to the first control input of the register 37. Counter 39 is 8-bit, the maximum code in it is 255/11111111 /, hence and the maximum compression ratio is 255. A counter made of K531IE160 microcircuits with a response time of 8 ns [5 p. 428]. When uneven codes appear from circuit 38, a signal from output 2 or 3 / A <B /, which are combined, follows, the signal from them is used to issue a code for the number of equal codes from the pulse counter 39 through diodes to the inputs of block 43 and to fill in block 43 of the ninth the bit from which the signal is used to identify the code for the number of equal codes during decoding. The same signal opens the keys in block 42 / input 1 / and resets the register 37 / input 2 /. The code issued before this from block 43 is the first sequence code, diagram I of figure 4, they are marked with crosses. Codes of equal magnitude and counted by the counter 39 are excluded from the flow, diagram III of FIG. 4, due to them, the frame stream is compressed. The capacity of the buffer drive 43 is 200 × 10 ³ 9-bit codes to ensure the rate of repetition of codes with a frequency of 5 MHz. When following consecutive codes, equal in size than 255, a job enters the decoder 40. When the code 11111111 decoder 40 outputs a signal that simultaneously opens keys at block 42, resets the register 37, outputs a signal U _vyd code from the counter 39 / input 1 / and reset counter 39 / input 2 /, and the 9th digit of block 43 receives a signal to identify the code of the number of equal codes. The bandwidth of the encoder is determined by the response time of the comparison circuit 38, which provides up to 40 MB / s and satisfies the required 20 MB / s. With the output of encoders 18, 19, 20, 9-bit codes in parallel form are fed to the first information input of the generator 24 codes / Fig.5/. From the outputs of the encoders 21, 22, 23, 9-bit codes are fed to the second information input of the encoder 24 codes. The first code in the first line of the frame is the 27-bit SIS code, starting from the second line, the first code in each line is the SSI code. In the compressed stream of codes from the 2nd to 197th there are codes of color signals (Fig. 2/), three codes 3v1 and three codes 3v2. Three 9-bit consecutive codes R, G, B constitute a 27-bit total code of the stereo frame’s right frame, three 9-bit codes R _L , G _L , V _L comprise a 27-bit code of the stereo frame’s left frame. At the output of the block, 24 units in the total code of the right frame of the stereopair are represented by positive half-sine waves of the 135 MHz monofrequency, and units in the total code of the left frame of the stereopair are represented by negative half-sines of the same frequency.

The operation of the shaper 24 codes, Fig.5.

Timing diagrams of the operation of block 24 in Fig. 19. Block 24 converts parallel codes into sequential ones and replaces the representation of units from pulses with positive and negative half-sine waves in them. At the first information input in block 44, 9-bit codes of the right frame of the color signals R, G, B are received, at the second information input in block 49, 9-bit codes of the left frame of R _L , G _L , V _L are received. The third information input to block 54 receives 16-bit 3v1 audio signal codes with an ADC 31, the fourth to block 57 receives 16-bit 3v2 audio signal codes with an ADC 32, the fifth receives 27-bit SSI codes from SRI 29 and the sixth 27-bit SIS codes are received from the SRI 30. The second inputs of blocks 44, 49, 54, 57 receive sequentially 27 pulses from the SRI 48, 53, 56, 59, respectively. The start signal U _П SRI 48, 53 comes from key 60, the start signal U _P SRI 56, 59 comes from key 61.

. Выходной ключ 47 в открытом состоянии пропускает одну положительную полусинусоиду на выход, выходной ключ 52 в открытом состоянии пропускает на выход одну отрицательную полусинусоиду.From the outputs of blocks 44, 49, the pulses of the codes sequentially through the OR elements 45, 46 and 50, 51 are fed to the control inputs of the output keys 47 and 52 and open them for a duration of 7.4 ns

. The output switch 47 in the open state passes one positive half-sine wave to the output, the output switch 52 in the open state passes one negative sine-wave to the output.

The outputs of the output keys are combined and are the first output of block 24, the output signal from which is a full or incomplete sinusoid of a single frequency of 135 MHz with a stability of 10 ^-7 . The sequence of codes in the line is determined by the counter 62 pulses and the decoder 63. The counter 62 8-bit counts the pulses of the line 5 MHz from the first to the 200th. When the code 00000001, the pulse from the first output of the decoder 63 opens the key 60, which transmits 5 MHz pulses, the generation of line codes from the second to 197. With the arrival of the counter counter 62 of the 197th pulse, the signal from the second output of the decoder 63 closes the key 60 and opens the key 61, with three sound codes being generated. With the arrival in the counter 62 of the 200th pulse of the line from the third output of the decoder 63, the pulse closes the key 61 and as a signal U _P starts the SRI 29, issuing a serial 27-bit SSI code to the signal input of the third key 64, in the open state it transmits the SSI code to the third the input of the OR element 46. With the arrival of a pulse of 25 Hz U _P to the input of the SRI 30, it closes the key 64 with the leading edge for the duration of its duration and starts the SRI 30, which issues a serial 27-bit SIS code to the third input of the OR element 51, with the end of the pulse duration U _W / 200 ns / key 6 4 opens. The pulse duration UЗ is determined by the duration of the SIS code, 27 bits are 200 ns. When the SSI codes go, the SIS code does not go and vice versa.

The amplitude modulator 35 of the transmitter 33 consists of a series-connected ring modulator and a band-pass filter [4, p.234]. In the ring modulator, the carrier frequency is suppressed, the band-pass filter filters the lower side, Fig.7. The upper side modulated frequency of 2160 MHz with the information of the stereo pair codes by block 35 is provided to the output amplifier 36 and is radiated by it. With the adopted carrier frequency stability of 10 ^{-7, the} occupied band on the air is ± 216 Hz or 432 Hz, to transmit such a band, much less transmitter power is needed than when transmitting a signal with a band of several MHz. The radio signals at the receiving side are received by the block 66/6 /, which is a channel selector with electronic tuning. Block 66 includes an input circuit, a radio frequency amplifier, and a mixer. The radio frequency signal through the communication loop is fed to the mixer, the second input of which from the frequency synthesizer 108 / input 3 of block 66 / is supplied with a frequency equal to the frequency of the transmitter 33, necessary for detecting a single-band signal [6, p.146]. The signal from the mixer, which is the output signal of block 66, is input to the amplifier 67 of the radio frequency, where it is amplified to the required value and fed to the input of a bipolar amplitude detector 68, made according to the circuit of Fig. 8. Diode D1 selects the positive envelope of the modulating signal / Fig. 19, diagram 9 /. The diode D2 from the modulating one selects the envelopes of the positive half-sine waves - symbols of units of codes of the right frame R, G, B of the stereo pair. D3 diode from the modulating one selects the envelopes of negative half-sine waves - symbols of units of codes of the left frame R _L , G _L , B _{L of a} stereo pair. From the first output of block 68, the detected positive half-sine waves of frequency 135 MHz are fed to the input of the first pulse shaper 69, and from the second output of the block 68, the detected negative half-sine waves of frequency 135 MHz go to the input of the second driver 70 pulses. The pulse shaper 69, 70 is made with an asymmetric trigger circuit with emitter coupling [7, p.209], which forms rectangular pulses from harmonically changing signals. The pulses have one polarity and a duration equal to the duration of the pulses on the transmitting side. Units in codes are represented by pulses, zeros by their absence. When you turn on the power, the key 109 in the closed state. The operating procedure of the receiving side is determined by the signals of the channel for generating control signals, the decisive role belongs to the block 107 allocation SSI. With each arrival at the input of block 107, a code of 27 units / in the absence of pulses from block 70 / at the output of block 107, an SSI horizontal sync pulse arrives at the first input of frequency synthesizer 108 and opens the key 109. The SSI performs synchronization / tuning / frequencies in block 108, the natural frequency of which has a stability of 10 ^-6 . The second inputs of block 108 are connected to the second group of outputs of block 65 / channel selection /, the signal from which determines the frequency output from block 108 to the third input of block 66. Frequency synthesizer 108 outputs: 5 MHz pulses from the first output, clock pulses from the second output 135 MHz, from the third - pulses of 75 kHz sampling of sound signals, from the fourth - pulses of sampling codes 20 MHz, from the fifth - sinusoidal oscillations of the carrier frequency, from the sixth - pulses of 50 Hz frame frequency, from the seventh - pulses of a double sampling frequency of video codes 40 MHz . From the pulse shaper 69, the codes of the stereopair's right frame are fed to the information input of the first receiving register 71, from the second pulse shaper 70 the codes of the stereopair's left frame are fed to the information input of the second receiving register 72. The receiving registers 71, 72 each include 27 bits for receiving the total stereopair codes from 9-bit three signal codes, respectively, R, G, B of the right frame and R _L , G _L , B _{L of the} left frame of the stereo pair. With the register 71 receiving signals U _vyd 5MHz issued codes into the registers 73, 78, 83, 72 from the receiving register in the registers 88, 93, 98. The outputs of these registers are given codes with a frequency of 5 MHz in their decoders, respectively 74, 79, 84, 89, 94, 99.

The operation of the decoders, Fig.9.

Codes in parallel form enter the first register 117, from which they are issued to the drive 118 frame codes, which have a capacity of 200 · 10 ³ 9-bit codes. From drive 118, codes are generated by 5 MHz signals from key 127. With the key 127 closed, drive 118 focuses the codes in itself. The initial state of the keys in block 120 is open, in block 122 is closed, keys 125, 127, 128 are open, key 126 is closed. In 1-8 bits of the second register 119, 1-8 information bits of codes are received, and if there is a number of equal codes in the 9th digit of the code recognition signal, it enters the 9th bit of register 119. From register 119, the code is issued by a signal from key 128 already with a frequency of 20 MHz. While codes without the identification signal in the 9th category are received in register 119, they enter through the public keys in block 120 into the third register 121, and from it they are issued by the signal U _issI from key 125 to the output of the decoder. The signal U _issI when issuing the code and resets the bits of register 121. When the code 119 receives an identification signal in the 9th digit, the signal from the ninth category of register 119 closes the keys in block 120 / input 2 /, closes the keys 125, 127, 128, opens the key 126 and the keys in block 122. The issuance of codes from the register 119 is interrupted, and the drive 118 codes accumulates the codes of the frame, as it continues to receive codes. The code of the number of equal codes through the public keys in block 122 enters the subtracting counter 123 pulses, the counting input of which from the key 126 receives pulses of 20 MHz. The pulse from the key 126 arrives as a signal U _vy2 to the second control input of the register 121 and outputs the code contained in it, but does not reset it. Therefore, while the counter 123 is working to subtract from the register 121 the same code is issued, these codes were removed when the stream was compressed in the encoder on the transmitting side. From the output of register 121 is a 100% restored stream of codes. From register 121, only 8-bit codes with a sampling rate of 20 MHz go to block 75. Upon completion of the subtraction in counter 123, a code of zeros enters decoder 124; from the output of decoder 124, the signal simultaneously closes the keys in block 122, closes the key 126, opens the keys in block 120 / input 1 / and keys 125, 127, 128. From drive 118, codes are again sent to register 119, from it through the public keys of block 120 to register 121 and the processes are repeated. The decoder throughput is determined by the response time of 10.5 ns of counter 123, which of the 100IE137 microcircuits [5 p. 428] plus the response time of the decoder 124 6 ns / microcircuit 100ID161 / [5 p. 433]. Code stream recovery rate up to 50 MB / s. The reconstructed stream of codes with a frequency of 20 MHz and the number of samples in a row of 800/200 × 4 / is fed to the input of the 75/80, 85 / block of code processing to double them / 800 × 2 /. Doubling of samples is performed by obtaining intermediate / average / codes between each passing and the following code. The blocks perform the addition of codes and the division of the sum code into two, and the division is performed without time-consuming discarding the least significant digit in the sum code, as when dividing the decimal number by ten. The discarding of the least significant bit in the sum code is performed by the corresponding connection of the outputs 0-7 of the adder 136 / Fig. 10/ and the outputs 1-8 of the registers 137, 138:

, т.е. 40 МГц. Процесс сложения в сумматоре 136 длится 25 нс. Сумматор выполняется из микросхем К555ИМ6 [5 с.258]. После включения питания в регистрах 132-135 нули.Bit 0 means transfer to the high bit when the sum of codes in the adder. Doubling samples in a row reduces code repetition by half, equal to 25 ns

, i.e. 40 MHz. The addition process in the adder 136 lasts 25 ns. The adder is made of K555IM6 microcircuits [5 p. 258]. After power-up in the registers 132-135 zeros.

. Регистры 137, 138 выполняют хранение кодов 50 нс, причем первая половина хранения 25 нс приходится на время процесса сложения кодов в сумматоре 136. С приходом второго импульса 20 МГц в триггер 129 он же обнуляет сумматор, а сигнал со второго выхода триггера U_выд2 одновременно: выдает из регистра 138 на выход блока 75 код №2 “код 0”, с регистра 132 “код 1” в регистр 137 и через диоды в сумматор 136, с регистра 135 “код 0” в сумматор, открывает ключи в блоке 131 и регистры 134, 135 заполняются кодом “код 2”. В сумматоре идет сложение “код 0+ код 1”, затем код суммы идет на выход с делением на 2: Код №3

. С приходом третьего импульса в триггер 129 он обнуляет сумматор 136, а сигнал U_выд3 с первого выхода триггера одновременно: выдает с регистра 137 код №4 “код 1” на выход блока, из регистра 133 “код 1” в сумматор, из регистра 134 “код 2” в регистр 138 и через диоды в сумматор, открывает ключи в блоке 130 и регистры 132, 133 заполняются кодом “код 3”. В сумматоре идет сложение “код 1+код 2”, затем код суммы идет на выход с делением на 2: код №5

. С приходом четвертого импульса в триггер 129 он обнуляет сумматор, а сигнал U_выд4 со второго выхода триггера одновременно: выдает с регистра 138 код №6 “код 2” на выход, из регистра 132 “код 3” в регистр 137 и через диоды в сумматор 136, из регистра 135 “код 2” в сумматор, открывает ключи в блоке 131 и регистры 134, 135 выполняются кодом “код 4”. В сумматоре 136 идет сложение “код 2+ код 3”, код суммы с делением его на 2 идет на выход: код №7

.With the arrival of the first 20 MHz pulse to trigger 129 (Fig. 10/) from its first output, the signal U _issI simultaneously: provides a “code 0” from register 133 to the first inputs of the adder 136, from register 134 outputs a “code 0” to register 138 and through diodes to the second inputs of the adder 136, the output signals nullify the registers 132-135, opens the keys in block 130 while the next code passes through the keys, the registers 132, 133 are filled with the code “code 1”. In the adder is the addition of “code 0 + code 0”. At the end of the addition, the sum code from the adder goes to the output of block 75, while being divided by 2. Code No. 1

. Registers 137, 138 carry out storage of codes of 50 ns, the first half of storage of 25 ns occur during the process of adding codes in the adder 136. With the arrival of a second pulse of 20 MHz in trigger 129, it also resets the adder, and the signal from the second output of trigger U _out2 simultaneously: gives code No. 2 “code 0” from register 138 to the output of block 75, from register 132 “code 1” to register 137 and through diodes to adder 136, from register 135 “code 0” to adder, opens keys in block 131 and registers 134, 135 are filled with the code “code 2”. In the adder, the addition is “code 0+ code 1”, then the sum code goes to the output divided by 2: Code No. 3

. With the arrival of the third pulse in the trigger 129, it resets the adder 136, and the signal U _exp3 from the first output of the trigger at the same time: gives code No. 4 “code 1” from register 137 to the output of the block, from register 133 “code 1” to the adder, from register 134 “Code 2” to register 138 and through diodes to the adder, opens the keys in block 130 and the registers 132, 133 are filled with code “code 3”. In the adder, the addition is “code 1 + code 2”, then the sum code goes to the output divided by 2: code No. 5

. With the arrival of the fourth pulse in the trigger 129, it resets the adder, and the signal U _add4 from the second output of the trigger simultaneously: it issues code 6 from code register 138 “code 2” to the output, from code 132 “code 3” to register 137 and through diodes to the adder 136, from register 135 “code 2” to the adder, opens the keys in block 131 and registers 134, 135 are executed by code “code 4”. In the adder 136 is the addition of “code 2+ code 3”, the sum code by dividing it by 2 goes to the output: code number 7

.

. С приходом шестого и следующих импульсов в триггер 129 процессы повторяются. Выходы 0-7 сумматора 136 и выходы 1-8 регистров 137, 138 поразрядно объединены и являются выходами блока 75 /80, 85, 90, 95, 100/. Коды стереопар параллельно и с частотой 40 МГц поступают на информационные входы накопителей 76, 81, 86, 91, 96, 101 кодов кадра.With the arrival of the fifth pulse in the trigger, it resets the adder 136, and the signal U _isd5 from the first output of the trigger at the same time: gives code No. 8 “code 3” from register 137 to the output of the block, from register 133 “code 3” to the adder, from register 134 “ code 4 ”into register 138 and through diodes to the adder, opens the keys in block 130, registers 132, 133 are filled with“ code 5 ”, the adder goes addition“ code 3 + code 4 ”, the sum code divided by 2 goes to the output: code number 9

. With the arrival of the sixth and subsequent pulses in the trigger 129, the processes are repeated. The outputs 0-7 of the adder 136 and the outputs 1-8 of the registers 137, 138 are bitwise combined and are outputs of the block 75/80, 85, 90, 95, 100 /. Codes of stereo pairs in parallel and with a frequency of 40 MHz are fed to the information inputs of drives 76, 81, 86, 91, 96, 101 frame codes.

The operation of the drive codes of the frame, 11, 12.

The code signals in block 76 are supplied to the third inputs of the bits of eight registers 143/12 /. Filling the line registers begins with the opening of the 25 Hz signal of the first key 140 in the first block 139 ₁ registers / 11 /. The key 140 passes pulses U _d 40 MHz input pulse distributor 142, from which clock pulses sequentially supplied to the first / clock / input bits in parallel eight registers 143. By filling the register with the last exit 143/1600/142 block signal U _W closes switch 140 and as the control output signal, opens the key 140 in the next block 139 ₂ registers, registers 143 which are filled with codes of the second line. For a frame period of 40 ms, registers 143 of all blocks 139 _1-1000 registers are sequentially filled with codes. From block 139 ₁₀₀₀ output a control signal is supplied in parallel to the fourth control inputs of all the blocks 139 and opens /fig.11/ therein /fig.12/ second keys 141 which pass one signal U _vyd that synchronously outputs of registers 139 of all the blocks frame codes in the shaper 77 control signals / 6 /. Each drive frame codes has outputs 12.8 × 10 ^6/1600 × 8 × 1000 /, which are connected to as many inputs of a same section 77/82, 87, 92, 97, 102 /, each of which has in its composition 1, 6 × 10 ⁶ converters “code - the number of pulses of radiation”. The outputs of the six control signal shapers 4.8 × 10 ^6/3 × 1.6 × 10 ⁶ / are connected to the same inputs in the LED screen 103. Modern chip manufacturing technologies allow frame code drives and the corresponding control signal shapers to be executed in pairs in one microcircuit, in view of the large number of connections between them and the SD screen, execute these microcircuits on the back side of the SD screen in the same design.

System operation

FEP generates two analog FZI matrices of analog stereo signals, which the ADCs 4-6, 9-11 are converted at a frequency of 20 MHz into 8-bit codes, which enter the corresponding encoders 18-23 / 1 /. Encoders perform compression of the color signal frame streams with a compression ratio of 4. A code generator 24 from the compressed code streams generates a single code stream in which the units of the stereo frame right frame codes are represented by positive half-sine waves, the units of the stereo pair left frame codes are represented by negative half-sine waves. The stereo pair code information is transmitted by the transmitter 33 of the upper side carrier frequency. The receiving side receives radio signals in a single path for receiving and processing codes / Fig. 6/, performs detection, selects horizontal sync pulses and stereo clock pulses, the representation of units in the codes returns to pulses. Decoders restore code flows by 100%, code processing units double the number of samples in rows from 800 to 1600. Frame code accumulators for the frame period concentrate all the codes of the right and left frames. At the end of the period of 40 ms frame codes of the right and left frames. At the end of the 40 ms frame period, the codes of the right frame are sent to blocks 77, 82, 87, the codes of the left frame are sent to blocks 92, 97, 102, which convert the codes of color signals into the number of pulses of the emitted LEDs for the frame period. A 1600 × 1000 video mode is displayed on the LED screen 103. The system lacks both line and frame scans. Two channels reproduce stereo sound. Specifications in table 2. The viewer receives a three-dimensional image using ZD glasses and an IR transmitter 104 located on the housing of the SD screen, or by connecting an IR receiver circuit to the first output of trigger 114/6 /.

The result of the claimed system is to reduce its energy intensity by three times against the prototype and a significant reduction in the number of LEDs in the SD screen.

Used sources

1. Patent No. 2316142 C1, cl. H04N 15/00, bull. 3 from 01/27/08, prototype.

2. Murakhovsky V.I. Computer device. M, 2003, p. 522.

3. Kolesnikov O.V., Shishigin I.V. PC hardware. 5th ed., St. Petersburg, 2004, p. 832-835.

4. Radio transmitting devices. M.S. Shumilin et al. M., 1981, p. 234-235.

5. Digital integrated circuits. Handbook, Minsk, 1991, p. 258, 272, 279, 428, 433.

6. Radio communications, broadcasting and television. Ed. A.D. Fortushenko, M., 1981, p. 146.

7. Barkan V.F., Zhdanov V.K. Amplification and impulse technology. M., 1981, p. 209.

8. “Home computer”. No. 12, 2006, p. 43.

9. “Radio”. No. 9, 2004, p. 47.

table 2 Specifications Values Transmission side Carrier frequency 2025 MHz / option / Stereopair code information transmission one upper side frequency 2160 MHz Occupied band on air with carrier stability 10 ^-7 ± 216 Hz or 432 Hz System Clock 135 MHz Imaging two FDI arrays Code Sampling Rate 20 MHz Frame code stream compression ratio four Transmission side video mode 800 _count × 1000 _lines Receiving side Video code discretization 40 MHz Playable video mode 1600 _cf × 1000 _lines Frame resolution 1.6 × 10 ⁶ pixels Image playback LED screen 3D image perception through ZD glasses with IR receiver

Claims (1)

A stereo television system comprising a transmitting side including a photoelectric converter / photomultiplier, first, second, third analog-to-digital video signal converters, first and second analog-to-digital converters / ADC / sound signal, to the information inputs of which sound signals are connected in series with a sinusoidal generator oscillations and a frequency synthesizer, code generator, first and second self-propelled pulse distributors / SRI /, first and second keys, and a radio signal transmitter containing one a channel including a carrier frequency amplifier connected in series, the input of which is connected to the corresponding output of the frequency synthesizer, an amplitude modulator, the second input of which is connected to the first output of the code generator, and the output amplifier, the first output of the frequency synthesizer is connected to the control inputs of the first to third ADCs of the video signal, the second the output is connected to the corresponding input of the code generator and to the first control inputs of the first and second ADCs of the sound signal, the second inputs of which are combined and connected to the third output of the frequency synthesizer, the fourth output of which is connected to the corresponding input of the code generator, the fifth output of the frequency synthesizer is connected to the third control inputs of the first and second ADCs of the sound signal, the second output of the code generator is connected to the input of the first SRI, the outputs of which are combined and connected to the corresponding information input code generator, the outputs of the second SRI are combined and connected to the corresponding information input of the code generator, to the corresponding information input of which the output of the first ADC signal is connected, the photoelectric converter contains the first / right / and second / left / lenses and first to sixth pre-amplifiers whose outputs are the outputs of the photoelectric converter, the code generator includes three channels, the first and second channels are identical, their outputs are combined, the first channel includes serially connected the first block of AND elements, the first and second OR elements and the first output key, and the first SRI, the second channel includes serially connected the second block of AND elements, the third and fourth OR elements, and the second output key, and the second SRI, the second inputs of the AND element blocks are connected to the SRI outputs of their channel, the outputs of the output keys are combined and are the first output of the code generator, the third channel includes the third and fourth blocks of AND elements, the fifth and sixth OR elements, the output of the fifth element OR connected to the second input of the second OR element in the first channel, the output of the sixth OR element connected to the second input of the fourth OR element in the second channel, and the third and fourth SRI, the outputs of which are connected to the second inputs, respectively the third and fourth blocks of AND elements, includes the first and second keys, and a pulse counter and a decoder connected in series, the first output of which is connected to the first control input of the first key, the second output is connected to the second control input of the first key and to the first control input of the second key, the third the decoder output is the second output of the code generator and is connected to the input of the first SRI of the transmitting side, the output of the first key is connected to the inputs of the first and second SRI in the first and second channels, w output The key is connected to the inputs of the third and fourth SRI of the third channel, the third input of the fourth OR element is the corresponding information input of the code generator, the control inputs of which are: one combined signal inputs of the output keys and a counting input of the pulse counter, the other - the combined signal inputs of the output keys, as follows - the control input of the pulse counter, comprising a receiving side including an antenna, a control unit, a path for receiving and processing video signal codes, the inputs of which are are connected to the antenna, an LED flat-panel screen / LED screen / on the upper part of which there is an IR transmitter, including ZD glasses with an IR receiver on their frame, two sound reproduction channels and a channel for generating control signals, a path for receiving and processing video signal codes contains a series-connected unit for receiving radio signals, the first input of which is connected to the antenna, the second group of inputs is connected to the first group of outputs of the control unit, a radio frequency amplifier and a bipolar amplitude detector, the second and second pulse shapers connected to the first and second outputs of the bipolar amplitude detector, respectively, and the first three channels: a signal channel R containing a signal register R, a code processing unit and a frame code storage, a signal channel G containing a signal register G, a block code processing and frame code storage, signal channel B, containing signal register B, code processing unit and frame code storage, control signal generation channel includes series-connected lowercase sync block pulses / SSI /, frequency synthesizer, first key, pulse counter and decoder, and stereo pair clock extraction unit / SIS /, the first input of the SSI selection block is connected to the output of the first pulse shaper, the first input of the SIS selection block is connected to the output of the second pulse shaper, output the SSI allocation block is connected to the first input of the frequency synthesizer and to the first control input of the first key, the second group of inputs of the frequency synthesizer is connected to the second group of outputs of the control unit, the first output of the frequency synthesizer It is connected to the signal input of the first key and to the control inputs of the signal registers R, G, B, the second output is connected to the control / clock / inputs in the first and second channels of sound reproduction, the third output of the frequency synthesizer is connected to the corresponding control inputs, the fourth output of which connected to the control inputs of the code processing units, the fifth output of the frequency synthesizer is connected to the third input of the radio signal receiving unit, the seventh output is connected in parallel to the third control inputs of the frame code storage devices channels R, G, B, the first output of the decoder is connected to the corresponding control inputs in the first and second channels of sound reproduction, the second output of the decoder is connected to the control input of the pulse counter, to the second control input of the first key and to the corresponding control inputs in the first and second playback channels sound, the information inputs of which are connected to the outputs of the corresponding pulse shapers, the code processing units are identical, each includes a trigger, the input of which is the control input OK, from the first to the sixth registers, the adder and sixteen diodes, the adder control input is connected to the trigger input, the information inputs of the first and second registers are bitwise integrated, the information inputs of the third and fourth registers are bitwise integrated, the first trigger output is connected to the control inputs of the second, third and fifth register, the second trigger output is connected to the control inputs of the first, fourth and sixth registers, the outputs of the first register are connected to the inputs of the fifth register and through diodes to the first inputs I will give the adder to which the outputs of the second register are connected, the outputs of the third register are connected to the inputs of the sixth register and through the diodes to the second inputs of the adder, to which the outputs of the fourth register are connected, the outputs of the fifth and sixth register are bitwise combined, the drive codes of the frame are identical, each includes the corresponding number of register blocks, the information input of each drive of frame codes are bitwise combined 1-8 inputs of register blocks, the first control input of the drive of code codes is the second control input of the first block of registers, the second control input is the combined second control inputs of the register blocks, the third is the combined third control inputs of the register blocks, the first control inputs of the drive codes are combined, the second control inputs are combined, the third control inputs are connected and connected to the seventh output frequency synthesizer, each control output of the previous block of registers is the first control input of the next block of registers, the control output of the last about the register block is connected in parallel to the fourth control inputs of all register blocks, the outputs of each drive code frames are the parallel outputs of all register blocks, the register blocks are identical, each includes the first and second keys, the pulse distributor and eight registers, 1-8 information inputs of the register block bitwise combined third inputs of bits of eight registers, the outputs of all bits of eight registers are parallel outputs of the block of registers, the first control input is the first control input of the first key, the second is the signal input of the second key, the third is the signal input of the first key, the fourth is the first control input of the second key connected to the control output of the last block of registers, the output of the first key is connected to the input of the pulse distributor, the outputs of which are sequentially, starting from from the first, connected to the first control / clock / bit inputs in parallel to eight registers, the last output connected to the second control input of the first key and is the control output of the unit As registers, the output of the second key is connected in parallel to the second control inputs of all the bits of the eight registers and to the second control input of the second key, characterized in that on the transmitting side the first FDI mattress is introduced into the photomultiplier, the photosensitive side of which is located in the focal plane of the first / right / lens , the second FDI matrix, the photosensitive side of which is located in the focal plane of the second / left / lens, the first inputs of both FDI matrices are combined and connected to the output of the first key, the second the passages of the FDI matrices are combined and connected to the output of the second key, the first and third outputs of the first FDI matrix are connected to the inputs of the first and third preamplifiers, the first and third outputs of the second FDI matrix are connected to the inputs of the fourth and sixth preamps, the control inputs of the first and second keys and the input of the second SRI of the transmitting side are combined and connected to the sixth output of the frequency synthesizer, the fifth output / 25 kHz / of which is connected to the signal input of the first key and to the third control To the input of the code generator, the signal input of the second key is connected to the first output of the frequency synthesizer, the fourth, fifth, sixth ADCs of the video signal identical to 1-3 ADCs of the video signal are input on the transmitting side, and from the first to sixth encoders, the information inputs of the first-third ADCs of the video signal are connected to the outputs of the first to third pre-amplifiers in the photomultiplier tubes, the information inputs of the fourth to sixth ADCs of the video signal are connected to the outputs of the fourth to sixth pre-amplifiers photomultiplier tubes, which control the inputs The fourth to sixth ADCs of the video signal are combined and connected to the control inputs of the first to third ADCs of the video signal, the control inputs of the first to sixth encoders and the first control input of the code generator are combined and connected to the second output / 5 MHz / frequency synthesizer, to the fourth output / 135 MHz / which the second control input of the code generator is connected to, the outputs of the first and third encoders are connected to the first information input of which the outputs of the fourth and sixth encoders are connected to the second information input of code encoder, the information inputs of 1-6 encoders are connected to outputs 1-6 of the ADC of the video signal, the output of the first ADC of the sound signal is connected to the third information input of the code generator, the fourth information input of which is connected to the output of the second ADC of the sound signal, the output of the first SRI of the transmitting side is connected to the fifth information input of the code generator, to the sixth information input of which the second SRI of the transmitting side is connected, the first and sixth encoders are identical, each contains sequentially with united register, comparison circuit, pulse counter and decoder, series-connected block of delay elements, key block and buffer storage of frame codes, information inputs of the encoder are bitwise integrated 1-8 register inputs, the first inputs of the comparison circuit and 1-8 inputs of the block of delay elements, the outputs are 1–9 outputs of the buffer accumulator of frame codes, the control input of which is the control input of the encoder, the first output of the comparison circuit is connected to the first control input of the register, to the counting input of the count a pulse sensor and to the second control input of the key block, the second and third outputs of the comparison circuit are combined, the combined output is connected to the second control input of the register, to the first control input of the key block, to the first input of the pulse counter and to the ninth input of the buffer code storage frame, 1- 8 outputs of the pulse counter are connected to the inputs of the decoder and through diodes to 1-8 inputs of the buffer storage of frame codes, the output of the decoder is connected to the second control input of the pulse counter, and through the diode to the first control at the input of the key block, in the code generator, the first to fourth information inputs are the first inputs of the AND elements of the first, second, third and fourth blocks of AND elements, and, to the 1-27th inputs of the first block of AND elements, the outputs of the first - third encoders are connected, 1-27 inputs of the second block of elements And the outputs of the fourth to sixth encoders are connected, the outputs of the first ADC of the sound signal are connected to the inputs of the third block of elements, the outputs of the second ADC of the sound signal are connected to the inputs of the fourth block of elements, to the shaper the third key is input, the output of which is connected to the third input of the second OR element, the signal input of the third key is the fifth information input of the code generator, the sixth information input of which is the third input of the fourth OR element, the third decoder output is connected to the second control input of the second key, the signal inputs of the first , of the second keys and the counting input of the pulse counter combined with them are the first control input of the code generator, the combined signal inputs of the first and second the output keys are the second control input, the control input of the pulse counter is the third control input and the control input of the third key is the fourth control input of the code generator, the first and second receive registers are introduced on the receiving side, each of which contains twenty seven bits, the second three are identical channels of the left frame of stereo pair of R signals _L , G _L ,
B _L , each of which contains in series connected signal register R _L , G _L , B _L , a decoder, a code processing unit, a frame code accumulator, and a control signal generator, in the first three channels of the right frame of the stereo pair of R, G, B signals, a decoder is inserted into each, the inputs of which are connected to the outputs of its channel register, and the outputs of the decoder are connected to the inputs of the block processing of codes, and a driver of control signals, the inputs of which are connected to the outputs of the drive code codes of the frame of its channel, the information input of the first receiving register is connected to the output of the first pulse generator, the information input of the second The receiver register is connected to the output of the second pulse shaper, the first control inputs of the receiving registers are combined and connected to the first output of the frequency synthesizer, their second control inputs are combined and connected to the second output of the frequency synthesizer, 1-9, 10-18, 19-27 bit outputs of the first the receiving register is connected to the inputs 1-9, respectively, of the signal registers R, G, B, the outputs 1-9, 10-18, 19-27 bits of the second receiving register are connected to the inputs 1-9, respectively, of the signal registers R _L , G _L , B _L / left frame of the stereo pair /, the first control inputs of all decoders are combined and connected to the first output of the frequency synthesizer, the second control inputs of all decoders are combined and connected to the fourth output of the frequency synthesizer, to which the control inputs of all code processing blocks are connected, the same control 1-3 the inputs of the drive codes of the frame are combined and connected to the outputs of the SIS allocation block, the SSI allocation block, and to the seventh output of the frequency synthesizer, respectively, the corresponding outputs of the drivers x signals of channels of signals of the right frame of the stereo pair R, G, B, and channels of signals of the left frame of the stereo pair R _L , G _L , B _L combined and connected to the corresponding inputs of the LED screen, which contains the corresponding screen material and the matrix made of emitting elements in it according to the frame resolution number / 1600 × 1000 /, each radiating element includes three LED cells / LED cells /, which contains a white LED luminescence and the corresponding color filter on the radiating side, the control input of each LED is connected to the corresponding output of the corresponding driver of control signals, in the channel the second key and the trigger are entered, the signal input of the second key is connected to the sixth output / 50 Hz / of the frequency synthesizer, and its output is connected to the input of the IR transmitter and to the trigger input, the control input of the second key is connected to the output of the SIS selection block, the first output of the trigger connected to the control inputs of the drivers of control signals in three channels of signals R, G, B of the right frame of the stereo pair and to the input of the IR receiver circuit on the rim of the ZD glasses, the second output of the trigger is connected to the control inputs of the drivers of the control signals of three signal channels R _L , G _L , B _L the left frame of the stereo pair, the information input of the first sound reproducing channel is connected to the output of the first pulse shaper, the information input of the second sound reproducing channel is connected to the output of the second pulse shaper, the decoders are identical, each includes series-connected first register, frame code storage, second register, first key block and a third register, sequentially connected to the second block of keys, subtracting the pulse counter and decoder, from the first to fourth keys, information the decoder moves are 1–9 inputs of bits of the first register, the outputs are 1–8 outputs of the third register, the first control input is the combined first control input of the first register and the signal input of the third key, the second control input is the combined signal inputs of the first, second and fourth keys, the output of the first key is connected to the control input of the third register, the second control input of which and the counting input of the subtracting pulse counter are connected to the output of the second key, the output of the third key It is connected to the control input of the frame code storage device, the fourth key output is connected to the second input control input, the ninth digit of which is connected in parallel to the second control inputs of the first, third and fourth keys, to the first control input of the second key, to the second control input of the first block of keys and to the first control input of the second block of keys, the output of the decoder is connected in parallel to the first control input of the first block of keys, to the second control input of the second block of keys, to The first control inputs of the first, third, fourth keys and the second control input of the second key, the first and second key blocks are inserted into each code processing block, 1-8 inputs of which are bitwise combined and are information inputs of the block, bitwise combined inputs of the first and second registers are connected to the outputs of the first block of keys, the bitwise combined inputs of the third and fourth registers are connected to the outputs of the second block of keys, the control input of the first block of keys is connected to the first output of the trigger, The input of the second block of keys is connected to the second output of the trigger, 1-8 outputs of the fifth and sixth registers and 0-7 outputs of the adder are bitwise combined and are 1-8 outputs of the code processing unit, the control signal conditioners are identical, each includes a pulse generation unit, the input of which is the control input of the driver of control signals, and the code-to-number of radiation pulses converters according to the frame resolution number, each of the code-to-number radiation pulses converters contains a series connection a decoder, 1-8 inputs of which are inputs of the converter, a key block of 255 keys and an output key, a self-propelled pulse distributor / SRI / from the corresponding number of bits, the outputs of which are connected to the signal inputs of the corresponding keys in the key block, and a power source, the output of which connected to the signal input of the output key, the decoder outputs are connected to the first control inputs of the corresponding keys in the key block, the outputs of which are combined, the combined output is connected to the control input of the output to If the output is the output of the converter, the pulse forming unit includes pulse forming circuits according to the number of “code - number of radiation pulses” converters, the output of each pulse forming circuit is connected to the SRI input of its converter, the information inputs of the control signal generator are the inputs of the decoders of all converters, the outputs are the outputs of the output keys of all converters "code - the number of pulses of radiation", the block allocation SSI and block allocation SIS identical, each It includes a pulse counter, a decoder, a NOT element and two diodes, the information input is a counting input of a pulse counter, to which the input of the element NOT is connected, the control input is the combined control input of the pulse counter and the output of the element NOT, which are connected through the first diode to the output of the corresponding driver pulses of the receiving side, the corresponding outputs of the bits of the pulse counter are connected to the corresponding inputs of the decoder, the output of which is the output of the unit and is connected through the second diode to the control input of the pulse counter and to the output of the element NOT, the information input of the block is connected to the output of the corresponding pulse shaper of the receiving side.

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