RU2384010C1 - Stereo television system - Google Patents

Abstract

FIELD: physics; radio.

SUBSTANCE: invention relates to radio communication engineering and can be used in digital television. The result is achieved due to that on the transmitting side a photoelectric converter includes two charge injection devices (CID matrices), first and second lenses are placed side by side and the second lens includes a zoom system, the transmitter has a single channel, on the receiving side there two receiving registers, and the control signal generation channel includes a second switch.

EFFECT: reduction of power consumption of the system by three times compared to the primary standard and simplification of apparatus when creating conditions for perception of a three-dimensional image by an observer without using an infrared transmitter and 3D glasses.

18 dwg, 1 tbl

Description

The invention relates to radio communications technology and can be used for digital broadcasting.

The stereo-television system [1] was adopted as a prototype [1], which contains a photoelectric converter / photovoltaic converter / transmitter on the basis of three piezoelectric deflectors that generates codes for two images of the same space and includes right and left lenses at an appropriate distance from each other, and whose optical axes are parallel , horizontal and vertical scanning units, six photodetectors and six pre-amplifiers, three ADCs of a video signal, two ADCs of a sound signal, a sinusoidal oscillation generator and a frequency synthesizer, three code reader, two self-propelled pulse distributors / SRI /, a trigger and a three-channel radio signal transmitter, on the receiving side containing an antenna, control unit / channel selection /, three paths for receiving and processing video signal codes, LED screen / LED screen / with an IR transmitter on the casing of the SD screen, 3D glasses with an IR receiver on the rim, a channel for generating control signals from the horizontal sync / SSI / frequency synthesizer, frequency synthesizer, key, pulse counter and decoder, and a frame sync. thoron includes first and second channels of sound reproduction. Each path for receiving and processing codes of video signals contains a series-connected block for receiving radio signals, a radio frequency amplifier and a bipolar amplitude detector, the first and second pulse shapers and the channel of one of the color signals R, B, G, each of which contains two registers, a processing / doubling unit / codes, the first block of delays, the adder, the second block of delays, two stores of codes and two blocks for generating control signals. The viewer perceives the image from the screen through 3D glasses. When sequentially reproducing the right and left frames on the SD screen, the 3D glasses' glasses alternately lose transparency, each eye sees its own frame, which gives a stereo effect. Glasses of glasses are made by the technology of LCD cells of the translucent type, used as electronically-controlled filters / shutters / [2, p.558-565]. The code information is transmitted on three radio channels. On the receiving side, three radio signals are received in parallel by three paths, alternately the codes of the right and left frames of stereo pairs, the signal codes of R, B, G are distributed over their channels, in which the number of samples in a line doubles and the number of lines in a frame doubles. The disadvantages of the prototype: the transmission and reception of information through three radio channels determine the high energy consumption of the system, the complexity of obtaining a three-dimensional image, which is used for binocular vision using an IR transmitter and 3D glasses with an IR receiver on the frame that opens the shutters in the glasses 3D glasses . The purpose of the invention is to reduce the energy consumption of the system and hardware simplification when creating conditions for the perception of volumetric images by the viewer.

,The technical results are a three-fold reduction in the energy consumption of the system against the prototype and hardware simplification in creating the conditions for the perception of a three-dimensional image without an IR transmitter and an IR receiver with 3D glasses. The perception of the volumetric image is carried out according to two images of the same space formed by two lenses located nearby without distance between them, but with different image scales each (Fig. 1). The first lens gives the front image of the space being shot, the second lens gives the back image of the same space. The depth between the front and rear images is set by the shooting operator by zooming the second lens. At the shooting location, the operator selects the appropriate image scale with the second lens [3, p.81-82]. In such a shooting, the perception of a three-dimensional image uses the accommodation property of the eye muscles / focusing the eyes on objects of different distances / and the binocular property of the eyes / reducing the direction of views /, since the scale of the images is different [4, p. 94]. As a result, the viewer's brain receives more information for reproducing three-dimensional space. The essence of the claimed television system is that two FDI arrays / devices with charge injection / are introduced into the stereo television system on the transmitting side in the photomultiplier, and the transmitter is single-channel, two receiving registers are introduced on the receiving side, each channel of the signal R, B, G includes one code store and one control signal generation unit, and a second key is inserted into the control signal generation channel. The frame acquisition diagram in figure 1, transmitting to the system side in figure 2, the structure of the digital stream in figure 3, the code generator in figure 4, the spectrum of the amplitude-modulating signal in figure 5, the receiving side in figure 6, bipolar amplitude the detector in Fig. 7, the code processing unit in Fig. 8, the code storage device in Fig. 9, the register block in Figs. 10 and 11, the control signal generation unit in Fig. 12, the SSI signal extraction unit in Fig. 13, an LED cell in Fig. 14, the radiating element of the matrix in Fig. 15, the arrangement of the radiating elements in the LED screen in Fig. 16, time nye system operation diagram in Figure 17, the lens structure 7 in Figure 18. On the transmitting side, the video mode is 1000 × 800 × 50 Hz, 1000 is the number of encoded lines, 800 is the number of encoded samples in a line, 50 Hz is the number, half-frame frequency, 25 Hz is the frame rate. Each frame of two half-frames: front and rear, figure 1, following each other. Frame duration 40 ms, half frame duration 20 ms. Code sampling rate: ƒ _d = 50 Hz × 1000 ×

,

where 2 is the coding of line samples of positive and negative half-sine waves.

The clock frequency on the transmitting side: ƒ _t = 20 MHz × 12 = 240 MHz, where: 12 is the number of bits in the total codes (Fig. 3): 8 - code bits of a single R / G / signal, and 4 bits of signal B.

, период следования разрядов в коде

Несущая частота принимается: ƒ_н=240 МГц×15=3600 МГц, нижняя боковая частота ƒ_нн=3600-240=3360 МГц, верхняя боковая частота ƒ_в=3600+240=3840 МГц. Частота дискретизации сигналов звука принимается ƒ_дзв=50 кГц×2=100 кГц, по два кода звука на строку. Видеорежим на приемной стороне составляет 1000×1600×50 Гц, разрешение кадра на приемной стороне: 1000×1600=1,6×10⁶.Line frequency: ƒ _s = 1000 × 50 Hz = 50 kHz. Codes Period

, the period of the sequence of bits in the code

The carrier frequency is taken: ƒ _n = 240 MHz × 15 = 3600 MHz, the lower side frequency ƒ _nn = 3600-240 = 3360 MHz, the upper side frequency ƒ _in = 3600 + 240 = 3840 MHz. The sampling frequency of the sound signals is accepted ƒ _dzv = 50 kHz × 2 = 100 kHz, two codes of sound per line. The video mode on the receiving side is 1000 × 1600 × 50 Hz, the resolution of the frame on the receiving side is 1000 × 1600 = 1.6 × 10 ⁶ .

The transmitting side includes (Fig. 2) a photoelectric converter 1 / photomultiplier /, which is a sensor of video signals of two half-frames / front and rear /. Each half-frame of three color signals R, B, G. The transmitting side contains the first lens 2, in the focal plane of which is the photosensitive side of the first matrix of the PZI 3 - charge injection device using the Foveon X3 technology from a three-layer CMOS sensor [2, p. 832 , 833] with an optical resolution of 1000 × 800, the first and third outputs of the PED matrix 3 are connected to the inputs of the preamplifiers 4, 5, 6. The photomultiplier includes a second lens 7 located next to lens 2, their optical axes are parallel, in the focal plane of the lens 7 the photosensitive side of the second PZI matrix 8 is located, the first or third outputs of which are connected to the inputs of the preamplifiers 4, 5, 6. Lens 7 is a pancrotic lens with a zoom [5, p. 300], the design of the lens 7 in Fig. 18 [3, p .81, Fig. 11.40], the movement of the positive zoom lens in the lens 7 is performed by the operator before shooting. The transmitting side includes the first 9, second 10, third 11 ADCs of the video signal R, B, G, code generator 12, sine wave generator 13 and frequency synthesizer 14, first 15, second 16, third 17, fourth 18 and fifth 19 keys, trigger 20 , the first self-propelled distributor of 21 pulses / SRI / [their description and operation in 13 p.269], generating a 12-bit horizontal sync pulse code / CSI /, the second SRI 22, generating a 12-bit frame sync pulse code / KS /, fig .3, the first ADC 23 sound signal 3in1, the second ADC 24 sound signal 3v2, the transmitter 25 of the radio signals, containing a series-connected amplifier 26 of a carrier frequency / 3600 MHz /, an amplitude modulator 27 and an output amplifier 28. The ADC 9, 10, 11 of the video signal are identical to the prototype [l, p.5, Fig. 5], the ADC 23, 24 of the sound signal are identical analogue [6, p.6, Fig. 7] and convert the sound signals into 16-bit codes with a sampling of 100 kHz, received at 3 and 4 information inputs of block 12 (figure 2). Code generator 12 (FIG. 4) includes three channels, the first and second are identical. The first channel includes serially connected the first block of 29 AND elements, the first 12 inputs of which are the first information input and receive signals from eight bits of the ADC 9 codes R and signals from 1-4 bits of the ADC 10 codes B, the first 30 and second 31 OR elements and the first the output key 32, and the first SRI 33. The second channel includes a block of AND elements 34 connected in series, the first 12 inputs of which are the second information input of block 12 and receive signals from 8 bits of ADC codes C 11 and signals of codes B from 5-8 bits of ADC 10 third 35 and fourth 36 OR elements and a second output key 37, and a second SRI 38. The third channel includes a third block of 39 AND elements, the first 16 inputs of which are the third information input of block 12 and receive sound codes from the ADC 23, the fifth OR element 40, the output of which is connected to the second input of the second OR element 31, and the third SRI 41 includes the fourth AND element block 42, the first 16 inputs of which are the fourth information input of the block 12, the sixth OR element 43, the output of which is connected to the second input of the fourth OR element 36, and the fourth SRI 44. Block 12 includes The first 45, second 46 and third 47 keys and serially connected pulse counter 48 and decoder 49. SRI 33, 38, 41, 44 are 16-bit. The fifth information input is the signal input of the key 47, the sixth is the third input of the OR element 36. The outputs of block 12 are: the first are the combined outputs of the output keys 32, 37, the second is the third output of the decoder 49. The control inputs are: the first is the combined signal inputs of the keys 45 , 46/20 MHz / and the counting input of the 48-pulse counter, the second - the signal inputs / 240 MHz / output keys 32, 37, the third - the control input / 50 kHz / 48-pulse counter, and the fourth - the control input / 25 Hz / key 47. The first output of the decoder 49 is connected to the first control at entry / U _on / key 45, the second - to a second control input / U ₃ / first switch 45 and the first control input / U _to / _from the second switch 46, a third output is connected to the second control input / U ₃ / key 46 and is the second output of the unit 12. The output of the key 45 is connected to the inputs of the SRI 33, 38, the output of the key 46 is connected to the inputs of the SRI 41, 44. The lens 7 (Fig. 18) contains the lens itself and a zoom 105 of two fixed negative lenses [3, p. 82, Fig. 11.40] and one movable positive lens moving to zoom. The receiving side includes (Fig. 6) an antenna, a control unit 50 / channel selection /, one path for receiving and processing video signal codes, an LED screen 70 / LED screen /, a channel for generating control signals, and two sound reproduction channels 78, 79. The code receiving and processing section receives the codes of the first and second half-frames and includes serially connected radio signal receiving unit 51, radio frequency amplifier 52 and bipolar amplitude detector 53, first 54 and second 55 pulse shapers, first 56 and second 57 receiving registers, each of which contains twelve digits, and three channels of color signals R, B, G, which are identical. The signal channel R includes a series-connected register 58, a code processing unit 59, a code storage unit 60 / half frame /, and a control signal generating unit 61. Signal channel B includes a register 62, a code processing unit 63, a code storage 64, and a control signal generating unit 65. The signal channel G includes a register 66, a code processing unit 67, a code storage 68, and a control signal generating unit 69. The outputs of blocks 61, 65, 69 are connected to the corresponding inputs of the LED screen 70. The operating side of the receiving side determines the channel for generating control signals, including a sequentially connected block 71 for selecting horizontal sync pulses / SSI /, frequency synthesizer 72, first key 73, pulse counter 74 and a decoder 75, a frame synchronization pulse allocation unit / KS / 76 and a second key 77. The receiving side includes identical stereo channels 78 and 79, each of which includes a DAC with a low-pass filter, a power amplifier and a loud voritel. LED display 70 includes radiating elements, respectively, frame resolution 1.6 × 10 ^6/1600 × 1000 / performed in screen material of glass or other suitable screen material. Each emitted element includes three LED cells / LED cells /, each of which emits one of the primary colors R, B, G. Three LED cells represent the emitting element of the matrix (Fig. 15). As light emitting diodes, superbright white LEDs with color filters R, B, G on the emitting side, or PL ED technology LEDs [8, p. 43], or organic light-emitting OL ED diodes [9, p. 7-9] are used. LEDs are executed by the method of microelectronic technology in the screen material. The total light emitting by the LEDs of the radiating element of three colors R, B, G forms the brightness and color tone of one pixel of the screen. The location of the radiating elements in the LED screen in Fig.16. Blocks 59, 63, 67 of the code processing are identical, each includes (Fig. 8) a trigger 80, the input of which is the control input / 20 MHz / block, the first 81 and second 82 key blocks of eight keys each, the first 83, the second 84, the third 85, fourth 86, fifth 88 and sixth 89 registers, adder 87, block 90 delay elements and 16 diodes. Information inputs are bitwise integrated 1-8 inputs of blocks 81, 82 keys. The outputs are the bit-wise combined 1-8 outputs of the registers 88, 89 and block 90. Registers 88 and 89 carry out storage / delay / codes for 50 ns and issue them according to the control signals from the outputs of trigger 80. Block 90 performs the delay of the codes after the adder 87 to the corresponding time, if the adder performs the addition process in less than 25 ns, in this case, block 90 performs a code delay of 2 ns. The code repetition rate from the output of blocks 59, 63, 67 is 40 MHz.

, 255 - разрешение 8-и разрядного кода, 20 мс - длительность полукадра. Выходные сигналы с дешифратора 97 соответственно величине кода открывают ключи в блоке 98, с выходов разрядов СРИ 100 последовательно через 78 мкс появляются импульсы, поступающее на сигнальные входы ключей в блоке 98, проходят открытые ключи и поступают на первый управляющей вход выходного ключа 99. При открытом выходном ключе 99 напряжение питания с источника 101 запитывает свой светодиод в экране на длительность 78 мкс. Импульс с разряда СРИ 100 после прохода своего ключа в блоке 98 поступает на второй управляющий вход /U_з/ ключа и закрывает его /как во втором ключе 93 на фиг.10/. В результате ключи блока 98 после срабатывания переходят опять в закрытое состояние. За период полукадра светодиод запитывается столько раз по 78 мкс, сколько было открыто ключей в блоке 98: чем больше код, тем больше излучений по 78 мкс сделает светодиод СД-экрана. В периоде полукадра импульсы излучений распределяются соответствующим образом, который приводится в таблице.The first output of the trigger 80 U _{vdI is} connected to the control inputs of the registers 84, 85, 88 and to the control input U from the _I block 81, the second output of the trigger 80 U _{vy2 is} connected to the control inputs of the registers 83, 86, 89 and to the control input U from _{2 of the} block 82 keys . The trigger input 80 is connected to the control input of the adder 87 and resets it before each process of adding codes. The outputs of block 81 are connected to the inputs of the registers 83, 84, the outputs of block 82 are connected to the inputs of the registers 85, 86. And the outputs of the register 83 are connected to the inputs of the register 88 and through diodes to the first inputs of the adder 87, to which the outputs of the register 84 are connected. 85 are connected to the inputs of the register 89 and through diodes are connected to the second inputs of the adder 87, to which the outputs of the register 86 are connected. The drives 60, 64, 68 of the codes are identical, each includes (Fig. 9) blocks of registers 91, of which the number of lines in the frame , 1000. Information inputs are bitwise integrated inputs of all the blocks of 91 registers, control inputs are: first - the first control U input _to / 50 Hz / first block 9I _I, the second - the combined second inputs / 50 kHz / block 91, the third - the combined third control inputs / 40 MHz / U _d blocks of 91 registers. Each control output of the previous block of registers is the first control input for each subsequent block of registers. The control output of the last block of 91 ₁₀₀₀ registers is connected in parallel to the fourth control inputs of all blocks of 91 registers. Outputs codes are outputs of all drive units 91 registers, all the outputs 12.8 × 10 ^6/12800 × 1000 /. The blocks 91 of the registers are identical, each includes (FIGS. 10, 11) the first key 92, the second key 93, a pulse distributor 94 and eight registers 95, each containing 1600 bits / by the number of samples in a row /. The information inputs of block 91 are the bitwise combined third inputs of the bits of eight registers 95. The outputs are the parallel outputs of all bits / 1600 / eight registers, total outputs 12800/1600 × 8 /. The control inputs are: the first is the first control input / 50 Hz / of the first key 92, the second is the signal input / U _output 50 kHz / key 93, the third is the signal input / U _d 40 MHz / key 92, the fourth is the first control input of the key 93 The last output of the pulse distributor 94 is the control output of the _I block 91 for the next block _{2 of the 2} registers and is connected to the first control input of the first key 92 (Fig. 11). The output of the first key 92 is connected to the input of the pulse distributor 94, the outputs of which are sequentially, starting from the first, connected to the first / clock / inputs of the bits in parallel to eight registers 95. The output of the key 93 is connected in parallel to the second inputs of the bits of the registers 95 _, and to the second control input of its key 93, passing the first pulse closes the key 93. The outputs of the drive 60 codes are connected to the information inputs of the block 61 of its channel. The purpose of the blocks 61, 33, 39 is to perform the "code - number of radiation pulses" conversion to form the brightness of the LED radiation, which is directly proportional to the value of the color signal code. Each of the blocks 61, 65, 69 comprises a number of transducers on the frame resolution 1.6 × 10 ^6/1600 × 1000/96 and the block (12) pulses reinforcement schemes, containing 1.6 × ¹⁰ June circuits forming coming out on control input signal U _to / 50 Hz / start pulses U _p the duration and amplitude. The code-to-number of radiation pulses converter includes a sequentially connected decoder 97, the inputs of which are 1–8 inputs of the converter, a key block 98 of 255 keys and an output key 99, includes an SRI 100 having 255 bits, and a power supply 101 supplying one LED in the LED screen 70. 255 outputs of the decoder 97 are connected to the first control inputs 255 of the keys in block 98, the outputs of which are combined and connected to the control input U _{from the} output key 99, the signal input of which is connected to the output of the power source 101. The input of each SRI 100 is connected to the output of its pulse forming circuit in block 96. The outputs of 255 bits of each SRI 100 are connected to the signal inputs of their keys in block 98. The information inputs of blocks 61, 65, 69 are the inputs of the decoders 97. The outputs are the outputs of the output keys 99 , total outputs 1.6 × 10 ⁶ , they are connected to the corresponding 1.6 × 10 ⁶ inputs of the LED screen 70. The initial state of the output keys 99 and keys of the block 98 is closed. With the arrival of the signal U _k to the control input / 50 Hz / block 61 of the circuit of block 96, the pulses U _{p are} issued in parallel to the inputs of all SRI 100 and start them up. The duration of the SRI: the passage of the pulse from the first to the 255th digits constitutes the half-frame period, i.e. 20 ms The duration of one emitting pulse of the LED is 78 μs

, 255 - resolution of the 8-bit code, 20 ms - half-frame duration. The output signals from the decoder 97, according to the size of the code, open the keys in block 98, from the outputs of the SRI 100 bits, pulses appear sequentially through 78 μs arriving at the signal inputs of the keys in block 98, public keys go through and go to the first control input of the output key 99. When open the output key 99, the supply voltage from the source 101 powers its LED in the screen for a duration of 78 μs. The pulse from the discharge of the SRI 100 after passing its key in block 98 enters the second control input / U _s / key and closes it / as in the second key 93 in figure 10 /. As a result, the keys of the block 98 after operation go back to the closed state. During the half-frame period, the LED is energized as many times at 78 μs as the number of keys was opened in block 98: the larger the code, the more emissions at 78 μs the LED of the LED screen will make. In the half-frame period, the radiation pulses are appropriately distributed, which is given in the table.

The duration of the radiation with the code 00000001 is 78 μs, and the radiation pulse is performed in the middle of the period, with the code 00000001 there are 255 emissions. The inertia of the operation of the LEDs should be up to 1 μs, which is carried out by superbright LEDs and diodes PLEД and OLEД. Following radiation in the half-frame period at equal time intervals brings the reaction of vision closer to natural in nature and increases the degree of reliability of color reproduction and perception of brightness by human vision. The frame synchronization pulse KS represents the first code in the first line of each first half frame, they go with a frequency of 25 Hz. Pulse KS opens the second key 77/6 /, transmitting pulses of 50 Hz half-frames. The first pulse from key 77 enters the first control input of blocks 60, 64, 68, starts them to accumulate the codes of the first half-frame, which, at the end of the half-frame period of 20 ms, are synchronously and parallel issued to the control signal generation blocks 61, 65, 69, respectively. With the arrival of the second pulse from key 77, the blocks 60, 64, 68 begin the process of accumulating the codes of the second half-frame, and the blocks 61, 65, 69 energize the corresponding LEDs on the screen 70: the image of the first half-frame is displayed on the screen for 20 ms. With the arrival of the third pulse from key 77, the image of the second half frame is displayed on the screen, and blocks 60, 64, 68 accumulate codes of the first half frame of the next frame. Next, the processes are repeated. When observing the image of the first half-frame / front image / to the viewer’s brain, the signals of muscles performing accommodation of the eyes go; when observing the image of the second half-frame / back image of the frame / signals of convergence go to the viewer's brain / the picture has changed / and the signals of accommodation of the eyes. And observation takes place with both eyes at the same time, and the conditions for the viewer to perceive three-dimensional space are fulfilled without using an IR transmitter and 3D glasses with an IR receiver. Blocks 71, 76 are identical, each includes (FIG. 13) a four-digit pulse counter 102 that keeps track of twelve pulses in a row of the SSI / KS / code, element I 103, first diode D1, second diode D2 and element HE104. The information input of the block is the counting input of the counter 102 pulses, the control input of the block 71/76 / is the input of the diode D1 connected to the control input U _{o of the} counter 102. The outputs of the two high-order bits of the counter 102 are connected to the inputs of the element And 103, the output of which is the output of the block 71 / 76 / and through the diode D2 is combined with the output of the element NOT 104, which is connected to the control input of the counter 102. The SSI code from block 54 is fed to the first input of block 71, while there are no pulses from block 55. The KS code arrives at the first input of block 76 from block 55, while there are no pulses from block 54. The output of block 71 is connected to the first input of the frequency synthesizer 72, the output of block 76 is connected to the control input U _{from the} second key 77. When the SSI code arrives at the counting input of the counter 102, it counts the code pulses, the code 1100/12 / is formed in the counter, from the outputs of the two senior bits, the signals enter the element And 103, the output of which follows the pulse SSI / KS /. Pulses of SSI go with a frequency of 50 kHz / KS with a frequency of 25 Hz /. Moreover, from the block 55/54 / to the control input of the block 71/76 / pulses are not received. Starting from the second line code, from block 55/54 / the codes will go to the second input of block 71/76 /. With the arrival of each pulse of the code at the control input of the counter 102, the counter is reset and will not reach the count 12/1100 /. When pulses arrive at the first input of the counter 102, for every zero in the code, the element 104 will nullify the counter 102. When the signal from the block 71/76 / is output, the pulse through the diode D2 enters the control input of the counter 102 and will also reset it. Thus, the circuit blocks 71, 76 do not allow the appearance of false SSI and KS at the output

FEP 1 the first matrix of the FDI 3 generates three color signals of the first / front / half frame. For each of the three layers of the array of FDI 3 from the key 15, pulses of 50 kHz line frequencies for reading the vertical charges of the pixels / input I / are received, the second input of the matrix of the FDI 3 from the key 17 receives 20 MHz pulses for reading the charges horizontally [2, p .832]. The signals from the three layers of the FDI 3 matrix are fed to the preamplifiers 4, 5, 6, from the outputs of which they are fed to the ADCs 9, 10, 11, from the outputs of which the codes of color signals R, B, G with a frequency of 20 MHz are fed to the first and second information inputs of the shaper of 12 codes. The synchronization of reading signals from matrices with the beginning of the first half-frame period is performed by opening the key 19 with a leading edge of the pulse of 25 Hz frame rate. Key 19 passes two pulses of half frames, starting with the first. The first pulse from the key 19 is fed to the input of the trigger 20, which opens the keys 15 and 17 with a signal from the first output. The public keys 15 and 17 transmit 50 kHz and 20 MHz pulses to the first and second inputs of the FDI 3 matrix, which read the pixel charges of the first half frame from it . The second pulse from the second output of trigger 20 is the pulse of the second half-frame and opens the keys 16 and 18 for a duration of 20 ms, transmitting pulses of 50 kHz and 20 MHz to the first and second inputs of the FDI matrix 8, which read the pixel charges of the second half-frame from the matrix. The signals from the three layers of the FDI 8 are fed to the inputs of the preamplifiers 4-6. A frequency synthesizer 14 generates: from the first output pulses U _{d of} sampling codes of 20 MHz, from the second - pulses of half-frame frequencies of 50 Hz, from the third - pulses of sampling of codes of sound 100 kHz, from the fourth - clock pulses of U _t 240 MHz, from the fifth - pulses of frequency lines of 50 kHz, from the sixth - pulses of 25 Hz, from the seventh output - sinusoidal oscillations of the carrier frequency of 3600 MHz with an oscillation stability of 10 ^-7 to the amplifier 26 of the transmitter 25 of the radio signals. With the ADC 9-11, the codes in parallel form arrive at the first and second information inputs of block 12: the first input receives signals from 1-8 bits of the ADC 9 and signals 1-4 bits from the ADC 10, the signals from 1-8 come to the second input bits of the ADC 11 and signals from 5-8 bits of the ADC 10. The first code in the first line of the first half frame is the 12-bit code of the CS (figure 2) to the sixth information input of block 12. Starting from the second line, the first code in each line goes SSI code to the fifth information input of block 12. In the line from the second to 396 samples are the codes of color signals, and in the countdown tach lines 397, 398, 399, 400 are sound codes 3v1 and 3v2 (figure 3). Eight bits of the signal code R and 1-4 bits of the code code of signal B comprise 12 bits of the total code, the unit symbols in it are represented by positive half-sinusoids of the 240 MHz monofrequency. Eight bits of the signal code G and 5-8 bits of code B also make up twelve bits of another summary code, the unit symbols in it are represented by negative half-sine waves of the 240 MHz monofrequency.

The operation of the shaper 12 codes (figure 4).

. Входной ключ 32 в открытом состоянии пропускает одну положительную полусинусоиду 2,0 нс моночастоты 240 МГц, выходной ключ 37 в открытом состоянии пропускает одну отрицательную полусинусоиду 2 нс той же частоты

. Выходной сигнал с первого выхода блока 12 представляет полные и неполные синусоиды частоты 240 МГц со стабильностью 10^-7, являющиеся модулирующим сигналом для несущей частоты в амплитудном модуляторе 27 (фиг.2). Очередность следования кодов видеосигналов и кодов звука в строке определяет счетчик 48 импульсов и дешифратор 49. Счетчик 48 девятиразрядный, ведет счет импульсов 20 МГц с первого по 400-ый. При коде 00000001 импульс с первого выхода дешифратора 49 открывает ключ 45, пропускающей импульсы 20 МГц как сигналы U_п запуска СРИ 33, 38. Со второго по 396 отсчеты строки идут коды видеосигнала, с приходом 396 импульса строки сигнал со второго выхода дешифратора 49 закрывает ключ 45 и открывает ключ 46, пропускающий 397, 398, 399 и 400 импульсы как сигналы U_п в СРИ 41, 44. На входы элементов ИЛИ 32 и 36 поступают по два 16-и разрядных кода звука 3в1, 3в2. С приходом в счетчик 400 импульса строки дешифратор 49 закрывает ключ 46 и поступает как сигнал U_п в СРИ 21, выдающий по нему код ССИ через ключ 47 на третий вход элемента ИЛИ 31. С приходом первого импульса строки в счетчик 48 процессы повторяются. С приходом на вход СРИ 22 импульса 25 Гц и на управляющий вход ключа 47 ключ 47 закрывается передним фронтом импульса, а СРИ 22 выдает код КС на третий вход элемента ИЛИ 36 (фиг.4). С окончанием кода КС ключ 47 открывается. Амплитудный модулятор 27 (фиг.2) состоит из последовательно соединенных кольцевого модулятора и полосового фильтра [7, с.234-235]. Несущая частота 3600 МГц в кольцевом модуляторе подавляется, а полосовой фильтр отфильтровывает нижнюю боковую частоту, верхняя боковая частота 3840 МГц с информацией кодов излучается в эфир и при стабильности ее 10^-7 занимает в эфире полосу ±384 Гц или 768 Гц (фиг.5).Timing diagrams of operation on Fig. Block 12 converts parallel codes into sequential ones and replaces units from pulses with positive and negative half-sinusoids of a single frequency of 240 MHz in them. 16 pulses from the SRI 33, 38 are received at the second inputs of the AND elements of the blocks 29, 34, 16 pulses from the SRI 41 and 44 are received at the second inputs of the AND elements of the blocks 39, 42. From the outputs of the blocks 29, 34, the code pulses are sequentially fed through the OR elements 30 , 31 and 35, 36 to the control inputs of the output keys 32 and 37 and open them for the duration of their duration 3.125 ns

. The input key 32 in the open state transmits one positive half-sine wave of 2.0 ns monofrequency of 240 MHz, the output key 37 in the open state transmits one negative half-sine wave of 2 ns of the same frequency

. The output signal from the first output of block 12 represents a complete and incomplete sinusoid frequency of 240 MHz with a stability of 10 ^-7 , which is a modulating signal for the carrier frequency in the amplitude modulator 27 (Fig.2). The sequence of the following codes of video signals and codes of sound in a line is determined by a counter of 48 pulses and a decoder 49. The counter 48 is nine-digit, it counts pulses of 20 MHz from the first to the 400th. When code 00000001 pulse from the first output of the decoder 49 opens switch 45, transmitting pulses of 20 MHz as signals U _n HRE run 33, 38. From the second to 396 samples the video signal lines are codes 396 with the arrival of the pulse string signal output from the second decoder 49 closes switch 45 and opens the key 46, which transmits 397, 398, 399 and 400 pulses as signals U _p in SRI 41, 44. Two 16-bit sound codes 3v1, 3v2 arrive at the inputs of the OR 32 and 36 elements. With the arrival of a line pulse in the counter 400, the decoder 49 closes the key 46 and acts as a signal U _p in the SRI 21, issuing the ID code through the key 47 to the third input of the OR element 31. With the arrival of the first line pulse in the counter 48, the processes are repeated. With the arrival at the input of the SRI 22 of a pulse of 25 Hz and the control input of the key 47, the key 47 is closed by the leading edge of the pulse, and the SRI 22 issues a code КС to the third input of the OR 36 element (Fig. 4). With the end of the COP code, key 47 opens. Amplitude modulator 27 (figure 2) consists of a series-connected ring modulator and a band-pass filter [7, p.234-235]. The carrier frequency of 3600 MHz in the ring modulator is suppressed, and the band-pass filter filters the lower side frequency, the upper side frequency of 3840 MHz with the code information is broadcast and, if it is 10 ^{-7, it} occupies the band of ± 384 Hz or 768 Hz on the air (Fig. 5) .

At the receiving side, the radio signals are received by the block 51 (Fig.6), which is a channel selector with electronic tuning from the control unit 50 / channel selection /. Block 51 includes an input circuit, a radio frequency amplifier, and a mixer. The radio frequency signal through the communication loop is fed to the mixer, the second input of which / input 3 / s of the frequency synthesizer 72 is supplied with a frequency equal to the carrier frequency and necessary for detecting a single-band signal [l0, p.146]. The signal from the mixer, which is the output signal from block 51, enters the radio frequency amplifier 52, where it is amplified to the required value and fed to the bipolar amplitude detector 53, made according to the scheme in Fig.7. Diode D1 selects the positive envelope of the modulating signal (Fig.17, Fig. 9). The diode D2 from the modulating one selects the envelopes of the positive half-sine waves / symbols of the units of the signal R and 1-4 bits of the signal B /. Diode D3 from the modulating one selects the envelopes of negative half-sinusoids / symbols of units of signal G and 5-8 bits of signal B /. From the first output of block 53, the detected positive half-sine waves of frequency 240 MHz are fed to the input of the first pulse shaper 54, and from the second output of block 53, the detected negative half-sine waves go to the input of the second pulse shaper 55. Shapers 54, 55 pulses are made according to the scheme of an asymmetric trigger with emitter coupling [11, p.209] and form rectangular pulses from harmonically changing signals (Fig. 17, diag. 12, 13). Pulses have one polarity and a duration equal to the pulse width of the codes on the transmitting side. The units in the codes are again represented by the presence of an impulse, the zeros by their absence. The operating procedure of the receiving side is determined by the signals from the channel forming control signals. The decisive role belongs to block 71 allocation SSI. The horizontal sync pulse arrives at the first input of the frequency synthesizer 72 and opens the first key 73. According to the SSI signals in the frequency synthesizer 72, the frequency is adjusted to the frequency of the generator on the transmitting side. The natural frequency of the synthesizer 72 frequencies has a stability of 10 ^-6 . The second inputs of block 72 are connected to the second group of outputs of block 50, the signal from which determines the frequency output from block 72 to the third input of block 51. The frequency synthesizer 72 gives out: 20 MHz code sampling pulses from the first output, and U _t 240 clock pulses from the second output MHz, from the third - sampling pulses of the sound signal 100 kHz, from the fourth - pulses of double sampling of codes 40 MHz, from the fifth - sinusoidal oscillations to the third input of block 51, from the sixth - half-frame pulses of 50 Hz. From block 54, pulses of codes R and pulses of 1-4 bits of codes B are sequentially received in the first receiving register 56 and 12 bits are filled. From block 55, pulses of codes G and pulses of 5-8 bits of codes B are sequentially supplied to the second receiving register 57 and 12 bits are filled. On receiving the signal register 56 U _vyd 20 MHz outputs code R in the register 58, a 1-4 signal level B bits 1-4 of register 62. Register 57 outputs a signal U _vyd signal G code in the register 66 and the 5-8 level signal B - in 5-8 bits of the register 62. From registers 58, 62, 66, the signal codes R, B, G are issued in parallel form in the blocks 59, 63, 67 of the code processing, respectively, to double the number of samples in a row.

Doubling of samples is performed by obtaining intermediate / middle / codes between each passing code and the one following it. The blocks add codes and divide the sum by 2, and the division is performed without time: by dropping the least significant bit of the sum code / as when dividing the decimal number by ten /. The discarding of the least significant bit in the sum code is performed by connecting the outputs 0-7 of the adder 87 (Fig. 8) and 1-8 inputs of the delay block 90:

block outputs 87 0 one 2 3 four 5 6 7 8 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ block 90 inputs one 2 3 four 5 6 7 8

не, т.е. 40 МГц. Процесс сложения двух 8-и разрядных кодов занимает 23 нс, сумматор 87 выполняется из микросхем К555ИМ5 [l2, с 258]. После включения питания в регистрах 83, 84, 85, 86 нули (фиг.8). С приходом первого импульса 20 МГц на вход триггера 80 с его первого выхода сигнал U_выд1 одновременно выдает код "код 0" с регистра 84 на первые входы сумматора 87, с регистра 85 "код 0" в регистр 89 и через диоды на вторые входы сумматора 87 /сигналы выдачи и обнуляют регистры/, сигнал U_от1 открывает ключи в блоке 81 на время прохода кода "код I", который заполняет регистры 83 и 84. В сумматоре идет сложение "код 0 + код 0", код суммы идет на выход в блок 90 задержек, при этом делится на 2. После задержки кода в блоке 90 на 2 нс /25 нс - 23 нс/ код №1 идет на выход блока 90: код №1

. Регистры 88, 89 выполняют хранение /задержку/ на 50 нс, при этом первая половина задержки 25 нс приходится на время сложения 23 нс и плюс время задержки 2 нс в блоке 90. С приходом второго импульса в триггер 80 /он обнуляет сумматор 87/ сигнал со второго выхода триггера U_выд2 одновременно: выдает из регистра 89 код №2 "код 0" на выход, следующий за кодом №1 через 25 нс, с регистра 83 "код 1" в регистр 88 и через диоды в сумматор 87, открывает ключи в блоке 82, регистры 85, 86 заполняются кодом "код 2". В сумматоре идет сложение "код 0+код 1", код суммы идет в блок 90 с делением на 2, и с него на выход идет код №3

. С приходом третьего импульса 20 МГп в триггер 80 обнуляется сумматор 87, а сигнал U_выд3 одновременно: выдает из регистра 88 код 4 "код 1", из регистра 84 "код 1" в сумматор, из регистра 85 "код 2" в регистр 89 и через диоды в сумматор 87, открывает ключи в блоке 81, регистры 83, 84 заполняются кодом "код 3". В сумматоре идет сложение "код 1+код 2" и выдача кода суммы в блок 90 с делением на 2, код №5

идет на выход блока 59. С приходом четвертого импульса в триггер 80 обнуляется сумматор 87, а сигнал U_выд4 выдает одновременно из регистра 89 код №6 "код 2" на выход блока 59, из регистра 86 "код 2" в сумматор, из регистра 83 "код 3" в регистр 88 и через диоды в сумматор 87, открывает ключи в блоке 82, и регистры 85, 86 заполняются кодом "код 4". В сумматоре идет сложение "код 2+код 3", деление на два, и на выход с блока 90 идет код №7

. С приходом пятого импульса в триггер 80 сигнал с первого выхода U_выд5 одновременно выдает из регистра 88 код №8 "код 3" на выход, из регистра 85 "код 4" в регистр 89 и через диоды в сумматор, из регистра 84 "код 3" в сумматор 87, открывает ключи в блоке 81, и регистры 83, 84 заполняются кодом "код 5". В сумматоре идет сложение "код 3+код 4", код суммы идет с делением на 2 в блок 90, с него код №9

идет на выход блока 59. С приходом шестого и последующих импульсов в триггер 80 процессы повторяются. С выходов блоков 59, 63, 37 коды сигналов R, В, G в параллельном виде идут на входы накопителей 60, 64, 68 кодов с частотой 40 МГц. Сигналы с блока 59 поступают на 1-8 входы блока 60. Заполнение кодами строк блоков 91 регистров начинается с открытием сигналом U_к /50 Гц/ с блока 77 (фиг.6) первого ключа 92 в блоке 91₁ (фиг.10). Ключ 92 пропускает импульсы U_д 40 МГц на вход распределителя 94 импульсов, тактовые импульсы U_т с выходов которого последовательно поступают на первые /тактовые/ входы разрядов параллельно восьми регистров 95. По заполнении регистров 95 с последнего выхода блока 94 сигнал закрывает ключ 92 и является выходным управляющим сигналом для следующего блока 91₂ регистров, регистры 95 которого заполняются кодами второй строки. За период 20 мс первого полукадра заполняются кодами регистры 95 всех блоков 91_1-1000. С блока 91₁₀₀₀ выходной управляющий сигнал поступает параллельно на четвертые управляющее входы всех блоков 91 регистров и открывает в них вторые ключи 93, которые пропускают по одному импульсу U_выд, которые синхронно выдают из всех блоков 91 коды полукадра в блок 61 формирования управляющих сигналов. Каждый накопитель 60, 64, 68 кодов имеет 12,8×10⁶ выходов /1600×8×100/, которые подключены к стольким же входам в блоках 61, 65, 69, каждый из которых в своем составе имеет 1,6×10⁶ /1600×1000/ преобразователей "код - число импульсов излучений". Выходы блоков 61, 65, 69 подключены к стольким же входам в СД-экране 70. Современные технологии изготовления микросхем позволяют накопитель кодов и соответствующий ему блок формирования управляющих сигналов выполнять попарно одной микросхемой, которые разместить на тыльном стороне СД-экрана в единой с ним конструкции.Bit 0 means transferring the signal to the high bit when adding codes in the adder. Doubling the samples in a row reduces the code period by half

not i.e. 40 MHz. The process of adding two 8-bit codes takes 23 ns; the adder 87 is made from K555IM5 microcircuits [l2, p. 258]. After turning on the power in the registers 83, 84, 85, 86 zeros (Fig.8). With the arrival of the first 20 MHz pulse to the input of the trigger 80 from its first output, the signal U _vyd1 simultaneously gives the code "code 0" from register 84 to the first inputs of the adder 87, from register 85 "code 0" to the register 89 and through diodes to the second inputs of the adder 87 / issuing signals and reset the registers /, the signal U _{from 1} opens the keys in block 81 for the passage of the code "code I", which fills the registers 83 and 84. In the adder is the addition of "code 0 + code 0", the sum code goes to the output block 90 delays, while divided by 2. After delaying the code in block 90 for 2 ns / 25 ns - 23 ns / code number 1 goes to the output of block 90: code 1

. Registers 88, 89 carry out storage / delay / for 50 ns, while the first half of the delay of 25 ns occurs at the addition time of 23 ns and plus a delay time of 2 ns in block 90. When the second pulse arrives at trigger 80 / it resets the adder 87 / signal from the second output of the trigger U _vyd2 simultaneously: it issues code No. 2 "code 0" from register 89 to the output following code No. 1 after 25 ns, from register 83 "code 1" to register 88 and through diodes to the adder 87, opens the keys in block 82, the registers 85, 86 are filled with the code "code 2". In the adder is the addition of "code 0 + code 1", the sum code goes to block 90 divided by 2, and code No. 3 goes to the output

. With the arrival of the third pulse of 20 megapixels, the adder 87 is reset to trigger 80, and the signal U is _output3 simultaneously: it issues code 4 "code 1" from register 88, from code 84 "code 1" to the adder, from code 85 "code 2" to register 89 and through the diodes to the adder 87, opens the keys in block 81, the registers 83, 84 are filled with the code "code 3". In the adder is the addition of "code 1 + code 2" and the issuance of the sum code in block 90 with a division of 2, code No. 5

goes to the output of block 59. With the arrival of the fourth pulse in the trigger 80, the adder 87 is reset, and the signal U _vy4 simultaneously outputs code No. 6 "code 2" from register 89 to the output of block 59, from register 86 "code 2" to the adder, from register 83 "code 3" to the register 88 and through the diodes to the adder 87, opens the keys in block 82, and the registers 85, 86 are filled with the code "code 4". In the adder is the addition of "code 2 + code 3", division by two, and the output from block 90 is the code number 7

. With the arrival of the fifth pulse in trigger 80, the signal from the first output _Udy5 simultaneously outputs code 8 from code 88 from register 88 to code 8, from code 85 to code 85 from register 85 to code 89 through diodes, from code 84 to code 3 "in the adder 87, opens the keys in block 81, and the registers 83, 84 are filled with the code" code 5 ". In the adder is the addition of "code 3 + code 4", the sum code is divided by 2 into block 90, from it code No. 9

goes to the output of block 59. With the arrival of the sixth and subsequent pulses in trigger 80, the processes are repeated. From the outputs of blocks 59, 63, 37, the signal codes R, B, G in parallel form go to the inputs of the drives 60, 64, 68 codes with a frequency of 40 MHz. The signals from block 59 are received at 1-8 inputs of block 60. Filling with the codes of the lines of the blocks of 91 registers begins with the opening of the first key 92 in block 91 ₁ (figure 10) by the signal U _to / 50 Hz / s of block 77 (Fig. 6). The key 92 passes pulses U _d 40 MHz to the input of the pulse distributor 94, the clock pulses U _t from the outputs of which are sequentially fed to the first / clock / inputs of the bits in parallel with eight registers 95. When the registers 95 are filled from the last output of block 94, the signal closes the key 92 and is the output control signal for the next block 91 ₂ registers, registers 95 of which are filled with codes of the second line. For a period of 20 ms the first half-frame is filled with codes registers 95 of all blocks 91 _1-1000 . From block 91 the output control signal ₁₀₀₀ is applied in parallel to the fourth control inputs of all the registers of blocks 91 and opens them in a second key 93 which passed one pulse U _vyd which synchronously issue of all the blocks 91 in half frame codes unit 61 generating control signals. Each drive 60, 64, 68 codes has 12.8 × 10 ⁶ outputs / 1600 × 8 × 100 /, which are connected to the same inputs in blocks 61, 65, 69, each of which in its composition has 1.6 × 10 ^6/1600 × 1000 / transformers "code - a number of radiation pulses." The outputs of blocks 61, 65, 69 are connected to the same inputs in the LED screen 70. Modern microcircuit manufacturing technologies allow the code storage device and its corresponding control signal generation block to be performed in pairs with one microcircuit, which can be placed on the back side of the LED screen in a single design .

System operation.

The photoelectric converter sequentially forms the first and second half-frames with different image scales of the front and rear image of the frame with lenses 2 and 7. Video signals K, B, G with PZI 3 and 8 are converted by ADCs 9-11 into 8-bit codes with a frequency of 20 MHz. Codes with ADCs 9-11 are received at the first and second information inputs of block 12, which converts parallel codes into serial ones with replacing unit symbols from pulses with positive and negative half-sinusoids of a single frequency of 240 MHz (Fig. 2). The information of the half-frame codes is transmitted by the upper side frequency carrying 3840 MHz to the receiving side. The receiving side (Fig. 6/) receives radio signals in a single path for receiving and processing codes, performs bipolar amplitude detection, selects horizontal and frame sync pulses of SSI, CS, returns the representation of unit symbols in half-sinusoid codes into pulses and distributes the color signal codes R, B, G through their channels, in which doubling of samples is performed in rows from 800 to 1600. The accumulators of 60, 64, 68 codes for the period of the first half-frame concentrate the codes of this half-frame, which at the end of the period are synchronously and parallel issued in the block and 61, 65, 69 generating control signals in which the codes are converted to the corresponding number of pulses energizing the LEDs in the LED screen 70. While the image of the first half frame is displayed on the screen, the code stores focus codes of the second half frame, then the codes of the second half frame are output in blocks 61 , 65, 69, the second half-frame is displayed on the screen, and the code stores concentrate the codes of the next first half-frame. Next, the processes are repeated. The reproduced video mode on the screen is 1600 × 1000 × 50 Hz. The viewer observes each half-frame on the screen with two eyes. When depicting one space with different scales of inertia of vision, the brain of the viewer, receiving information from the muscles of the eyes when they are accommodated on each half frame and information of convergence of the eyes when moving from the front image to the back (figure 1), creates a three-dimensional space. The result of the claimed system is a three-fold reduction in energy intensity against the prototype and the viewer's perception of three-dimensional space without the use of an IR transmitter and 3D glasses with an IR receiver.

Used sources

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3. Handbook amateur photographer. Ed. E.A. Iophisa, M., 1964, pp. 81-82, Fig. 11.40.

4. PC Magazine. Personal computer today. No. 8, August 2008, p. 94.

5. B.N. Begunov, N.P. Zakaznov. Theory of optical systems. M., 1973, p. 300.

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Claims (1)

A stereo television system, comprising a transmitting side, including a photoelectric converter (PEC), including first and second lenses and first and third pre-amplifiers, the outputs of which are PEC outputs, the system includes first-third analog-to-digital (ADC) video signal converters, the information inputs of which are connected to the outputs of the first to third preamplifiers, respectively, a code generator, to the first information input of which the outputs of the first ADC of the video signal are connected, the first and the second ADC of the sound signal, the inputs of which are accompanied by sound signals, the output of the first ADC of the sound signal is connected to the corresponding information input of the code generator, serially connected sinusoidal oscillation generator and frequency synthesizer, the first and second self-propelled pulse distributors (SRI), the outputs of which are connected to the corresponding information inputs of the code generator, from the first to the fifth keys, a trigger and a radio signal transmitter containing a series-connected amplifier carrier frequencies, the amplitude modulator and the output amplifier, the outputs of the frequency synthesizer are connected: the first to the control inputs of the first to third ADCs of the video signal and to the first control input of the code generator, the third to the second control inputs of both ADCs of the audio signal, the fourth to the corresponding control input of the generator codes, the fifth - to the third control inputs of both ADC sound signals and to the corresponding control input of the code generator, the first output of which is connected to the second input of the amplitude modulator a radio signal transmitter, the input of the carrier frequency amplifier of which is connected to the corresponding output of the frequency synthesizer, the control input of the first SRI is connected to the second output of the code generator, the first output of the trigger is connected to the first control inputs of the first and third keys, the second output of the trigger is connected to the first control inputs of the second and fourth keys, the code generator includes three channels, the first and second channels are identical, the first channel includes the first block of AND elements connected in series, the first and second e OR elements and the output key, and the first self-propelled pulse distributor (SRI), the second channel includes the second block of AND elements, the third and fourth OR elements and the output key, and the second SRI, the third channel includes the third block of AND elements, the fifth OR element, the output of which is connected to the second input of the second OR element, and the third SRI, includes the fourth block of AND elements, the sixth OR element, the output of which is connected to the second input of the fourth OR element, and the fourth SRI, the code generator includes the first and second keys and serially connected pulse counter and decoder, the second inputs of the blocks of elements And the first and second channels are connected to the outputs of the SRI of their channel, the second inputs of the third and fourth blocks of elements And are connected respectively to the outputs of the third and fourth SRI, the first output of the code generator are the combined outputs of both output keys, the output of the first key is connected to the inputs of the first and second SRI, the output of the second key is connected to the inputs of the third and fourth SRI, the first output of the decoder is connected to the first mu control input of the first key, the second output of the decoder is connected to the second control input of the first key and to the first control input of the second key, the third output of the decoder is the second output of the code generator and connected to the control input of the first SRI of the transmitting side, the control inputs of the code generator are: the combined signal inputs of the first and second keys and the counting input of the pulse counter, the other - the combined signal inputs of both output keys, the next is the control input (U ₀ ) a pulse counter, and containing the receiving side, including the antenna, a control unit (channel selection), a path for receiving and processing video signal codes, the input of which is connected to the antenna, a channel for generating control signals, an LED screen (LED screen) and two sound reproduction channels, the path for receiving and processing codes of video signals includes a series-connected block for receiving radio signals, the first input of which is connected to the antenna, the second group of inputs is connected to the first group of outputs of the control unit, the radio frequency amplifier and a bipolar amplitude detector, the first and second pulse shapers connected respectively to the first and second outputs of the bipolar amplitude detector, three channels of color signals R, B, G, each of which includes a register and a processing unit, are connected in a path to the reception and processing of video signal codes codes and sequentially connected code storage unit and a control signal generation unit, the outputs of the control signal generation units are connected to the inputs of the LED screen, the formation channel of the control signals includes a series-connected block of horizontal sync pulses (CCI), a frequency synthesizer, a first key, a pulse counter and a decoder, and a block of frame sync pulses (CS), the first input of the CCI block is connected to the output of the first pulse shaper, the first input of the CS block connected to the output of the second pulse shaper, the first control input of the first key is connected to the output of the SSI allocation unit, the signal input of the first key is connected to the first output of the frequency synthesizer, w The second control input of the first key and the control input of the pulse counter are combined and connected to the second output of the decoder, the inputs of the frequency synthesizer are connected: the first is to the output of the SSI allocation block, the second group of inputs is connected to the second group of outputs of the control unit, the outputs of the frequency synthesizer are connected: the first to the control inputs of the code processing units, the second to the third control inputs of the sound reproduction channels, the fourth control inputs of which are connected to the third output of the frequency synthesizer, the fifth output of which connected to the third input of the radio signal receiving unit, the information input of the first sound reproduction channel is connected to the output of the first pulse shaper, the first control inputs of the sound reproduction channels are connected to the first output of the decoder, the second output of which is connected to the second control inputs of both sound reproduction channels, code processing units identical, each includes a trigger, the input of which is the control input of the block, from the first to the sixth registers, the block of delay elements, the adder and w eleven diodes, the control input of the adder is connected to the trigger input, the inputs of the first and second registers are bitwise combined, the inputs of the third and fourth registers are bitwise combined, the outputs of the first register are connected to the inputs of the fifth register and through the diodes to the first inputs of the adder, to which the outputs of the second the register, the outputs of the third register are connected to the inputs of the sixth register and through the diodes to the second inputs of the adder, to which the outputs of the fourth register are connected, the first output of the trigger is connected in parallel to the control inputs of the second, third and fifth registers, the second trigger output is connected in parallel to the control inputs of the first, fourth and sixth registers, the adder outputs are connected to the corresponding inputs of the delay element block, the outputs of which and the outputs of the fifth and sixth registers are bitwise combined and are 1-8 the outputs of the code processing unit, the code stores are identical, each includes register blocks according to the number of lines of the frame, the information inputs are bit-wise combined 1-8 inputs of register blocks, the first The branching input is the first control input of the first block of registers, the second is the combined second control inputs of the register blocks, the third is the combined third control inputs of the register blocks, the first, second, third control inputs of the code drives are combined, each control output of the previous register block is connected to the first control the input of each subsequent block of registers, the control output of the last block of registers is connected in parallel to the fourth control inputs of all blocks registers, the outputs of the code store are the parallel outputs of all register blocks that are connected to the inputs of the control signal generating unit of their channel, the register blocks are identical, each includes the first and second keys, a pulse distributor and eight registers, the information inputs are the bit-wise combined third inputs of the bits of eight registers , the outputs of all the bits of eight registers are the outputs of the register block, the first control input is the first control input of the first key, the second the signal input of the second key, the third is the signal input of the first key, the fourth is the first control input of the second key connected to the control output of the last block of registers, the output of the first key is connected to the input of the pulse distributor, the outputs of which are sequentially, starting from the first, connected to the first control ( clock) inputs of bits in parallel to eight registers, the last output of the pulse distributor is connected to the second control input of the first key and is the control output of the block, registers, output the second key is connected in parallel to the second control inputs of the bits in parallel to eight registers and to the second control input of its key, the control signal generation blocks are identical, the control inputs are combined, the information inputs of each control signal generation block are connected to the outputs of the channel code store, the LED screen consists of screen material and matrix elements according to the number of frame resolutions, each matrix element includes three emitting LED cells, each of which contains a white diode and a color filter of one of the primary colors R, B, G, the screen material according to the number of matrix elements has recesses in which there are LED cells, the inputs of which are connected to the corresponding outputs of the corresponding control signal generating units, characterized in that on the transmitting side the first and second FDI arrays (charge-injection device) are introduced into the photoelectric converter, the photosensitive side of the first matrix is located in the focal plane of the first lens, the photosensitive side of the second The FDI matrix is located in the focal plane of the second lens, the first and third outputs of the same name are combined and connected to the inputs of the first and third preamplifiers, the first and second control inputs of the first FDI matrix are connected to the outputs of the first and third keys, the first and second control inputs of the second matrix FDI is connected to the outputs of the second and fourth keys, the first and second lenses are located nearby and their optical axes are parallel, a second zoom lens is included in the second lens, including the front and rear negative lenses and the movable positive lens located between them, the signal and control inputs of the fifth key are connected respectively to the second and sixth outputs of the frequency synthesizer, the output of the fifth key is connected to the trigger input, the signal inputs of the first and third keys are combined and connected to the fifth output of the frequency synthesizer, the signal inputs of the second and fourth keys are combined and connected to the first output of the frequency synthesizer, to the fourth output of which is connected the second control input of the code generator c, the first and third control inputs of which are connected respectively to the first and fifth outputs of the frequency synthesizer, the first output of which is connected to the first control inputs of both ADC sound signals, the fourth control input of the code generator and the input are connected to the sixth output of the frequency synthesizer (U _P ) the second SRI, the first to twelfth outputs of which are combined and connected to the sixth information input of the code generator, to the fifth information input of which the combined first to twelfth outputs of the first SRI are connected, 1-8 outputs of the first ADC video signal and 1-4 outputs of the second ADC video signal are connected to the first information input of the code generator, to the second information input of which 5-8 outputs of the second ADC of the video signal and 1-8 outputs of the third ADC of the video signal are connected, to the third and fourth information inputs of the encoder of the codes the outputs of the first and second ADCs of the sound signal are connected, and the input of the carrier amplifier of the radio signal transmitter is connected to the seventh output of the frequency synthesizer, the third key is entered into the encoder, the signal input of which is the fifth information input and connected to the output of the first SRI of the transmitting side, the control input the third key is the fourth control input, the output of the third key is connected to the third input of the second OR element, the first twelve inputs of the first block of AND elements are the first information input of the code generator, the second information input of which is the first twelve inputs of the second block of AND elements, the sixth information input of the code generator is the third input of the fourth OR element, the combined signal inputs of the first and second keys and the counting input of the pulse counter are the first control input of the code generator, the second control input of which is the combined signal inputs of both output keys, the control input (Uo) of the pulse counter is the third control input of the code generator, the third output of the decoder is connected to the second control input of the second key of the code generator, the first and second receiving registers are introduced on the receiving side, each of which includes twelve bits, the information input of the first receiving register is connected to the output of the first pulse generator, information the input of the second receiving register is connected to the output of the second pulse shaper, the first and second control inputs of the same name of the first and second receiving reg strovs are combined and connected respectively to the first and second outputs of the frequency synthesizer, the outputs of the first to eighth bits of the first receiving register are connected to the inputs of the first to eighth bits of the channel register of the signal R, the outputs of 9-12 bits of the first receiving register are connected to the inputs of the first to fourth bits of the channel register signal B, the outputs of the first to eighth bits of the second receiving register are connected to the inputs of the first to eighth bits of the channel register signal G, the outputs of 9-12 bits of the second receiving register are connected to the inputs of the fifth to eighth digits of the signal channel B register, the second input of the SSI block is connected to the output of the second pulse shaper, the second input of the KS block is connected to the output of the first pulse shaper, a second key is entered into the channel for generating control signals, the signal input of which is connected to the sixth output frequency synthesizer, the control input is connected to the output of the CS allocation unit, and its output is connected in parallel to the first control inputs of the code storage devices and to the control inputs of the generating units control signals in the signal channels R, B, G, the combined second and combined third control inputs of the three code drives are connected respectively to the fourth output of the frequency synthesizer and to the output of the SSI isolation block, the information input of the second sound reproduction channel is connected to the output of the second pulse shaper, each block generating control signals includes a block of pulse shaping circuits, the input of which is a control input (U _to ) and contains 1.6 · 10 ⁶ pulse generating circuits, and includes converters "code-number of radiation pulses" by the number of frame resolutions 1.6 · 10 ⁶ / 1600 × 1000 /, each “code-number of radiation pulses” converter includes a decryptor connected in series, the inputs of which are converter inputs, a key block of 255 keys and an output key, the output of which is the converter output, includes a self-propelled pulse distributor (SRI) containing 255 bits, the outputs of which are connected to the signal inputs of 255 keys of the key block, and a power source, the output of which is connected to the signal input of the output key, the outputs of the decoder are connected to the first control inputs 255 to key in the key block, control input (U _P ) SRI is connected to the corresponding output in the block of pulse formation circuits, the outputs of 255 keys in the block of keys are combined and connected to the first control input of the output key, the information inputs of the block for generating control signals are the inputs of all decoders of the code-to-number of radiation pulses converters, the block outputs are the outputs of all the output keys connected to the corresponding inputs of the SD screen, the SSI allocation unit and the CS allocation unit are identical, each includes a pulse counter connected in series s and an AND element HE, the first and second diodes, data input is counting pulses of the counter input to which is connected and the input of NOT circuit, a control input is an input of the first diode, the output of which an output of NOT combined and connected to the control input (U _o ) a pulse counter, the outputs of the two high-order bits of which are connected to the inputs of the And element, the output of which is the output of the unit and connected through the second diode to the control input of the pulse counter, the information input of the SSI selection block is connected to the output of the first pulse shaper, its control input is connected to the output of the second pulse shaper, the information input of the KS selection block is connected to the output of the second pulse shaper, and its control input is connected to the output of the first pulse shaper, in each nth code processing unit, the first and second key blocks of eight keys are entered each, the first-eighth inputs of the key blocks are bitwise combined and are the first to eighth information inputs of the code processing block, the first-eighth outputs of the first key block are connected to the bitwise combined first-eighth inputs of the first and second registers, the first to eighth outputs of the second key block are connected to the bitwise combined first to eighth inputs of the third and fourth registers, the control input of the first key block is connected to the first output of the flip-flop, the second control input key unit connected to the second output of the flip-flop.

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