RU2384011C1 - Method of generating three-dimensional image and television system to this end - Google Patents

Abstract

FIELD: physics; radio.

SUBSTANCE: invention relates to radio communication engineering and can be used in digital television. The result is achieved due to that on the transmission side the image scale is changed using both lenses to obtain a third and a fourth image of the same space and formation of codes for the right and left codes of the second stereo pair, and on the receiving side the observer sees a three-dimensional image on four images of frames of two stereo pairs.

EFFECT: reduction of power consumption by three times compared to the primary standard and obtaining twice more amount of information for perception by a three-dimensional space observer.

2 cl, 17 dwg

Description

The invention relates to radio communications technology and can be used for digital broadcasting,

A method for obtaining a three-dimensional image of a television system [1] was adopted as a prototype of the method, using the binocular property of the eyes / convergence principle /, which consists in performing operations on the transmitting side: obtaining two images / right and left / same space with right and left identical lenses in their focal plane , the formation of codes of the right and left frames making up a stereo pair, with the replacement in the symbol codes of units from pulses to positive and negative half-sinusoids of a monofrequency, a multiple of the carrier frequency totem, transmitting successively the codes of the right and left frames of a stereo pair of one of the side frequencies of the carrier frequency of the radio signal transmitter, on the receiving side: receiving radio signals with information of stereo pair codes, bipolar amplitude detection with replacing unit symbols in half-sine wave codes with pulses, distribution of color signal codes R, G, B through its channels, filling in the right-hand frame codes of a stereo pair of three drive codes for the frame and synchronously issuing all the right-frame codes at the end of the frame period for parallel converting each code into a corresponding control signal that feeds the LEDs in the LED screen, filling in the freed up drive codes for the frame with codes of the left frame of the stereo pair and synchronously issuing them for parallel conversion of the codes into control signals that feed the LEDs in the LED screen. The viewer perceives the volumetric image from the screen through 3D glasses, the IR receiver of which, according to the control signals from the IR transmitter located on the screen, darkens the left swelling of the glasses when playing the right frame on the screen, then the right glass of glasses is darkened when playing the left frame on the screen . The disadvantage of the prototype method: to reproduce the volumetric image uses only the binocular property of vision / convergence /, does not use the second property of the eye muscles - accommodation, focusing the eyes on objects of different distances [2; p. 96-97]. The prototype device adopted "Stereotelevision [1], containing on the transmitting side of the photoelectric transducer / PEC / based on three piezoelectric deflectors, forming codes for two images of the same space and including right and left lenses with identical technical characteristics, horizontal and vertical scanning units, photodetectors and six preamplifiers, six keys, three ADCs of a video signal, two ADCs of a sound signal, a sinusoidal oscillator and a frequency synthesizer, three code shapers, two bypass pulse distributor / SRI /, trigger and three-channel transmitter of radio signals, on the receiving side containing an antenna, control unit, three paths for receiving and processing codes of video signals, LED flat-panel screen / LED screen / with IR transmitter on the body of the LED screen, 3D- glasses with an IR receiver on their rim, a channel for generating control signals from a block for extracting horizontal sync pulses / SSI /, a frequency synthesizer, a key, a pulse counter and a decoder, and a block for isolating sync pulses of stereo pairs / SIS /, the receiving side is VK yuchaet first and second channels of sound reproduction. Each path for receiving and processing codes of video signals contains a series-connected block for receiving radio signals, a radio frequency amplifier and a bipolar amplitude detector, first and second pulse shapers, and a channel of one of the color signals R, G, B containing two registers, a code processing unit, and a first delay block, an adder, a second block of delays, two code stores and two blocks for generating control signals. The image from the screen is perceived by the viewer through 3D glasses. When sequentially playing the right and left frames on the SD screen, the 3D glasses glass lose their transparency in turn: each eye sees its own frame, which gives a stereo effect. Glasses of glasses are made using the technology of LCD cells of the translucent type, used as electronically controlled filters / shutters / [3; p. 588-565]. With the arrival of the CMC clock pulse in the IR transmitter, it emits an IR pulse received by the 3D glasses IR receiver, which generates a control signal in the left-glass LCD cells, dimming it for the duration of the frame, then the IR receiver itself issues a second control signal in the LCD -cells of the right glass of glasses, dimming it for the duration of the frame. As a result, each eye sees its frame. The code information is transmitted on three radio channels. On the receiving side, three radio signals are received in three paths in succession, codes of the right and left frames of stereo pairs, signal codes R, G, B are distributed on their channels, in which the number of samples in the lines doubles and the number of lines in the frame doubles. The disadvantages of the prototype: the transmission and reception of information through three radio channels determine the high energy intensity of the system, and when creating a stereo effect for the viewer, only one principle is used - the convergence of vision.

The purpose of the invention is to reduce the energy consumption of the system, and for the formation of the stereo effect is used along with the property of convergence of the eyes and the second property of vision - accommodation of the eyes / focusing the eyes on objects of different distances /.

The technical result is to reduce the power consumption of the system by three times due to the transmission and reception of information on one radio channel and receiving twice as much information for the viewer to perceive three-dimensional space. The inventive method for forming a three-dimensional image uses the binocular property of the eyes and their second property - accommodation of the eyes — and consist in the sequential execution of operations: on the transmitting side, two images of the same space are received by right and left identical lenses with the first image scale set, the formation of the right and left frame codes sequentially the first stereo pair, setting the second image scale synchronously in both lenses, obtaining the third and fourth images then about the space at the second image scale, normalization of the codes of the right and left frames of the second stereo pair with replacing in the character codes of the units in both stereo pairs with positive and negative half-sinusoids of the mono frequency, a multiple of the carrier frequency, and the transmission of information codes sequentially of the first and second stereo pairs of one of the side frequencies of the carrier frequency, on the receiving side, reception of radio signals with information codes of the first and second stereo pairs, bipolar amplitude detection, return of unit symbols in half-sinusoid codes and pulses, the distribution of color signal codes on the R, B, G signal channels, filling in the right stereo frame with the first stereo pair of three frame code drives in the channels and synchronously issuing all the right frame codes to convert each code into the corresponding number of pulses energizing the LEDs on the LED screen , filling in the vacated drives of the frame codes with the codes of the left frame of the first stereo pair, synchronously issuing them for parallel conversion of the codes into the number of pulses energizing the LEDs in the SD screen, filling in the free the existing drives with the codes of the right frame of the second stereopair and synchronously issuing codes of this frame to convert them into the number of pulses energizing the LEDs in the LED screen, filling the vacated drives with the codes of the left frame of the second stereopair and synchronously issuing codes of this frame to convert them into the number of pulses, power LEDs in the LED screen. Stereo images of two stereo pairs create a real perception by the viewer of the depth of the image space.

The essence of the proposed method is that in the method of forming a three-dimensional image, performing on the transmitting side receiving two images of the same space with two lenses, transmitting the information of the codes of the first stereo pair to the receiving side and sequential playback of the right and left frames of the stereo pair on the SD screen, is performed on the transmitting side synchronous zooming with both lenses, obtaining the third and fourth images of the second stereo pair, transmitting information codes of two stereo pairs to the receiving side and playback on the SD screen of the image frames sequentially of the first and second stereo pairs.

The essence of the claimed system is that in the stereo-TV system on the transmitting side two photodetector arrays / charge injection injection device / are introduced into the photoelectric converter / PEC /, and the transmitter is single-channel, two receiving registers are introduced on the receiving side, each channel of the signal is R, B, G includes one drive of code codes and one block for generating control signals; the second key, trigger, and switch are connected in series to the channel for generating control signals. The transmitting side of the system in FIG. 1, the structure of the digital stream in FIG. 2, the code generator in FIG. 3, the lens construction in FIG. 4, the receiving side in FIG. 5, the spectrum of the amplitude-modulated signal in FIG. 6, a bipolar amplitude detector in Fig. 7, the code processing unit in Fig. 8, the frame code storage in Fig. 9, the register block in Figs. 10, 11, the control signal generation unit in Fig. 12, the SSI / SIS / allocation unit in Fig. 13, The LED cell of FIG. 14, the radiating element of the matrix of FIG. 15, the arrangement of the radiating elements in the LED screen of FIG. 16, temporary the operation of the system on Fig. A video mode of 600 × 400 × 100 Hz is formed on the transmitting side, 600 is the number of encoded lines of a frame, 400 is the number of encoded samples in a line, 100 Hz is the frame rate, 50 Hz is the frequency of stereo pairs, 25 Hz is the frequency of pairs of stereo pairs. Each stereo pair of two frames - the right and left frames, following each other.

,Each three-dimensional image of two stereo pairs, four frames. The duration of one frame is 10 ms, the duration of the stereo pair is 20 ms. Code Sampling Rate:

,

where 2 - bipolar coding of line samples: positive and negative half-sine waves.

Clock frequency: f _t = 12 MHz × 12 times = 144 MHz,

12 times - the number of bits in the total code: 8 bits of one code and 4 bits of another code.

, период следования разряда в коде 10,4 нс /

/. Передающая сторона системы включает /фиг.1/ фотоэлектрический преобразователь 1 /ФЭП/, являющимся датчиком видеосигналов двух изображения одного пространства, представляемых двумя стереопарами /четырьмя кадрами/. Каждая стереопара включает правое и левое изображение из трех цветовых сигналов R, В, G и содержит первый объектив 2 /правый/, в фокальнои плоскости которого расположена фоточувствительная сторона первой матрицы ПЗИ - прибора с зарядовом инжекцией по технологии Foveon Х3 из трехслойного КМОП-датчика [3; с.832, 833] с соответствующим оптическим разрешением 600×400 и обеспечивающим 24-битную глубину цвета [3; с.835], первый - третий выходы матрицы ПЗИ 3 подключены к входам предварительных усилителей соответственно 4, 5, 6. ФЭП включает второй /левый/ объектив 7, расположенный на соответствующем расстоянии от правого объектива 2, в фокальной плоскости объектива 7 расположена фоточувствительная сторона второй матрицы П3И 8, первый - третий выходы которой подключены тоже к входам 4, 5, 6 предварительных усилителей. Правый и левый объективы 2, 7 идентичны, являются панкротическими объективами класса трансфокаторов, имеют неподвижную плоскость изображения [4; с.300], которой является фоточувствительная сторона матриц ПЗИ. Конструкция объективов 2 и 7 на фиг.4. Механическое перемещение положительной линзы трансфокатора выполняется [5; с.81, 82, рис.11. 40] введенным в каждый объектив пьезоэлектрическим двигателем /ПЭД/ [6; с.40], перемещающим положительную линзу в в два таксированных положения: первое вперед, второе назад в шаговом режиме работы ПЭД. Двигатель ПЭД размещается в корпусе объектива 2, 7, скорость линейного движения до 0,2

, минимальный шаг линейного движения 0,1 мкм, время пуска и останова 0,001 с, диапазон перемещения 0-350 мм, масса двигателя 10 г, работает в плавном и дискретном изменении скорости, напряжение возбуждения 5 В, мощность до 15 Вт. Передающая сторона включает первый 9, второй 10, третий 11 АЦП видеосигнала R, В, G, формирователь 12 кодов, генератор 13 синусоидальных колебаний и синтезатор 14 частот, первый 15, второй 16, третий 17, четвертый 18, пятый 19 ключи, первый триггер 20, второй триггер 21, первый самоходный распределитель 22 импульсов /СРИ/, формирующий 12-разрядный код строчных синхроимпульсов /ССИ/, второй СРИ 23, формирующий 12-разрядный код синхроимпульса правого кадра первой стереопары /СИС/ в первой строке кадра /фиг.2/, первый АЦП 24 сигнала звука 3 в 1, втором АЦП 25 сигнала 3 в 2, передатчик 26 радиосигналов, включающий последовательно соединенные усилитель 27 несущей частоты /2160 МГц/, амплитудный модулятор 28 и выходной усилитель 29. AЦП 24, 25 выполнены идентично аналогу [8; с.6, рис.7] и преобразуют сигналы звука в 16-разрядные коды, поступающие с дискретизацией 60 кГц с AЦП 24, 25 на третий и четвертый информационные входы блока 12. АЦП видеосигнала 9, 10, 11 выполнены идентично прототипу [1; с.5, 6, рис.5]. Формирователь 12 кодов /фиг.3/ включает три канала. Первый и второй каналы идентичны, первый канал включает последовательно соединенные первый блок 30 элементов И, первые двенадцать входов которого являются первым информационным входом и принимают сигналы с восьми разрядов сигнала R с AЦП 9 и 1-4 сигналы с разрядов 1-4 АЦП 10, первый 31 и второй 32 элементы ИЛИ и первый выходной ключ 33, и первый самоходный растре делитель 34 импульсов /СРИ/. Второй канал включает второй блок 35 элементов И, первые двенадцать входов которого являются вторым информационным входом блока 12 и принимают код 1-8 разрядов сигнала G с АЦП 11 и сигналы В с 5-8 разрядов с АЦП 10, третий 36 и четвертый 37 элементы ИЛИ и второй выходной ключ 38, и второй СРИ 39. Третий канал включает третий блок 40 элементов И, первые 16 входов которого являются третьим информационным входом блока 12 и принимают коды звука с АЦП 24, пятый элемент ИЛИ 41, выход которого подключен к второму входу второго элемента ИЛИ 32, и третий СРИ 42, включает четвертый блок 43 элементов И, первые 16 входов которого являются четвертым информационным входом блока 12 и принимают коды звука с АЦП 25, шестой элемент ИЛИ 44, выход которого подключен к второму входу четвертого элемента ИЛИ 37, и четвертый СРИ 45. Блок 12 включает первый 46, второй 47 и третий 48 ключи и последовательно соединенные счетчик 49 импульсов и дешифратор 50. СРИ 34, 39 являются 12-разрядными, СРИ 42, 45 являются 16-разрядными. Пятым информационным входом является сигнальный вход ключа 48, шестым - третий вход четвертого элемента ИЛИ 37, выходами блока 12 являются: первым - объединенные выходы выходных ключей 33, 38, вторым - третий выход дешифратора 50. Управляющими входами являются: первым - объединенные сигнальные входы первого 46 и второго 47 ключей и счетный вход счетчика 49 импульсов, вторым - сигнальный вход /144 МГц/ выходных ключей 33, 38, третьим - управляющий вход /60 кГц/ счетчика 49 импульсов, четвертым - управляющий вход третьего ключа 48. Первый выход дешифратора 50 подключен к первому управляющему входу ключа 46, второй выход подключен к второму управляющему входу ключа 46 и к первому управляющему входу второго ключа 47, третий выход дешифратора 50 подключен к второму управляющему входу ключа 47 и является вторым выходом формирователя 12 кодов. Вторые входы блоков 30, 35, 40, 43 подключены к выходам СРИ соответственно 34, 39, 42, 45. Выход ключа 46 подключен параллельно к входам СРИ 34, 39, выход второго ключа 47 подключен параллельно к входам СРИ 42, 45. Объективы 2 и 7 идентичны /фиг.4/ каждый содержит сам объектив, трансфокатор 51 из двух неподвижных отрицательных линз [5; с.81-82] и одной подвижной положительной линзы, перемещающейся между ними, и пьезоэлектрический двигатель 52. Приемная сторона включает /фиг.5/ антенну, блок 53 управления /выбора каналов/, один тракт приема и обработки кодов видеосигналов, светодиодный экран 73 /СД-экран/, канал нормирования управляющих сигналов и два канала 86, 87 воспроизведения звука. Тракт приема и обработки кодов производит последовательный прием кодов первой и второй стереопар и включает последовательно соединенные блок 54 приема радиосигналов, усилитель 55 радиочастоты и двухполярный амплитудный детектор 56, первый 57 и второй 58 формирователи импульсов, первый 59 и второй 60 приемные регистры, каждый содержит по 12 разрядов, и три идентичных канала цветовых сигналов R, В, G. Канал сигнала R включает последовательно соединенные регистр 61, блок обработки 62 кодов, накопитель 63 кодов кадра и блок 64 формирования управляющих сигналов. Канал сигнала В включает последовательно соединенные регистр 65, блок 66 обработки кодов, накопитель 67 кодов кадра и блок 68 формирования управляющих сигналов, канал сигнала G включает последовательно соединенные регистр 69, блок 70 обработки кодов, накопитель 71 кодов кадра и блок 72 формирования управляющих сигналов. Выходы блоков 64, 68, 72 подключены к соответствующим входам СД-экрана 73, с расположенным на его корпусе ИК-передатчиком 74. В состав приемной стороны входят 3Д-очки 75 с ИК-приемником 76 на оправе, соединенным кабелем с включателем 77 в позиции 2. Порядок работы приемной стороны определяется каналом формирования управляющих сигналов, которым включает последовательно соединенные блок 78 выделения строчных синхроимпульсов /ССИ/, синтезатор 79 частот, первый ключ 80, счетчик 81 импульсов и дешифратор 82, и блок 83 выделения синхроимпульсов первой стереопары СИС, второй ключ 84 и триггер 85, Приемная сторона содержит идентичные первый 86 и второй 87 каналы воспроизведения звука, каждый из которых включает регистр, цифроаналоговый преобразователь /ЦАП/ с фильтром низкой частоты, усилитель мощности и громкоговоритель. СД-экран 73 представляется соответствующим числом излучающих элементов согласно разрешению кадра /600×800/ 48×10⁴, выполняемых в экранном материале, который может быть стеклом или другим прозрачным материалом. Каждый излучающий элемент включает три светодиодных ячейки /фиг.14/, каждая из которых излучает один из основных цветов R, В, G. Три СД-ячейки представляют излучающий элемент матрицы /фиг.15/. В качестве светодиодов применяются сверхяркие светодиоды белого свечения с цветными светофильтрами /R, В, Q/ или светодиоды технологии СДТ или РLЕД [9; с.43], или органические светоизлучающие OL ЕД-диоды [10; с.7-9]. Светодиоды исполняются методом микроэлектронной технологии в экраном материале. Суммарное излучение светодиодами трех цветов формирует яркость и цветовой тон одного пиксела экрана. Расположение излучающих элементов в СД-экране на фиг.16. Блоки 62, 66, 70 обработки кодов идентичны, каждый включает /фиг.8/ триггер 88, вход которого является управляющим входом /12 МГц/, первый 89 и второй 90 блоки ключей из восьми ключей каждый, первый 91, второй 92, третий 93, четвертый 94 регистры, сумматор 95, пятый 97 и шестой 98 регистры, блок 96 элементов задержек и 16 диодов. Информационными входами являются поразрядно объединенные входы блоков 89, 90 ключей, на них поступают с регистров 61, 65, 69 в параллельном виде коды с частотой 12 МГц. Выходами являются поразрядно объединенные 1-8 выходы регистров 97, 98 и блока 96. Регистры 97, 98 выполняют хранение /задержку/ кодов на 83 нс и выдают их по управляющим сигналам с выходов триггера 88. Блок 96 выполняет задержку кодов после сумматора 95 на 17,5 нс /41,5 нс - 24 нс/. Частота следования кодов с блока 62 /66, 78/ 24 МГц. Первый выход U_выд1 триггера 88 подключен к управляющим входам регистров 92, 93, 97 и к управляющему входу блока 89 ключей /U_от1/, второй выход /U_выд2/ триггера, подключен к управляющим входам регистров 91, 94, 98 и к управляющему входу /U_от2/ блока 90 ключей. Вход триггера 88 подключен к управляющему входу сумматора 95 и обнуляет его перед каждым процессом сложения кодов. Выходы блока 89 подключены к 1-8 входам регистров 91, 92, выходы блока 90 ключей подключены к 1-8 входам регистров 93, 94. Выходы регистра 91 подключены к входам регистра 97 и через диоды к первым входам сумматора 95, к которым подключены и выходы регистра 92. Выходы регистра 93 подключены к входам регистра 98 и через диоды подключены к вторым входам сумматора 95, к которым подключены и выходы регистра 94. Накопители 63, 67, 71 кодов кадра идентичны, каждый включает /фиг.9/ блоки регистров 99, которых по числу строк в кадре 600, информационными входами являются поразрядно объединенные 1-8 входы всех блоков 99 регистров, управляющими входами являются: первым - первый управляющий вход U_к /100 Гц/ первого блока 99₁, вторым - объединенные вторые управляющие входы U_выд 60 кГц блоков 99 регистров, третьим - объединенные третьи управляющие входы U_д /24 МГц/ блоков 99 регистров. Каждый управляющий выход предыдущего блока регистров является первым управляющим входом для каждого последующего блока регистров. Управляющий выход последнего блока 99₆₀₀ регистров подключен параллельно к четвертым управляющим входам всех блоков 99 регистров. Выходами накопителя кодов кадра являются выходы всех блоков регистров, всего выходов 3,84×10⁶ /6400×600/. Блоки 99 регистров идентичны, каждый включает /фиг.10/ первый ключ 100, второй ключ - 101, распределитель 102 импульсов и восемь регистров 103, каждый из которых содержит по 800 разрядов, по числу отсчетов в строке. Информационными входами блока 99 являются поразрядно объединенные третьи входы разрядов восьми регистров 103. Выходами являются параллельные выходы всех /800/ разрядов восьми регистров, всего выходов 6400 /800×8/. Управляющими входами являются: первым - первый управляющий вход /100 Гц/ первого ключа 100, вторым - сигнальный вход U_выд/60 кГц/ ключа 101, третьим - сигнальный вход U_д/24 МГц/ ключа 100, четвертым - первый управляющий вход ключа 101. Последний 800-й выход блока 102 является управляющим выходом блока 99₁ регистров для следующего блока 99₂ и подключен к первому управляющему входу первого ключа 100 /фиг.11/. Выход первого ключа 100 подключен к входу распределителя 102 импульсов, выходы которого последовательно, начиная с первого, подключены к первым /тактовым/ входам разрядов параллельно восьми регистров 103. Выход ключа 101 подключен параллельно к вторым входам разрядов регистров 103 и к второму управляющему входу своего ключа 101, проходящий первый импульс закрывает ключ 101. Выходы накопителя кодов кадра подключены к информационным входам своего блока 64, 68, 72 формирователя управляющих сигналов, назначение которых выполнять преобразование "код - число импульсов излучений" для получения яркости излучения светодиода прямо пропорционально величине кода цветового сигнала. Каждый из блоков 64, 68, 72 включает преобразователи по числу разрешения кадра 48×10⁴/800×600/ и блок 104 /фиг.12/ схем формирования импульсов, содержании 48×10⁴ схем, формирующих из приходящего на управляющий вход сигнала U_к /100 Гц/ импульсы U_п по длительности и амплитуде. Преобразователь "код - число импульсов излучений" включает последовательно соединенные дешифратор 105, входы которого являются 1-8 входами преобразователя, блок 106 ключей из 255 ключей и выходной ключ 107, включает самоходный распределитель 108 импульсов /СРИ/, имеющий 255 разрядов, и источник 109 питания, запитывающий один светодиод в СД-экране 73. 255 выходов дешифратора 105 подключены к первым управляющим входам ключей в блоке 106, выходы которых объединены и подключены к управляющему входу U_от выходного ключа 107, сигнальный вход которого подключен к выходу источника 109 питания. Вход СРИ 108 подключен к выходу своей схемы формирования импульса U_п в блоке 104. 255 выходов разрядов СРИ 108 подключены к сигнальным входам своих ключей /255/ в блоке 106. Информационными входами блока 64 /68, 72/ являются входы всех дешифраторов 105. Выходы выходных ключей 107 являются выходами блоков 64, 68, 72. Всего выходов 48×10, которые подключены к соответствующим входам СД-экрана 73. Исходное состояние выходных ключей 107 и ключей в блоке 106 закрытое. С поступлением сигнала U_к на управляющий вход /100 Гц/ блока 64 схемы блока 104 выдают параллельно импульсы U_п на входы СРИ 108 и запускают их в работу. Длительность работы СРИ: прохождение импульсом от первого до 255 разряда, составляет период кадра 10 мс. Длительность одного излучающего импульса 39 мкс:

, 255 - разрешение восьмиразрядного кода, 10 мс - длительность кадра. Выходные сигналы с дешифратора 105 соответственно величине кода открывают ключи в блоке 106, с выходов разрядов СРИ 108 последовательно через 39 мкс появляются импульсы. которые поступают на сигнальные входы ключей в блоке 106, проходят открытые ключи и поступают на первый управляющий вход выходного ключа 107. При открытом выходном ключе 107 напряжение питания с источника 109 запитывает свой светодиод в экране от каждого импульса с СРИ 108 на 39 мкс. Импульс с разряда СРИ после прохода ключа в блоке 106 поступает на второй управляющий вход этого же ключа и закрывает его /как во втором ключе 101 на фиг.10/, в результате ключи в блоке 106 после срабатывания переходят опять в закрытое состояние. За период кадра светодиод запитывается столько раз по 39 мкс, сколько было открыто ключей в блоке 106: чем больше код, тем больше импульсов излучений выдаст светодиод. А распределение импульсов излучений в периоде кадра соответственно величине кода приводится в таблице. Длительность излучения при коде 00000001 - 39 мкс, при коде 00000010 - 39 мкс × 2, при коде 11111110 - 39 мкс × 254, при коде 11111111 - 39 мкс × 255=10 мс. Инерционность срабатывания светодиодов должна быть менее 1 мкс, что выполняется сверхяркими светодиодами и светодиодами РLЕД и OLЕД.Line frequency: f _s = 600 × 100 Hz = 60 kHz. Code Following Period

, the period of the discharge in the code of 10.4 ns /

/. The transmitting side of the system includes / Fig. 1 / photoelectric converter 1 / photomultiplier /, which is a video signal sensor of two images of the same space, represented by two stereo pairs / four frames /. Each stereo pair includes a right and left image of three color signals R, B, G and contains the first lens 2 / right /, in the focal plane of which is the photosensitive side of the first PZI matrix - a device with charge injection according to the Foveon X3 technology from a three-layer CMOS sensor [ 3; p.832, 833] with the corresponding optical resolution of 600 × 400 and providing 24-bit color depth [3; p. 835], the first and third outputs of the FIR array 3 are connected to the inputs of the preamplifiers 4, 5, 6. The photomultiplier includes a second / left / lens 7 located at an appropriate distance from the right lens 2, the photosensitive side is located in the focal plane of the lens 7 the second matrix P3I 8, the first - the third outputs of which are also connected to the inputs 4, 5, 6 of the preliminary amplifiers. The right and left lenses 2, 7 are identical, are pancrotic lenses of the zoom class, have a fixed image plane [4; p.300], which is the photosensitive side of the FDI matrices. The design of the lenses 2 and 7 in figure 4. Mechanical movement of the positive zoom lens is performed [5; p. 81, 82, fig. 11. 40] a piezoelectric motor / PED / [6; p.40], which moves the positive lens into two taxed positions: the first forward, the second back in the stepped mode of operation of the SEM. The PED engine is located in the lens housing 2, 7, the linear speed of up to 0.2

, the minimum step of linear motion is 0.1 μm, the start and stop times are 0.001 s, the range of movement is 0-350 mm, the mass of the engine is 10 g, it works in a smooth and discrete change in speed, the excitation voltage is 5 V, the power is up to 15 W. The transmitting side includes the first 9, second 10, third 11 ADCs of the video signal R, B, G, code generator 12, sine wave generator 13 and a frequency synthesizer 14, first 15, second 16, third 17, fourth 18, fifth 19 keys, first trigger 20, the second trigger 21, the first self-propelled pulse distributor 22 / SRI /, which generates a 12-bit horizontal sync pulse code / SSI /, the second SRI 23, which generates a 12-bit sync pulse code of the right frame of the first stereo pair / SIS / in the first line of the frame / Fig. 2 /, the first ADC 24 sound signal 3 in 1, the second ADC 25 signal 3 in 2, ne edatchik radio 26 comprising series-connected carrier frequency amplifier 27/2160 MHz / amplitude modulator 28 and output amplifier 29. The D converter 24, 25 are identical analog [8; p. 6, Fig. 7] and convert the sound signals into 16-bit codes arriving at 60 kHz sampling from the ADC 24, 25 to the third and fourth information inputs of block 12. The ADC of the video signal 9, 10, 11 is identical to the prototype [1; p.5, 6, fig. 5]. Shaper 12 codes / 3 / includes three channels. The first and second channels are identical, the first channel includes the first block of 30 AND elements connected in series, the first twelve inputs of which are the first information input and receive signals from eight bits of the signal R with ADC 9 and 1-4 signals from bits 1-4 of the ADC 10, the first 31 and the second 32 elements OR and the first output key 33, and the first self-propelled raster pulse divider 34 / SRI /. The second channel includes a second block of 35 AND elements, the first twelve inputs of which are the second information input of block 12 and receive a code of 1-8 bits of signal G with ADC 11 and signals B with 5-8 bits with ADC 10, third 36 and fourth 37 elements OR and the second output key 38, and the second SRI 39. The third channel includes a third block of 40 AND elements, the first 16 inputs of which are the third information input of block 12 and receive sound codes from the ADC 24, the fifth element OR 41, the output of which is connected to the second input of the second element OR 32, and the third SRI 42, includes the fourth block 43 of AND elements, the first 16 inputs of which are the fourth information input of block 12 and receive sound codes from the ADC 25, the sixth element OR 44, the output of which is connected to the second input of the fourth element OR 37, and the fourth SRI 45. Block 12 includes the first 46 , the second 47 and the third 48 keys and serially connected pulse counter 49 and decoder 50. SRI 34, 39 are 12-bit, SRI 42, 45 are 16-bit. The fifth information input is the signal input of key 48, the sixth is the third input of the fourth OR element 37, the outputs of block 12 are: the first are the combined outputs of the output keys 33, 38, the second is the third output of the decoder 50. The control inputs are: the first are the combined signal inputs of the first 46 and the second 47 keys and the counting input of the counter 49 pulses, the second is the signal input / 144 MHz / output keys 33, 38, the third is the control input / 60 kHz / counter 49 pulses, the fourth is the control input of the third key 48. The first output of the decoder 50 I will connect it is connected to the first control input of the key 46, the second output is connected to the second control input of the key 46 and to the first control input of the second key 47, the third output of the decoder 50 is connected to the second control input of the key 47 and is the second output of the code generator 12. The second inputs of the blocks 30, 35, 40, 43 are connected to the outputs of the SRI 34, 39, 42, 45, respectively. The output of the key 46 is connected in parallel to the inputs of the SRI 34, 39, the output of the second key 47 is connected in parallel to the inputs of the SRI 42, 45. Lenses 2 and 7 are identical (Fig. 4/) each contains the lens itself, a zoom 51 of two fixed negative lenses [5; p.81-82] and one movable positive lens moving between them, and a piezoelectric motor 52. The receiving side includes / Fig. 5 / antenna, control unit / channel selection 53 /, one path for receiving and processing video signal codes, LED screen 73 / LED screen /, the channel normalization of control signals and two channels 86, 87 of sound reproduction. The path for receiving and processing codes sequentially receives codes of the first and second stereo pairs and includes serially connected radio signal receiving unit 54, radio frequency amplifier 55 and bipolar amplitude detector 56, first 57 and second 58 pulse shapers, first 59 and second 60 receiving registers, each containing 12 bits, and three identical color channels R, B, G. The channel of the R signal includes a series-connected register 61, a processing unit 62 codes, a drive 63 frame codes and a block 64 for generating control signals als. The signal channel B includes a series-connected register 65, a code processing unit 66, a frame code storage unit 67 and a control signal generating unit 68, a signal channel G includes a series-connected register 69, a code processing unit 70, a frame code storage unit 71 and a control signal generating unit 72. The outputs of blocks 64, 68, 72 are connected to the corresponding inputs of the LED screen 73, with an IR transmitter 74 located on its case. The receiver side includes 3D glasses 75 with an IR receiver 76 on the frame, connected by a cable to the switch 77 in position 2. The operating side of the receiving side is determined by the channel for generating control signals, which includes a series-connected block 78 of the selection of horizontal sync pulses / SSI /, a frequency synthesizer 79, a first key 80, a pulse counter 81 and a decoder 82, and a block 83 of the sync pulses of the first stereo pairs sys, second key 84 and trigger 85, the receiving side contains identical first 86 and second 87 sound reproduction channels, each of which includes a register, a digital-to-analog converter / DAC / with a low-pass filter, a power amplifier and a loudspeaker. The LED screen 73 is represented by the corresponding number of radiating elements according to the resolution of the frame / 600 × 800/48 × 10 ⁴ performed in the screen material, which may be glass or other transparent material. Each radiating element includes three LED cells (Fig. 14/), each of which emits one of the primary colors R, B, G. Three LED cells represent the radiating element of the matrix (Fig. 15/). As light-emitting diodes, superbright white LEDs with color filters / R, B, Q / or LEDs of SDT or PLED technology are used [9; p. 43], or organic light-emitting OL ED diodes [10; p. 7-9]. LEDs are executed by microelectronic technology in a screen material. The total emission of LEDs in three colors forms the brightness and color tone of one pixel of the screen. The location of the radiating elements in the LED screen in Fig.16. The processing units 62, 66, 70 of the codes are identical, each includes / Fig. 8 / trigger 88, the input of which is the control input / 12 MHz /, the first 89 and second 90 key blocks of eight keys each, the first 91, the second 92, the third 93 , fourth 94 registers, adder 95, fifth 97 and sixth 98 registers, block 96 delay elements and 16 diodes. Information inputs are bitwise combined inputs of blocks 89, 90 of keys; they are received from registers 61, 65, 69 in parallel form codes with a frequency of 12 MHz. The outputs are the bit-wise combined 1–8 outputs of the registers 97, 98 and block 96. Registers 97, 98 carry out storage / delay / codes for 83 ns and issue them according to the control signals from the outputs of trigger 88. Block 96 performs a delay of the codes after the adder 95 to 17 5 ns / 41.5 ns - 24 ns /. Frequency of repetition of codes from the block 62/66, 78/24 MHz. The first output U _{vyd1 of} trigger 88 is connected to the control inputs of the registers 92, 93, 97 and to the control input of the 89 key block / U _from1 /, the second output / U _vyt2 / of the trigger is connected to the control inputs of the registers 91, 94, 98 and to the control input / U _from2 / block of 90 keys. The input of the trigger 88 is connected to the control input of the adder 95 and resets it before each process of adding codes. The outputs of block 89 are connected to 1-8 inputs of registers 91, 92, the outputs of block 90 of keys are connected to 1-8 inputs of registers 93, 94. The outputs of register 91 are connected to the inputs of register 97 and through diodes to the first inputs of adder 95, to which they are connected the outputs of the register 92. The outputs of the register 93 are connected to the inputs of the register 98 and through the diodes are connected to the second inputs of the adder 95, to which the outputs of the register 94 are connected. The drives 63, 67, 71 of the frame codes are identical, each includes / Fig. 9/ register blocks 99 , of which the number of lines in the frame is 600, the information inputs are bit 1-8 of the combined inputs of all registers block 99, control inputs are: first - the first control input _to U / 100 Hz / ₁ of the first block 99, second - the combined second control inputs U _vyd 60 kHz block 99 registers, the third - the combined third control inputs U _d / 24 MHz / blocks 99 registers. Each control output of the previous block of registers is the first control input for each subsequent block of registers. The control output of the last unit ₉₉₆₀₀ registers connected in parallel to the fourth control inputs of all the blocks 99 registers. Outputs the frame code storage registers are outputs of all blocks, all outputs 10 3.84 × ^6/6400 × 600 /. The blocks of 99 registers are identical, each includes / Fig. 10/ the first key 100, the second key 101, a pulse distributor 102 and eight registers 103, each of which contains 800 bits, according to the number of samples in a row. The information inputs of block 99 are the bitwise combined third inputs of the bits of eight registers 103. The outputs are the parallel outputs of all / 800 / bits of eight registers, the total outputs are 6400/800 × 8 /. Control inputs are as follows: first - the first control input / 100Hz / first switch 100, second - signal input U _vyd / 60 kHz / chip 101, the third - the signal input U _d / 24 MHz / chip 100, the fourth - the first control input key 101 The last 800th output of block 102 is the control output of block 99 _{1 of the} registers for the next block 99 ₂ and is connected to the first control input of the first key 100/11 /. The output of the first key 100 is connected to the input of the pulse distributor 102, the outputs of which are sequentially, starting from the first, connected to the first / clock / inputs of the bits in parallel to eight registers 103. The output of the key 101 is connected in parallel to the second inputs of the bits of the registers 103 and to the second control input of its key 101, the passing first pulse closes the key 101. The outputs of the frame code storage device are connected to the information inputs of its control signal generator block 64, 68, 72, the purpose of which is to perform code-to-number conversion of pulses of radiation "for the brightness of the LED light is directly proportional to the magnitude of the color signal code. Each of the blocks 64, 68, 72 comprises a number of transducers on the frame 48 permits × 10 ^4/800 × 600/104 /fig.12/ unit and pulse shaping circuits 48 Content × ¹⁰ April circuits forming of the incoming signal to the control input U _to / 100 Hz / pulses U _p the duration and amplitude. The code-to-number of radiation pulses converter includes a decryptor 105 connected in series, the inputs of which are 1-8 converter inputs, a key block of 255 keys and an output key 107, includes a self-propelled pulser 108 / SRI / having 255 bits, and a source 109 supply that feeds one LED in the LED display 73. The 255 outputs of the decoder 105 are connected to the control inputs of the first key in block 106, whose outputs are combined and connected to the control input U _from an output switch 107, the signal input of which is connected to you ode power source 109. The input of the SRI 108 is connected to the output of its pulse formation circuit U _p in block 104. 255 outputs of the bits of the SRI 108 are connected to the signal inputs of their keys / 255 / in block 106. The information inputs of block 64/68, 72 / are the inputs of all decoders 105. The outputs output keys 107 are outputs of blocks 64, 68, 72. A total of 48 × 10 outputs are connected to the corresponding inputs of the LED screen 73. The initial state of output keys 107 and keys in block 106 is closed. With the arrival of the signal U _k to the control input / 100 Hz / block 64, the circuits of block 104 give out parallel pulses U _p to the inputs of the SRI 108 and start them up. The duration of the SRI: the passage of a pulse from the first to 255 bits, is a frame period of 10 ms. Duration of one emitting pulse 39 μs:

, 255 - resolution of an eight-bit code, 10 ms - frame duration. The output signals from the decoder 105, according to the code size, open the keys in block 106, pulses appear sequentially after 39 μs from the outputs of the SRI 108 discharges. which enter the signal inputs of the keys in block 106, pass the public keys and go to the first control input of the output key 107. When the output key 107 is open, the supply voltage from the source 109 feeds its LED in the screen from each pulse from the SRI 108 to 39 μs. The pulse from the SRI discharge after passing the key in block 106 enters the second control input of the same key and closes it / as in the second key 101 in Fig. 10 /, as a result, the keys in block 106 after switching go back to the closed state. During the frame period, the LED is energized as many times as 39 μs each as the number of keys in block 106 has been opened: the larger the code, the more pulses of radiation the LED will produce. And the distribution of radiation pulses in the period of the frame according to the code value is given in the table. The radiation duration with the code 00000001 is 39 μs, with the code 00000010 - 39 μs × 2, with the code 11111110 - 39 μs × 254, and with the code 11111111 - 39 μs × 255 = 10 ms. The inertia of the operation of the LEDs should be less than 1 μs, which is performed by superbright LEDs and LEDs OLED and OLED.

Decoder Input Code The distribution of radiation pulses in the frame period The number of emissions per frame 00 ... 01 00 ... 128 00 one 00 ... 10 00 ... 88 176 00 2 00 ... 11 00 ... 64 128 192 00 3 00 ... 100 00 ... 51 102 153 204 00 four · • • · • • · • • 11111110 1, 2, 3 ... 254.00 254 11111111 1, 2, 3, ... 254,255 255 0 - absence of a radiation pulse, 1, 2, 3, ... 255 - the sequence numbers of emissions in the frame period.

Following in the frame period, radiation pulses at equal time intervals correspond to the natural perception of light by human vision, which increases the degree of reliability of color reproduction and image brightness for the viewer. The SIS pulse represents the first code in each first line of each right / first / frame of the first stereo pair, i.e. come with a frequency of 25 Hz. The SIS pulse from block 83 (Fig. 5/) opens the second key 84, which transmits 100 Hz frame pulses, and synchronizes playback on the CD-screen of frames starting from the first frame / right / first stereo pair, i.e. The first pulse from the IR transmitter determines the dimming of the left frame in 3D glasses. The first pulse from the key 84 after its opening is fed to the first control input of the blocks 63, 67, 71, starts them to accumulate the codes of the right frame of the first stereo pair, which, at the end of the period of the right frame, are synchronously and parallel issued to the normalization blocks 64, 68, 72 control signals. With the arrival of the second pulse from the key 84, the blocks 63, 67, 71 begin the process of accumulating the codes of the left frame of the first stereo pair, and the blocks 64, 68, 72, having received the codes of the first frame of the first stereo pair, energize the LEDs in the screen 73 according to the code values: the screen is playing right frame of the first stereo pair. When the third pulse from key 84 in the drives 63, 67, 71, the process of accumulating codes of the right frame of the second stereo pair is going on, and the left frame of the first stereo pair is displayed on the screen, with the fourth pulse from key 84, the storage of codes accumulate codes of the left frame of the second stereo pair, and on the CD -the screen displays the right frame of the second stereo pair, then the processes are repeated. The first pulse after opening the key 84 enters the trigger 85, and with the second pulse from the key 84, the signal from the second output of the trigger 85 when the IR transmitter 74 is connected causes the IR radiation from it received by the IR receiver 76. The IR receiver outputs to the LCD cell left glass glasses control signal, causing dimming the left glass glasses. At this time, the viewer observes the image of the right frame with the right eye. When the image of the left frame of the first stereopair arrives on the screen, the IR receiver 76 itself provides the second control signal to the LCD cells of the right glass of glasses, dimming it for 10 ms, the viewer sees the image of the left frame with the left eye. When observing the frames of the first stereopair, signals are transmitted to the brain of the viewer that carry the convergence and accommodation information of the eyes at the first position of the moving lens in the lenses 2, 7 / Fig. 4/, when observing the frames of the second stereopair, signals are transmitted to the brain that carry information from the muscles of the eyes in the second the position of the lens in lenses 2, 7: the more information the brain receives, the more expressed the volume and depth of space perceived by the viewer. In the inventive system, an option is added - obtaining a three-dimensional image without an IR transmitter 74, in this case, the IR receiver of the glasses is connected by a switch 77 to the second position, the process of obtaining a three-dimensional image remains the same.

Blocks 78 allocation SSI and 83 allocation SIS identical, each contains / Fig.13/ four-digit counter 110 pulses, the leading count of 12 pulses in a row code SSI / CIS /, element AND 111, element HE 112, the first diode D1 and the second diode D2. The information input of the block is the counting input of the counter 110, the control input of the block is the input of the diode D1 connected to the control input U _{about the} counter 110, the outputs of its two high-order bits are connected to the inputs of the element And 111, the output of which is the output of the block 78/83 / and through the diode D2 is combined with the output of the element NOT 112, which is connected to the control input U _{о of the} counter 110. The SSI code from block 57 is supplied to the first input of block 78, while there are no pulses from block 58. The SIS code arrives at the first input of block 83 from block 58, while pulses do not come from block 57 to the control input of block 83. The output of block 78 is connected to the first input of the frequency synthesizer 79, the output of block 83 is connected ss to the control input U _{from the} second key 84.

The operation of blocks 78, 83, Fig.13.

With the receipt of the SSI code at the counting input of the counter 110, it counts 12 pulses of the code, the code 1100 is formed in the counter. From the outputs of its two high-order bits, the signals go to the OR element 111, the output of which follows the SSI / SIS / pulse. SSI pulses come with a line frequency of 60 kHz / SIS with a frequency of 25 Hz /. In this case, from block 58 to the control input of block 78/83 / pulses are not received. Starting from the second code of the line, from block 58, the codes will go to the second input of block 78. With the arrival of each pulse of the code at the control input, the counter 110 will be reset to zero and will not be able to reach the count 12/1100 /. Starting from the second code of the line, frame codes from block 57 and to the first input of block 78 will go, and since there will be zeros in the codes, for every zero in the code the element DOES NOT give a signal and reset the counter. When the signal is output from block 78, the pulse through the diode D2 enters the control input of the counter and resets it. Block 83 operates identically. Block diagrams 78, 83 do not allow the appearance of a false signal SSI and SIS at the output. FEP 1 by the first matrix of FDI 3 generates three color video signals of the right frame of the first stereo pair. For each of the three layers of the array of FDI 3 from the key 15, pulses of 60 kHz line frequencies are received for reading the vertical signals of pixels / input 1 /, the second input of the matrix of FDI 3 from the key 17 receives pulses of 12 MHz for reading charges horizontally [3; p.832]. The signals from the three layers of the FDI 3 matrix are fed to the preamplifiers 4, 5, 6, from the outputs of which they are fed to the ADCs 9, 10, 11, from the outputs of which the eight-bit codes of the color signals R, B, G with 12 MHz sampling arrive at 1 and 2 information inputs of the shaper 12 codes. Synchronization of reading signals from matrices with the beginning of the period of the right frame of the first stereo pair is performed by opening the clock pulse of the first stereopair of the SIS 25 Hz key 19. Key 19 passes four frame pulses, always starting from the first frame of the first stereo pair. The first pulse from key 19 is the first / right / frame of the first stereo pair, the second pulse is the pulse of the second / left / frame of the first stereo pair, the third pulse is the pulse of the right / first / frame of the second stereo pair, the fourth is the pulse of the left / second / frame of the second stereo pair. The first pulse from the key 19 is fed to the input of the first trigger 20, which is fed by the signal from the first output to the input of the second trigger 21 and opens the keys 15 and 17. The signal from the first output of the trigger 21 is the first control signal for piezoelectric motors 52 / Fig. 4/ lenses 2 and 7, which, according to the first control signal, move the positive zoom lens to the front position. The public keys 15 and 17 transmit pulses of 60 kHz and 12 MHz to the 1 and 2 inputs of the array of FDI 3, which reads from it the charges of the pixels of the right image. The second pulse about the second output of trigger 20 is the pulse of the left frame of the first stereo pair and opens the keys 16 and 18 for a duration of 10 ms, transmitting respectively 60 kHz and 12 MHz pulses to the first and second inputs of the FDI matrix to read the pixel charges of the left frame of the first stereo pair . The signals from the three layers of the matrix PZI 8 are fed to the inputs of the same amplifiers 4-6. The third frame pulse from the first output of the first trigger 20 enters the second pulse into the trigger 21, the signal from which from the second output is the second control signal for piezoelectric motors 52/4 /, which move the positive zoom lens in both lenses 2 and 7 in back position. The pulse from the first output of flip-flop 20, being the pulse of the right frame of the second stereo pair, opens keys 15, 17 for 10 ms in duration, which transmits pulses of 60 kHz and 12 MHz for reading 3 charges of pixels of the right frame of the second stereo pair from the PZD matrix. The fourth frame pulse from the second output of trigger 20 is the pulse of the left frame of the second stereo pair and opens for 10 ms the keys 16, 18, transmitting pulses of 60 kHz and 12 MHz at 1 and 2 inputs of the array of FDI 8, reading from it the charges of the pixels of the left frame of the second stereo pair. A frequency synthesizer 14 produces: from the first output, pulses U _{d of} sampling 12 MHz in the ADC 9, 10, 11 and to the inputs of the keys 17, 18, from the fourth - clock pulses of 144 MHz to the second control input of block 12, from the third output - pulses of 60 kHz sampling of sound codes to the second control inputs of the ADC 24, 25, from the fifth - pulses of 60 kHz line frequencies to the other inputs of the keys 15, 16 and to the third control inputs of the ADC 24, 25, from the second output frame frequency pulses of 100 Hz to the signal input of the key 19 , from the sixth, 25 Hz pulses to the control input of key 19, in SRI 23 and to the fourth control conductive input unit 12, the seventh - sinusoidal oscillations of the carrier frequency 2160 MHz with a stability of 10 ^-7 to amplifier 27 of the transmitter 26 signals. From the outputs of the ADCs 9, 10, 11, eight-bit codes are sent in parallel to the first and second information inputs of the code generator 12 / Fig. 1/: the signals of 1–8 bits from the ADC 9 and signals from 1–4 bits from the ADC go to the first information input 10, signals of 1–8 bits from the ADC 11 and signals of 5–8 bits from the ADC 10 go to the second information input. The first code in the first line of the right frame of the first stereo pair is the 12-bit SIS code / 2 / for the sixth information input of the block 12, starting from the second line, the first code in each line of all frames is the SSI code with RI 23 to the fifth information input of block 12. In the code stream from the second to the 198th, color signal codes go, and 199 and 200 line samples take one 16-bit 3v1 and 3v2 sound signal code with an ADC 24, 25. An eight-bit signal code R and four signals of 1-4 bits B make up the total code, also the eight-bit code G and signals of 5-8 bits of signal B make up the total code / Fig.2/. At the output of block 12, units in the total code R and B are represented by positive half-sinusoids of the mono-frequency 144 MHz, units in the total code G and B are represented by negative half-sines of the same frequency.

The operation of the shaper 12 codes, Fig.3.

/. Выходной ключ 33 в открытом состоянии пропускает одну положительную полусинусоиду моночастоты 144 МГц на выход, выходной ключ 38 в открытом состоянии пропускает на выход одну отрицательную полусинусоиду той же частоты. Выходы выходных ключей объединены и являются первым выходом блока 12, выходной сигнал с которого представляет полные и неполные синусоиды частоты 144 МГц со стабильностью 10^-7. Очередность следования кодов видеосигналов и кодов звука в строке задают счетчик 49 импульсов и дешифратор 50. Счетчик 49 восьмиразрядный, ведет счет импульсов 12 МГц с первого по 200-й. При коде 00000001 импульс с первого выхода дешифратора 50 открывает ключ 46, который пропускает импульсы 12 МГц как сигнал U_п на входы СРИ 34, 38. Со второго по 198 отсчеты строки идет формирование кодов сигналов R, В, G, с приходом 198 импульса строки сигнал со второго выхода дешифратора 50 закрывает ключ 46 и открывает ключ 47, при этом на вторые входы элементов ИЛИ 32, 37 приходят по одному 16-разрядному коду 3в1 и 3в2, с выхода блока 12 200-м кодом строки идут два кода звука. С приходом в счетчик 49 200-го импульса строки с третьего выхода дешифратора 50 импульс закрывает второй ключ 47, и сигнал этот поступает со второго выхода блока 12 сигналом запуска U_п в СРИ 22, который выдает код ССИ через открытый ключ 48 на третий вход элемента ИЛИ 32. С приходом первого импульса следующей строки в счетчик 49 процессы повторяются. С началом следующей пары двух стереопар на вход СРИ 23 и на управляющий вход ключа 48 /фиг.3/ приходит импульс 25 Гц, который передним фронтом закрывает ключ 48 на длительность кода СИС /83 нс/, и запускает в работу СРИ 23, код СИС с которого поступает на третий вход элемента ИЛИ 32. Закрытый ключ 48 не пропускает код ССИ с СРИ 22, так как он идет первым кодом в каждой строке. С окончанием кода СИС ключ 48 открывается для прохода кодов ССИ. Амплитудный модулятор 28 /фиг.1/ состоит из последовательно соединенных кольцевого модулятора и полосового фильтра [7; с.234]. Несущая частота выдается с седьмого выхода блока 14 и принимается 2160 МГц /144 МГц × 15/. В кольцевом модуляторе подавляется несущая, а полосовой фильтр отфильтровывает нижнюю боковую частоту 2016 МГц /2160-144/, верхняя боковая частота/ 2304 МГц /2160+144/ с информацией кодов излучается в эфир и при стабильности частоты 10^-7 занимает в эфире полосу ±230 Гц или 460 Гц /фиг.6/. На приемной стороне радиосигналы принимаются блоком 54 /фиг.5/, являющимся селектором каналов с электронной настройкой с блока 53 управления /выбор каналов/. Блок 54 содержит входную цепь, усилитель радиочастоты и смеситель. Радиочастотный сигнал через петлю связи поступает на смеситель, на второй вход которого /вход 3/ с синтезатора 79 частот подается частота, равная несущей частоте передатчика и необходимая для детектирования однополосного сигнала [11; с.146].Timing diagrams of the operation of block 12 in Fig.17. Block 12 converts the parallel codes into serial ones and replaces the units from pulses with positive ones in the signal codes R and the first four bits of signal code B and negative half-sine waves in the signal codes G and fifth through eighth bits of codes B. At the first inputs of the block 30 elements And at the same time the complete R code and 1-4 bits of code B are received. The first inputs of the block of 35 elements are received at the same time the signal codes G and 5-8 bits of code B. The 16-bit input goes to the third information input at the first 16 inputs of the AND block 40. signal code 3v 1, the 16-bit signal code 3v2 is received at the fourth information input at the first inputs of the AND elements of block 43. The second inputs of the elements And blocks 30, 35 receive 12 pulses from the SRI, respectively, 34, 39, the second inputs of the elements AND blocks 40, 43 receive sequentially 16 pulses from the SRI 42 and 45. The SRI 34, 39 are started by the signal U _p from the first key 46, SRI 40, 43 with a signal U _p from the second key 47. From the outputs of blocks 30, 35 elements AND pulses of codes R, B, G sequentially arrive through the elements OR 31, 32 and 36, 37 to the control inputs of the output keys 33 and 38 and opens them during its activity 6.9 ns /

/. The output switch 33 in the open state passes one positive half-sine wave of the 144 MHz monofrequency to the output, the output switch 38 in the open state passes one negative half-sine wave of the same frequency to the output. The outputs of the output keys are combined and are the first output of block 12, the output signal from which represents full and incomplete sinusoids of the frequency of 144 MHz with a stability of 10 ^-7 . The sequence of the following codes of video signals and codes of sound in the line is set by the counter 49 pulses and the decoder 50. The counter 49 is eight-bit, counts pulses 12 MHz from the first to the 200th. With the code 00000001, the pulse from the first output of the decoder 50 opens the key 46, which transmits 12 MHz pulses as a signal U _p to the inputs of the SRI 34, 38. From the second to 198 samples of the line, the codes of the signals R, B, G are generated, with the arrival of 198 line pulses the signal from the second output of the decoder 50 closes the key 46 and opens the key 47, while the second inputs of the OR 32, 37 elements come in one 16-bit code 3v1 and 3v2, two sound codes go from the output of block 12 with the 200th row code With the arrival in the counter 49 of the 200th pulse of the line from the third output of the decoder 50, the pulse closes the second key 47, and this signal comes from the second output of block 12 with the start signal U _p in the SRI 22, which issues the SSI code through the public key 48 to the third input of the element OR 32. With the arrival of the first pulse of the next line in counter 49, the processes are repeated. With the beginning of the next pair of two stereo pairs, a 25 Hz pulse arrives at the input of the SRI 23 and at the control input of the key 48 (Fig. 3/), which closes the key 48 with a leading edge for the duration of the SIS code / 83 ns /, and starts the SRI 23, SIS code from which it enters the third input of the OR element 32. The private key 48 does not pass the SSI code from the SRI 22, since it goes with the first code on each line. With the end of the SIS code, the key 48 is opened for the passage of SSI codes. Amplitude modulator 28/1 / consists of a series-connected ring modulator and a band-pass filter [7; p.234]. The carrier frequency is issued from the seventh output of block 14 and is received 2160 MHz / 144 MHz × 15 /. In the ring modulator, the carrier is suppressed, and the band-pass filter filters the lower side frequency 2016 MHz / 2160-144 /, the upper side frequency / 2304 MHz / 2160 + 144 / with the code information is broadcast and, with a frequency stability of 10 ^-7, occupies the band ± 230 Hz or 460 Hz / 6 /. At the receiving side, the radio signals are received by the block 54 / Fig. 5/, which is a channel selector with electronic tuning from the control unit 53 / channel selection /. Block 54 comprises an input circuit, a radio frequency amplifier, and a mixer. The radio frequency signal through the communication loop is fed to the mixer, the second input of which / input 3 / s of the frequency synthesizer 79 is supplied with a frequency equal to the carrier frequency of the transmitter and necessary for the detection of a single-band signal [11; p.146].

The signal from the mixer, which is the output signal of block 54, enters the radio frequency amplifier 55, amplifies to the required value, and enters the bipolar amplitude detector 56, made according to the scheme in Fig. 7. Diode D1 selects the positive envelope of the modulating signal (Fig. 17, Fig. 9). The diode D2 from the modulating one selects the envelopes of the positive half-sine waves / symbols of the signal units R and 1-4 bits of the signal B /. Diode 3 from the modulating one selects the envelopes of negative half-sinusoids / unit symbols in signal codes G and 5-8 bits of signal B /. From the first output of block 56, the detected positive half-sine waves of 144 MHz frequency are fed to the input of the first pulse shaper 57, and from the second output of block 56, the detected negative half-sine waves go to the input of the second pulse shaper 58. Shapers 57, 58 pulses are made according to the scheme of an asymmetric trigger with emitter coupling [12; p.209] and form rectangular pulses from harmonically changing signals, Fig.17, Diagram 12, 13. The pulses have one polarity and a duration equal to the pulse duration of the codes on the transmitting side. Units in the codes are represented by the presence of pulses, zeros by their absence. The order of operation of the receiving side is determined by the signals from the channel for generating control signals, the decisive role belongs to block 78 allocation SSI. An SSI horizontal sync pulse from block 78 goes to the first input of the frequency synthesizer 79 and opens the key 80. The frequency tuning is performed according to the SSI signals in the frequency synthesizer 79, the inherent frequency stability in block 79 is 10 ^-6 . The second inputs of block 79 are connected to the second group of outputs of block 53, the signal from which determines the frequency output from block 79 to the third input of block 54. A frequency synthesizer 79 produces: 12 MHz code sampling pulses from the first output, 144 MHz clock pulses from the second output, from the third, sampling pulses of 60 kHz sound signals, from the fourth, double sampling pulses of 24 MHz codes, from the fifth, sinusoidal oscillations of the corresponding frequency to the third input of block 54, and from the sixth, frame Hz pulses of 100 Hz. From block 57, pulses of codes R and pulses of 1-4 bits of code B are sequentially received in the first receiving register 59 and 12 bits are filled. From block 58, the pulses of code G and the pulses of 5-8 bits of code B are sequentially fed to the second receiving register 60 and filled with 12 bits. On receiving the signal register 59 U _vyd 12 MHz signal R produces code in the register 61 and signal level 1-4 B 1-4 level register 65. Register 60 outputs a signal U _vyd signal G code in the register 69 and the code bits 5-8 In 5-8 bits of the register 65. From the registers 61, 65, 69, the codes R, B, G are issued in parallel form in their code processing units 62, 66, 70 to double the number of samples in rows. Doubling of samples is performed by obtaining intermediate / middle / codes between each passing code and the one following it. Blocks add codes and divide the sum code in half, and the division is done without time: by dropping the least significant bit of the sum code / as when dividing the decimal number by ten /. The discarding of the least significant bit in the sum code is performed by connecting the outputs of the adder 0-7 / Fig. 8/95 and inputs 1-8 of the block 96 delays:

block outputs 95 0 one 2 3 four 5 6 7 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ block 96 inputs one 2 3 four 5 6 7 8

/, т.е. 24 МГц.Bit 0 means transferring the signal to the high bit when adding codes in the adder. Doubling the samples in the row reduces the code period by half, equal to 41.5 ns /

/, i.e. 24 MHz

. Регистры 97,98 выполняют хранение /задержку/ на 83 нс, но при этом первая половина времени хранения 41,5 нс приходится на время сложения 25 нс плюс время задержки в блоке 96 /25+16,5=41,5 нс/.The process of adding two eight-bit codes takes 25 ns, the adder 95 is made of K555IM6 microcircuits [13; p.258]. After turning on the power in the registers 91-94, 97, 98 zeros / Fig.8/. With the arrival of the first 12 MHz pulse to the input of trigger 88 from its first output, the signal U _vyd1 simultaneously: gives the code "code 0" from register 92 to the first inputs of the adder 95, from register 93 "code 0" to register 98 and through diodes to the second inputs adder 95 / issuing signals and reset the registers /, signal U _{from 1} opens the keys in block 89 for the passage of the code, and "code 1" fills the registers 91, 92. In the adder, the addition is "code 0 + code 0", the sum code is the output to block 96 delays, while this is divided by 2. After the code is delayed in block 96 by 16.5 ns / 41.5-25 /, code No. 1 goes to the output of block 96: code No. 1

. Registers 97.98 carry out storage / delay / for 83 ns, but in this case the first half of the storage time 41.5 ns falls on the addition time 25 ns plus the delay time in the block 96/25 + 16.5 = 41.5 ns /.

.With the arrival of the second pulse in trigger 88 / it resets the adder 95 / signal from the second output of trigger U _vyd2 at the same time: gives code No. 2 "code 0" to the output from register 98, it follows code No. 1 after 41.5 ns, from the register 91 "code 1" to register 97 and through diodes to the adder 95, from register 94 "code 0" to the adder, opens the keys in block 90, registers 93, 94 are filled with the code "code 2". In the adder is the addition of "code 0 + code 1", the sum code goes to block 96 divided by 2, and code No. 3 goes to the output of block 62 from it

.

идет на выход блока 62.With the arrival of the third pulse in the trigger 88, the adder 95 is reset, and the signal U _vyd3 simultaneously: it issues code No. 4 “code 1” from register 97, code “code 1” from register 92, and “code 2” from register 93 “into code 98” and through the diodes to the adder 95, opens the keys in block 89, and the registers 91, 92 are filled with the code "code 3". In the adder is the addition of "code 1 + code 2" and the issuance of the sum code in block 96 with a division of 2, code No. 5

goes to the output of block 62.

.With the arrival of the fourth pulse in the trigger 88, the adder 95 is reset, the signal U _vy4 from the second output of the trigger at the same time: generates code 6 "code 2" from register 98, followed by code 5 after 41.5 ns, from register 94 "code 2" into the adder 95, from the register 91 "code 3" to the register 97 and through the diodes to the adder, opens the keys in block 89, and the registers 93, 94 are filled with the code "code 4". In the adder is the addition of "code 2 + code 3", division by 2, and the output from block 96 is the code number 7

.

идет на выход блока 62. С приходом шестого и следующих импульсов в триггер 88 процессы повторяются. С выходов блоков 62, 66, 76 коды сигналов R, В, G в параллельном виде идут на входы накопителей 63, 67, 71 кодов кадра с частотой 24 МГц.With the arrival of the 5th pulse in the trigger 88, the adder 95 is reset, and the signal U _vyd5 from the first output of the trigger at the same time: issues code No. 8 "code 3" from register 97, from code 93 "register 4" to register 98 and through diodes to the adder , from register 92 "code 3" to the adder, opens the keys in block 89, and registers 91, 92 are filled with code "code 5". In the adder 95 is the addition, "code 3 + code 4", the sum code is divided by two into block 96, with it code number 9

goes to the output of block 62. With the arrival of the sixth and subsequent pulses in trigger 88, the processes are repeated. From the outputs of blocks 62, 66, 76, the signal codes R, B, G in parallel form go to the inputs of the drives 63, 67, 71 frame codes with a frequency of 24 MHz.

The operation of the drive codes of the frame, Fig.9, 10.

The signals from block 62 are received at 1-8 inputs of block 63. Filling with the codes of the lines of blocks of 99 registers begins with the opening of the first key 100 in block 99 _{1 /} Fig. 10/ by the signal U _to / 100 Hz / from block 84 / Fig. ₅ /. The key 100 passes pulses U _d 24 MHz to the input of the pulse distributor 102, the clock pulses from the outputs of which are sequentially fed to the first / clock / bit inputs in parallel of eight registers 103. When the registers 103 are filled from the last output of block 102, the signal closes the key 100 and is the output control a signal for the next block 99 ₂ registers, registers 103 which are filled with codes of the second line. For a frame period of 10 ms, the registers 103 of all blocks 99 _1-600 are filled with codes. C block _99,600 output control signal 1 is supplied in parallel to the fourth control input of unit 99 registers and opens therein the second key 101, which is passed by one pulse U _vyd that synchronously outputs of all the blocks 99 of the frame codes to a block 64 forming the control signals. Each drive 63, 67, 71 frame codes has 3.84 × 10 ⁶ outputs / 800 × 8 × 600 /, which are connected to the same inputs in blocks 64, 68, 72, each of which has 48 × 10 ⁴ converters "code - the number of pulses of radiation". The outputs of blocks 64, 68, 72 are connected to the same inputs in the LED screen 73. Modern microcircuit manufacturing technologies allow the frame code storage and the corresponding control signal generation block to be executed in pairs with one microcircuit and, due to the large number of connections between them and the LED screen , run these chips on the back of the screen in a single design.

System operation.

FEP normalizes sequentially the right and left frames of the first stereo pair at the first image scale [5; p.82] with lenses 2 and 7, the right and left frames of the second stereo pair at the second image scale with lenses 2 and 7. Signals R, B, G with PZI 3 and 8 are converted by the ADCs of 9-11 video signals with a frequency of 12 MHz into eight-bit codes received 1 and 2 information inputs of block 12, which converts parallel codes into serial ones with the replacement of unit symbols from pulses by half-sine waves of the monofrequency 144 MHz / Fig. 1/. The information of the stereo pair codes is transmitted by the upper side frequency of the carrier to the receiving side. The receiving side (Fig. 5/) receives radio signals in a single path for the reception and processing of video signal codes, performs bipolar amplitude detection, extracts horizontal sync pulses / SSI / and stereo pair sync pulses / SIS /, returns the representation of the symbols in the half-sine codes to pulses and distributes the color signal codes R , B, G through their channels, in which doubling of samples in lines of 400 to 800 is performed. The storage codes 63, 67, 71 of the frame codes for the first frame period concentrate the right frame codes of the first stereo pair, which at the end of The frame odes are synchronously and parallelly transmitted to the control signal generation blocks 64, 68, 72, all codes in them are converted to the corresponding number of pulses energizing the LEDs of the LED screen 73. While the image of the right frame of the first stereo pair is displayed on screen 73, the frame code drives concentrate the codes left / second / frame of the first stereo pair. Then, the left frame is displayed on the screen, and the frame code storage devices receive the right frame codes of the second stereo pair; when playing the right frame of the second stereo pair, the drives receive the left frame codes of the second stereo pair. And so the processes go on repeating. Playable video mode 800 x 600 x 100 Hz. The viewer receives a three-dimensional image using 3D glasses 75 in conjunction with an IR transmitter 74 or without an IR transmitter with the IR receiver of the glasses connected by a switch 77 to the output of trigger 85. When playing back frames of the first stereo pair, the viewer perceives a stereo image of space at the first image scale with lenses 2 and 7/20 ms /, when playing back frames of the second stereo pair, the viewer perceives a stereo image of the same space with a different image scale with 2 and 7/20 ms / lenses, the result of the claimed method and television systems are reducing energy consumption by three times against the prototype and getting twice as much information for the brain to play the viewer three-dimensional space.

If the image scales in lenses 2 and 7 are not changed, the system works like the systems existing now and will reproduce a two-coordinate image on the SD screen with a frequency of 100 Hz.

Information sources

1. Patent No. 2232608 C1, cl. H04N 15/00, bull. No. 16 dated 06/10/08, prototype.

2. P.C. Magazine Personal computer today. No. 3/206 /, August, 2008

3. Kolesnichenko OV, Shishigin I.V. PC hardware. 5th ed., St. Petersburg, p. 588-565, 832, 835.

4. B.N. Begunov, I.P. Zakaznov. Theory of optical systems. M., 1973, p. 300.

5. Handbook amateur photographer. Ed. V.A. Iophis, M., 1964, p. 81-82 fig. 11, 40.

6. The journal "Instruments and control systems", No. 1, 1990, p.40.

7. Radio transmitting devices. M.S. Shumilin et al., M., 1981, p. 234, 235.

8. Patent No. 2316142, cl. H04N 15/00, bull. No. 3 dated 01/27/08, analogue, p.6. fig. 8

9. "Home computer", No. 12, 2006, p. 43.

10. Radio, No. 6, 2008, pp. 7-9, fig. 6a, b.

11. Radio communications, broadcasting and television. Ed. A.D. Fortushenko, M., 1981, p. 146.

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Claims (2)

1. A method of forming a three-dimensional image, which consists in sequentially performing operations on the transmitting side: obtaining two images of the same space with identical right and left lenses at the first image scale, generating codes of the first right and left frames of the first stereo pair sequentially with replacing units of pulses with positive ones in the codes and negative half-sinusoids of a monofrequency, a multiple of the carrier frequency and transmission of information of the codes of the first stereo pair of one of the side frequencies of the carrier frequency n transmitter, on the receiving side: receiving radio signals with the information of the codes of the first stereo pair, bipolar amplitude detection, returning unit symbols in half-sine waves to pulses and distributing the color signal codes (R, B, G) over their channels, filling in the right frame with three codes stores frame in the channels and the synchronous output of all frame codes for parallel conversion of each code into the corresponding number of pulses energizing the LEDs in the LED screen (SD screen), fill in the freed up ley of frame codes by codes of the left frame of the stereo pair, synchronous issuance of them for parallel conversion of the codes into the corresponding number of pulses energizing the LEDs in the LED screen, characterized in that the second image scale is set on the transmitting side synchronously in both lenses, the third and fourth images of the same space, codes of the right and left frames of the second stereo pair are formed with the replacement of unit symbols in them from pulses by positive and negative half-sinusoids of a single frequency multiple of the carrier frequency, and the information of the codes of the second stereo pair is transmitted sequentially after the first stereo pair, information of the second stereo pair is received on the receiving side of the first stereo pair, detected, unit symbols in the codes are returned from the half-sine waves to pulses, the color signal codes of the second stereo pair are distributed along the same channels after the first whose frame code drives, freed from the left frame codes of the first stereo pair, are filled with the right frame codes of the second stereo pair and are synchronously issued for parallel conversion When each code is converted into the corresponding number of pulses energizing the LEDs of the LED screen, the freed up drive codes of the frame are filled with the codes of the left frame of the second stereo pair and synchronously issued for parallel conversion of codes into the corresponding number of pulses energizing the corresponding LEDs in the LED screen. 2. A stereo television system comprising a transmitting side including a photoelectric converter (PEC) comprising first (right) and second (left) lenses and first to third pre-amplifiers, the outputs of which are the first to third outputs of the photoconductor, including the first to third ADCs of the video signal, the information inputs of which are connected to the outputs of the first to third pre-amplifiers, a code generator, to the first information input of which the output of the first ADC video signal is connected, the first and second AD sound signal, to the inputs of which sound signals are supplied, the output of the first ADC of the sound signal is connected to the corresponding information input of the code generator, serially connected sinusoidal oscillation generator and frequency synthesizer, the first and second self-propelled pulse distributors (SRI), the outputs of which are connected to the corresponding information inputs a driver of codes, from first to fifth keys, a first trigger and a radio signal transmitter comprising a carrier amplifier of a carrier in series the frequencies, the amplitude modulator and the output amplifier, the outputs of the frequency synthesizer are connected: the first - in parallel to the control inputs of the first to third ADCs of the video signal and to the first control input of the code generator, the third - to the second control inputs of the first and second ADCs of the sound, the fourth - to the corresponding control the input of the code generator, the fifth - to the third control inputs of the first and second ADCs of the sound signal and to the corresponding control input of the code generator, the first output of which is connected to the second input at the amplitude modulator of the radio signal transmitter, the input of the carrier frequency amplifier of which is connected to the corresponding output of the frequency synthesizer, the control input of the first SRI is connected to the second output of the code generator, the first output of the first trigger is connected in parallel to the first control inputs of the first and third keys, the second output of the first trigger is connected in parallel to the first control inputs of the second and fourth keys, the code generator includes three channels, the first and second channels are identical, the first channel including the first block of AND elements, the first and second OR elements, and the output key, and the first SRI, the second channel includes the second block of AND elements, the third and fourth OR elements, and the output key, and the second SRI, the third channel includes the third block of elements And, the fifth OR element, the output of which is connected to the second input of the second OR element, and the third SRI, includes the fourth block of AND elements, the sixth OR element, the output of which is connected to the second input of the fourth OR element, and the fourth SRI, form the code tree includes the first and second keys and a pulse counter and decoder connected in series, the second inputs of the element blocks And the first and second channels are connected to the outputs of the SRI of their channel, the second inputs of the third and fourth blocks of elements And are connected respectively to the outputs of the third and fourth SRI, the first output shaper codes are the combined outputs of both output keys, the output of the first key is connected to the inputs of the first and second SRI, the output of the second key is connected to the inputs of the third and fourth SRI, the first the decoder output is connected to the first control input of the first key, the second decoder output is connected to the second control input of the first key and to the first control input of the second key, the third decoder output is the second output of the code generator and connected to the input of the first SRI of the transmitting side, the control inputs of the code generator are : one - the combined signal inputs of the first and second keys and the counting input of the pulse counter, the other - the combined signal inputs of both output keys, the next - governing input (U _o ) a pulse counter, and containing the receiving side, including the antenna, a control unit (channel selection), a path for receiving and processing video signal codes, the input of which is connected to the antenna, a channel for generating control signals, a flat-panel LED screen (LED screen) and two sound reproduction channels , the path for receiving and processing codes of video signals contains a series-connected block for receiving radio signals, the first input of which is connected to the antenna, the second group of inputs is connected to the first group of outputs of the control unit, a radio frequency spruce and a bipolar amplitude detector, first and second pulse shapers connected respectively to the first and second outputs of the bipolar amplitude detector, the receiving side contains three channels of color signals R, B, G, each of which includes a register and a code processing unit connected in series and sequentially connected frame code storage unit and a control signal generation unit, the outputs of which are connected to the inputs of the SD screen, on the upper part of the housing of which an IR transmitter is located, the receiving side contains 3D glasses with an IR receiver on their frame, the input windows of the glasses when used are opposite the output window of the IR transmitter, the channel for generating control signals contains a sequentially connected block for selecting horizontal sync pulses (SSI), a frequency synthesizer, a first key, and a pulse counter and a decoder and a stereo pair clock allocation unit (SIS), the first input of the SSI selection block is connected to the output of the first pulse shaper, the first input of the SIS selection block is connected to the output of the second form pulse generator, the control input of the first key is connected to the output of the SSI allocation block, the signal input of the first key is connected to the first output of the frequency synthesizer, the second control input of the first key and the control input of the pulse counter are combined and connected to the second output of the decoder, the inputs of the frequency synthesizer are connected: the first - to the output of the SSI allocation block, the second group of inputs is connected to the second group of outputs of the control unit, the outputs of the frequency synthesizer are connected: the first to the control inputs of the code processing blocks, sec d - to the third control inputs of the sound reproduction channels, the fourth control inputs of which are connected to the third output of the frequency synthesizer, the fifth output of which is connected to the third input of the radio signal receiving unit, the information input of the first sound reproduction channel is connected to the output of the first pulse shaper, the first control inputs of the reproduction channels sound are connected to the first output of the decoder, the second output of which is connected to the second control inputs of both sound reproduction channels, blocks code processing is identical, each includes a trigger, the input of which is the control input of the block, from the first to sixth registers, a block of delay elements, an adder and 16 diodes, the control input of the adder is connected to the trigger input, the inputs of the first and second registers are bitwise combined, the inputs of the third and fourth registers are bitwise combined, the output of the first register is connected to the inputs of the fifth register and through diodes to the first inputs of the adder, to which the outputs of the second register are connected, the outputs of the third register are connected to the inputs sixth register and through diodes to the second inputs of the adder, to which the outputs of the fourth register are connected, the first output of the trigger is connected in parallel to the control inputs of the second, third, fifth registers, the second output of the trigger is connected to the control inputs of the first, fourth, sixth registers, the outputs of the adder connected to the corresponding inputs of the block of delay elements, the outputs of which and the outputs of the fifth and sixth registers are bitwise combined and are 1-8 outputs of the code processing unit, the frame code drives are identical, as each includes register blocks according to the number of lines of the frame, information inputs are bit-wise combined 1-8 inputs of register blocks, the first control input is the control input of the first block of registers, the second are the combined second control inputs of the register blocks, the third are the combined third control inputs of the register blocks of the same name the first, second, third control inputs of the drive codes of the frame are combined, each control output of the previous block of registers is connected to the first control input for each subsequent block of registers, the control output of the last block of registers is connected in parallel to the fourth control inputs of all register blocks, the outputs of the frame code storage are the parallel outputs of all register blocks that are connected to the inputs of the control signal generation block of its channel, the register blocks are identical, each contains the first and the second keys, the pulse distributor and eight registers, the information inputs are the bitwise combined third inputs of the bits of the eight registers c, the outputs of all bits of eight registers are the outputs of the register block, the first control input is the first control input of the first key, the second is the signal input of the second key, the third is the signal input of the first key, and the fourth is the first control input of the second key connected to the control output of the last block registers, the output of the first key is connected to the input of the pulse distributor, the outputs of which are sequentially, starting from the first, connected to the first control inputs of the bits in parallel to eight registers, the last output of the pulse distributor is connected to the second control input of the first key and is the control output of the register block, the output of the second key is connected in parallel to the second control inputs of the bits in parallel to eight registers and to the second control input of its key, the control signal generation blocks are identical, their control inputs are combined, the information inputs of each control signal generation block are connected to the corresponding outputs of the channel code frame storage channel, the LED screen is um from screen glass and matrix elements according to the number of screen resolutions, each matrix element includes three emitting LED cells (LED cells), each of which contains a white LED and a color filter of one of the primary colors R, B, G, screen glass by the number matrix elements has recesses in which three LED cells are placed, the inputs of the LED cells are connected to the corresponding outputs of the corresponding control signal generating units, characterized in that the first and second matrices are introduced on the transmitting side PZI (charge injection device), the photosensitive side of the first PZI matrix is located in the focal plane of the first lens, the photosensitive side of the second PZI matrix is located in the focal plane of the second lens, their first and third outputs are combined and connected to the inputs of the first and third pre-amplifiers , the first and second control inputs of the first FDI matrix are connected to the outputs of the first and third keys, the first and second control inputs of the second FDI matrix are connected to the output From the second and fourth keys, a zoom lens is introduced into each lens, containing the front and rear negative lenses and a positive lens placed between them and moving in the corresponding range, and a piezoelectric motor (PED) with the corresponding mechanism for moving the positive lens along the optical axis of the lens, on the transmitting side introduced a second trigger, the input of which is connected to the first output of the first trigger, the first output of the second trigger is connected in parallel to the first control inputs of the engines PED in the first and second lenses, the second output of the second trigger is connected in parallel to the second control inputs of the PED motors in the first and second lenses, the signal and control inputs of the fifth key are connected respectively to the second and sixth outputs of the frequency synthesizer, the output of the fifth key is connected to the input of the first trigger, the signal inputs of the first and third keys are combined and connected to the fifth output of the frequency synthesizer, the signal inputs of the second and fourth keys are combined and connected to the first output of the synthesizer , to the fourth output of which the second control input of the code generator is connected, the first and third control inputs of which are connected respectively to the first and fifth outputs of the frequency synthesizer, to the first output of which the first control inputs of the first and second ADCs of the sound signal are connected, the fourth output of the frequency synthesizer is connected control input of the code generator and input (U _P ) the second SRI, the first to twelfth outputs of which are combined and connected to the sixth information input of the code generator, to the fifth information input of which the combined first to twelfth outputs of the first SRI, the first to eighth outputs of the first ADC video signal and the first and fourth outputs of the second ADC video signal are connected to the first information input of the code generator, to the second information input of which the fifth-eighth outputs of the second ADC video signal and the first-eighth outputs of the third ADC video signal are connected Ala, the outputs of the first and second ADCs of the sound signal are connected to the third and fourth information inputs of the code generator, and the input of the transmitter / radio signal carrier frequency amplifier is connected to the seventh output of the frequency synthesizer, the third key is entered into the code generator, the signal input of which is the fifth information input and connected to the output of the first SRI of the transmitting side, the control input of the third key is the fourth control input, the output of the third key is connected to the third input of the second OR element, the first twelve inputs of the first block of elements And the first channel are the first information input of the code generator, the second information input of which is the first twelve inputs of the second block of elements And the second channel, the sixth information input of the code generator is the third input of the fourth element OR of the second channel, the first control input of the code generator is the combined signal inputs of the first and second keys and the counting input of the pulse counter, the second control input is combined signal inputs of the two output switches, the third control input is a control input (U ₀ ) pulse counter, the third output of the decoder is connected to the second control input of the second key of the code shaper, the first and second receiving registers are introduced on the receiving side, each of which contains twelve bits, the information input of the first receiving register is connected to the output of the first pulse shaper, the information input of the second the receiving register is connected to the output of the second code generator, the first and second control inputs of the same name of the first and second receiving registers are combined and connected to respectively, to the first and second outputs of the frequency synthesizer, the outputs of the first to eighth bits of the first receiving register are connected to the first to eighth inputs of the signal channel register R, the outputs of the ninth to twelfth bits of the first receiving register are connected to the first to fourth inputs of the bits of the signal channel register B, the outputs of the first - the eighth bits of the second receiving register are connected to the first to eighth inputs of the channel register of the signal G, the outputs of the ninth to twelfth bits of the second receiving register are connected to the inputs of one or eight bits of the signal channel B register, the second input of the SSI isolation block is connected to the output of the second pulse shaper, the second input of the SIS isolation block is connected to the output of the first pulse shaper, the second key, trigger and switch are connected in series to the control signal generation channel, signal input the second key is connected to the sixth output of the frequency synthesizer, the control input of the second key is connected to the output of the ICU allocation unit, the first control inputs of three frame code drives and the control inputs of the three control signal generating units are combined and connected to the output of the second key, the combined second and combined third control inputs of the three frame code drives are connected respectively to the fourth output of the frequency synthesizer and to the output of the SSI allocation block, the switch is connected to the second output of the trigger and has two positions , in the first position, the switch connects the second trigger output to the IR transmitter, in the second position, the switch connects the second trigger output to the IR receiver 3D point c, the information input of the second sound reproduction channel is connected to the output of the second pulse shaper, the control signal generation blocks are identical, each includes a pulse formation circuit block, the input of which is a control input (U _to ), and contains 48 × 10 pulse generation circuits, and includes code-to-number radiation pulses converters according to the frame resolution number 48 · 10 ^four / 800 × 600 /, each code-to-number of radiation pulses converter includes a decryptor connected in series, the first to eighth inputs of which are converter inputs, a key block of 255 keys and an output key whose output is the converter output includes a self-propelled pulse distributor (SRI ), containing 255 bits, and a power source, the output of which is connected to the signal input of the output key, 255 outputs of the decoder are connected to the first control 255 inputs of the key block, the control input (U _P ) SRI is connected to the corresponding output of the block of pulse generating circuits, the outputs of 255 bits of SRI are connected to the signal inputs of 255 keys in the key block, the outputs of which are combined and connected to the first control input of the output key, the information inputs of the control signal generation block are the inputs of all decoder decoders "code - the number of radiation pulses, "the outputs of the block are the outputs of all the output keys connected to the corresponding inputs of the LED screen, the SSI allocation unit and the SIS allocation unit are identical s, each includes a series-connected pulse counter and AND element, element NOT, first and second diodes, the information input is the counting input of the pulse counter, to which the input of the element is NOT connected, the control input is the input of the first diode, the output of which and the output of the element are NOT combined and connected to the control input of the pulse counter, the first and second outputs of the highest bits of which are connected to the inputs of the element And, the output of which is the output of the unit and through the second diode is connected to the output of the element NOT and to vlyayuschemu input U _o pulse counter, the information input of the SSI isolation block is connected to the output of the first pulse shaper, its control input is connected to the output of the second pulse shaper, the information input of the SIS allocation block is connected to the output of the second pulse shaper, its control input is connected to the output of the first pulse shaper.

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